3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include "skeleton.dtsi"
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
18 reg = <0x08000000 0x5100000>;
23 reg = <0x0d100000 0x100000>;
28 reg = <0x0d200000 0xa00000>;
33 reg = <0x0dc00000 0x1900000>;
38 reg = <0x0f500000 0x500000>;
42 smem_region: smem@fa00000 {
43 reg = <0xfa00000 0x200000>;
48 reg = <0x0fc00000 0x160000>;
53 reg = <0x0fd60000 0x1a0000>;
58 reg = <0x0ff00000 0x10100000>;
66 interrupts = <1 9 0xf04>;
69 compatible = "qcom,krait";
70 enable-method = "qcom,kpss-acc-v2";
73 next-level-cache = <&L2>;
76 cpu-idle-states = <&CPU_SPC>;
80 compatible = "qcom,krait";
81 enable-method = "qcom,kpss-acc-v2";
84 next-level-cache = <&L2>;
87 cpu-idle-states = <&CPU_SPC>;
91 compatible = "qcom,krait";
92 enable-method = "qcom,kpss-acc-v2";
95 next-level-cache = <&L2>;
98 cpu-idle-states = <&CPU_SPC>;
102 compatible = "qcom,krait";
103 enable-method = "qcom,kpss-acc-v2";
106 next-level-cache = <&L2>;
109 cpu-idle-states = <&CPU_SPC>;
113 compatible = "cache";
115 qcom,saw = <&saw_l2>;
120 compatible = "qcom,idle-state-spc",
122 entry-latency-us = <150>;
123 exit-latency-us = <200>;
124 min-residency-us = <2000>;
130 compatible = "qcom,krait-pmu";
131 interrupts = <1 7 0xf04>;
136 compatible = "fixed-clock";
138 clock-frequency = <19200000>;
142 compatible = "fixed-clock";
144 clock-frequency = <32768>;
149 compatible = "arm,armv7-timer";
150 interrupts = <1 2 0xf08>,
154 clock-frequency = <19200000>;
158 compatible = "qcom,smem";
160 memory-region = <&smem_region>;
161 qcom,rpm-msg-ram = <&rpm_msg_ram>;
163 hwlocks = <&tcsr_mutex 3>;
167 compatible = "qcom,smp2p";
168 qcom,smem = <451>, <431>;
170 interrupt-parent = <&intc>;
171 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
173 qcom,ipc = <&apcs 8 18>;
175 qcom,local-pid = <0>;
176 qcom,remote-pid = <4>;
178 wcnss_smp2p_out: master-kernel {
179 qcom,entry-name = "master-kernel";
181 #qcom,state-cells = <1>;
184 wcnss_smp2p_in: slave-kernel {
185 qcom,entry-name = "slave-kernel";
187 interrupt-controller;
188 #interrupt-cells = <2>;
193 compatible = "qcom,smsm";
195 #address-cells = <1>;
198 qcom,ipc-1 = <&apcs 8 13>;
199 qcom,ipc-2 = <&apcs 8 9>;
200 qcom,ipc-3 = <&apcs 8 19>;
205 #qcom,state-cells = <1>;
208 modem_smsm: modem@1 {
210 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
218 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
224 wcnss_smsm: wcnss@7 {
226 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
234 #address-cells = <1>;
237 compatible = "simple-bus";
239 intc: interrupt-controller@f9000000 {
240 compatible = "qcom,msm-qgic2";
241 interrupt-controller;
242 #interrupt-cells = <3>;
243 reg = <0xf9000000 0x1000>,
247 apcs: syscon@f9011000 {
248 compatible = "syscon";
249 reg = <0xf9011000 0x1000>;
253 #address-cells = <1>;
256 compatible = "arm,armv7-timer-mem";
257 reg = <0xf9020000 0x1000>;
258 clock-frequency = <19200000>;
262 interrupts = <0 8 0x4>,
264 reg = <0xf9021000 0x1000>,
270 interrupts = <0 9 0x4>;
271 reg = <0xf9023000 0x1000>;
277 interrupts = <0 10 0x4>;
278 reg = <0xf9024000 0x1000>;
284 interrupts = <0 11 0x4>;
285 reg = <0xf9025000 0x1000>;
291 interrupts = <0 12 0x4>;
292 reg = <0xf9026000 0x1000>;
298 interrupts = <0 13 0x4>;
299 reg = <0xf9027000 0x1000>;
305 interrupts = <0 14 0x4>;
306 reg = <0xf9028000 0x1000>;
311 saw0: power-controller@f9089000 {
312 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
313 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
316 saw1: power-controller@f9099000 {
317 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
318 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
321 saw2: power-controller@f90a9000 {
322 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
323 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
326 saw3: power-controller@f90b9000 {
327 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
328 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
331 saw_l2: power-controller@f9012000 {
332 compatible = "qcom,saw2";
333 reg = <0xf9012000 0x1000>;
337 acc0: clock-controller@f9088000 {
338 compatible = "qcom,kpss-acc-v2";
339 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
342 acc1: clock-controller@f9098000 {
343 compatible = "qcom,kpss-acc-v2";
344 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
347 acc2: clock-controller@f90a8000 {
348 compatible = "qcom,kpss-acc-v2";
349 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
352 acc3: clock-controller@f90b8000 {
353 compatible = "qcom,kpss-acc-v2";
354 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
358 compatible = "qcom,pshold";
359 reg = <0xfc4ab000 0x4>;
362 gcc: clock-controller@fc400000 {
363 compatible = "qcom,gcc-msm8974";
366 #power-domain-cells = <1>;
367 reg = <0xfc400000 0x4000>;
370 tcsr_mutex_block: syscon@fd484000 {
371 compatible = "syscon";
372 reg = <0xfd484000 0x2000>;
375 mmcc: clock-controller@fd8c0000 {
376 compatible = "qcom,mmcc-msm8974";
379 #power-domain-cells = <1>;
380 reg = <0xfd8c0000 0x6000>;
383 tcsr_mutex: tcsr-mutex {
384 compatible = "qcom,tcsr-mutex";
385 syscon = <&tcsr_mutex_block 0 0x80>;
390 rpm_msg_ram: memory@fc428000 {
391 compatible = "qcom,rpm-msg-ram";
392 reg = <0xfc428000 0x4000>;
395 blsp1_uart2: serial@f991e000 {
396 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
397 reg = <0xf991e000 0x1000>;
398 interrupts = <0 108 0x0>;
399 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", "iface";
405 compatible = "qcom,sdhci-msm-v4";
406 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
407 reg-names = "hc_mem", "core_mem";
408 interrupts = <0 123 0>, <0 138 0>;
409 interrupt-names = "hc_irq", "pwr_irq";
410 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
411 clock-names = "core", "iface";
416 compatible = "qcom,sdhci-msm-v4";
417 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
418 reg-names = "hc_mem", "core_mem";
419 interrupts = <0 125 0>, <0 221 0>;
420 interrupt-names = "hc_irq", "pwr_irq";
421 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
422 clock-names = "core", "iface";
427 compatible = "qcom,prng";
428 reg = <0xf9bff000 0x200>;
429 clocks = <&gcc GCC_PRNG_AHB_CLK>;
430 clock-names = "core";
433 msmgpio: pinctrl@fd510000 {
434 compatible = "qcom,msm8974-pinctrl";
435 reg = <0xfd510000 0x4000>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 interrupts = <0 208 0>;
443 blsp_i2c8: i2c@f9964000 {
445 compatible = "qcom,i2c-qup-v2.1.1";
446 reg = <0xf9964000 0x1000>;
447 interrupts = <0 102 IRQ_TYPE_NONE>;
448 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
449 clock-names = "core", "iface";
450 #address-cells = <1>;
454 blsp_i2c11: i2c@f9967000 {
456 compatible = "qcom,i2c-qup-v2.1.1";
457 reg = <0xf9967000 0x1000>;
458 interrupts = <0 105 IRQ_TYPE_NONE>;
459 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
460 clock-names = "core", "iface";
461 #address-cells = <1>;
463 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
464 dma-names = "tx", "rx";
467 spmi_bus: spmi@fc4cf000 {
468 compatible = "qcom,spmi-pmic-arb";
469 reg-names = "core", "intr", "cnfg";
470 reg = <0xfc4cf000 0x1000>,
473 interrupt-names = "periph_irq";
474 interrupts = <0 190 0>;
477 #address-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <4>;
483 blsp2_dma: dma-controller@f9944000 {
484 compatible = "qcom,bam-v1.4.0";
485 reg = <0xf9944000 0x19000>;
486 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
488 clock-names = "bam_clk";
495 compatible = "qcom,smd";
498 interrupts = <0 168 1>;
499 qcom,ipc = <&apcs 8 0>;
500 qcom,smd-edge = <15>;
503 compatible = "qcom,rpm-msm8974";
504 qcom,smd-channels = "rpm_requests";
507 compatible = "qcom,rpm-pm8841-regulators";
520 compatible = "qcom,rpm-pm8941-regulators";
552 pm8941_lvs1: lvs1 {};
553 pm8941_lvs2: lvs2 {};
554 pm8941_lvs3: lvs3 {};
556 pm8941_5vs1: 5vs1 {};
557 pm8941_5vs2: 5vs2 {};