arch/arm/boot/dts/r8a7779.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7779
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Simon Horman
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /include/ "skeleton.dtsi"
  13
  14 #include <dt-bindings/clock/r8a7779-clock.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 / {
  19         compatible = "renesas,r8a7779";
  20         interrupt-parent = <&gic>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <0>;
  30                         clock-frequency = <1000000000>;
  31                 };
  32                 cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a9";
  35                         reg = <1>;
  36                         clock-frequency = <1000000000>;
  37                 };
  38                 cpu@2 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a9";
  41                         reg = <2>;
  42                         clock-frequency = <1000000000>;
  43                 };
  44                 cpu@3 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a9";
  47                         reg = <3>;
  48                         clock-frequency = <1000000000>;
  49                 };
  50         };
  51
  52         aliases {
  53                 spi0 = &hspi0;
  54                 spi1 = &hspi1;
  55                 spi2 = &hspi2;
  56         };
  57
  58         gic: interrupt-controller@f0001000 {
  59                 compatible = "arm,cortex-a9-gic";
  60                 #interrupt-cells = <3>;
  61                 interrupt-controller;
  62                 reg = <0xf0001000 0x1000>,
  63                       <0xf0000100 0x100>;
  64         };
  65
  66         timer@f0000600 {
  67                 compatible = "arm,cortex-a9-twd-timer";
  68                 reg = <0xf0000600 0x20>;
  69                 interrupts = <GIC_PPI 13
  70                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  71                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  72         };
  73
  74         gpio0: gpio@ffc40000 {
  75                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  76                 reg = <0xffc40000 0x2c>;
  77                 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
  78                 #gpio-cells = <2>;
  79                 gpio-controller;
  80                 gpio-ranges = <&pfc 0 0 32>;
  81                 #interrupt-cells = <2>;
  82                 interrupt-controller;
  83         };
  84
  85         gpio1: gpio@ffc41000 {
  86                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  87                 reg = <0xffc41000 0x2c>;
  88                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
  89                 #gpio-cells = <2>;
  90                 gpio-controller;
  91                 gpio-ranges = <&pfc 0 32 32>;
  92                 #interrupt-cells = <2>;
  93                 interrupt-controller;
  94         };
  95
  96         gpio2: gpio@ffc42000 {
  97                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  98                 reg = <0xffc42000 0x2c>;
  99                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 64 32>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105         };
 106
 107         gpio3: gpio@ffc43000 {
 108                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 109                 reg = <0xffc43000 0x2c>;
 110                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 111                 #gpio-cells = <2>;
 112                 gpio-controller;
 113                 gpio-ranges = <&pfc 0 96 32>;
 114                 #interrupt-cells = <2>;
 115                 interrupt-controller;
 116         };
 117
 118         gpio4: gpio@ffc44000 {
 119                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 120                 reg = <0xffc44000 0x2c>;
 121                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 122                 #gpio-cells = <2>;
 123                 gpio-controller;
 124                 gpio-ranges = <&pfc 0 128 32>;
 125                 #interrupt-cells = <2>;
 126                 interrupt-controller;
 127         };
 128
 129         gpio5: gpio@ffc45000 {
 130                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 131                 reg = <0xffc45000 0x2c>;
 132                 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
 133                 #gpio-cells = <2>;
 134                 gpio-controller;
 135                 gpio-ranges = <&pfc 0 160 32>;
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138         };
 139
 140         gpio6: gpio@ffc46000 {
 141                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 142                 reg = <0xffc46000 0x2c>;
 143                 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
 144                 #gpio-cells = <2>;
 145                 gpio-controller;
 146                 gpio-ranges = <&pfc 0 192 9>;
 147                 #interrupt-cells = <2>;
 148                 interrupt-controller;
 149         };
 150
 151         irqpin0: interrupt-controller@fe78001c {
 152                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 153                 #interrupt-cells = <2>;
 154                 status = "disabled";
 155                 interrupt-controller;
 156                 reg = <0xfe78001c 4>,
 157                         <0xfe780010 4>,
 158                         <0xfe780024 4>,
 159                         <0xfe780044 4>,
 160                         <0xfe780064 4>,
 161                         <0xfe780000 4>;
 162                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
 163                               0 28 IRQ_TYPE_LEVEL_HIGH
 164                               0 29 IRQ_TYPE_LEVEL_HIGH
 165                               0 30 IRQ_TYPE_LEVEL_HIGH>;
 166                 sense-bitfield-width = <2>;
 167         };
 168
 169         i2c0: i2c@ffc70000 {
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172                 compatible = "renesas,i2c-r8a7779";
 173                 reg = <0xffc70000 0x1000>;
 174                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 176                 status = "disabled";
 177         };
 178
 179         i2c1: i2c@ffc71000 {
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 compatible = "renesas,i2c-r8a7779";
 183                 reg = <0xffc71000 0x1000>;
 184                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 186                 status = "disabled";
 187         };
 188
 189         i2c2: i2c@ffc72000 {
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 compatible = "renesas,i2c-r8a7779";
 193                 reg = <0xffc72000 0x1000>;
 194                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 196                 status = "disabled";
 197         };
 198
 199         i2c3: i2c@ffc73000 {
 200                 #address-cells = <1>;
 201                 #size-cells = <0>;
 202                 compatible = "renesas,i2c-r8a7779";
 203                 reg = <0xffc73000 0x1000>;
 204                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 206                 status = "disabled";
 207         };
 208
 209         scif0: serial@ffe40000 {
 210                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 211                 reg = <0xffe40000 0x100>;
 212                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
 214                 clock-names = "sci_ick";
 215                 status = "disabled";
 216         };
 217
 218         scif1: serial@ffe41000 {
 219                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 220                 reg = <0xffe41000 0x100>;
 221                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
 223                 clock-names = "sci_ick";
 224                 status = "disabled";
 225         };
 226
 227         scif2: serial@ffe42000 {
 228                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 229                 reg = <0xffe42000 0x100>;
 230                 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
 232                 clock-names = "sci_ick";
 233                 status = "disabled";
 234         };
 235
 236         scif3: serial@ffe43000 {
 237                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 238                 reg = <0xffe43000 0x100>;
 239                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
 241                 clock-names = "sci_ick";
 242                 status = "disabled";
 243         };
 244
 245         scif4: serial@ffe44000 {
 246                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 247                 reg = <0xffe44000 0x100>;
 248                 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
 250                 clock-names = "sci_ick";
 251                 status = "disabled";
 252         };
 253
 254         scif5: serial@ffe45000 {
 255                 compatible = "renesas,scif-r8a7779", "renesas,scif";
 256                 reg = <0xffe45000 0x100>;
 257                 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
 259                 clock-names = "sci_ick";
 260                 status = "disabled";
 261         };
 262
 263         pfc: pfc@fffc0000 {
 264                 compatible = "renesas,pfc-r8a7779";
 265                 reg = <0xfffc0000 0x23c>;
 266         };
 267
 268         thermal@ffc48000 {
 269                 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
 270                 reg = <0xffc48000 0x38>;
 271         };
 272
 273         tmu0: timer@ffd80000 {
 274                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 275                 reg = <0xffd80000 0x30>;
 276                 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
 277                              <0 33 IRQ_TYPE_LEVEL_HIGH>,
 278                              <0 34 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 280                 clock-names = "fck";
 281
 282                 #renesas,channels = <3>;
 283
 284                 status = "disabled";
 285         };
 286
 287         tmu1: timer@ffd81000 {
 288                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 289                 reg = <0xffd81000 0x30>;
 290                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
 291                              <0 37 IRQ_TYPE_LEVEL_HIGH>,
 292                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 294                 clock-names = "fck";
 295
 296                 #renesas,channels = <3>;
 297
 298                 status = "disabled";
 299         };
 300
 301         tmu2: timer@ffd82000 {
 302                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 303                 reg = <0xffd82000 0x30>;
 304                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
 305                              <0 41 IRQ_TYPE_LEVEL_HIGH>,
 306                              <0 42 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 308                 clock-names = "fck";
 309
 310                 #renesas,channels = <3>;
 311
 312                 status = "disabled";
 313         };
 314
 315         sata: sata@fc600000 {
 316                 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
 317                 reg = <0xfc600000 0x2000>;
 318                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 320         };
 321
 322         sdhi0: sd@ffe4c000 {
 323                 compatible = "renesas,sdhi-r8a7779";
 324                 reg = <0xffe4c000 0x100>;
 325                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 327                 status = "disabled";
 328         };
 329
 330         sdhi1: sd@ffe4d000 {
 331                 compatible = "renesas,sdhi-r8a7779";
 332                 reg = <0xffe4d000 0x100>;
 333                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 335                 status = "disabled";
 336         };
 337
 338         sdhi2: sd@ffe4e000 {
 339                 compatible = "renesas,sdhi-r8a7779";
 340                 reg = <0xffe4e000 0x100>;
 341                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 343                 status = "disabled";
 344         };
 345
 346         sdhi3: sd@ffe4f000 {
 347                 compatible = "renesas,sdhi-r8a7779";
 348                 reg = <0xffe4f000 0x100>;
 349                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 350                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 351                 status = "disabled";
 352         };
 353
 354         hspi0: spi@fffc7000 {
 355                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 356                 reg = <0xfffc7000 0x18>;
 357                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 361                 status = "disabled";
 362         };
 363
 364         hspi1: spi@fffc8000 {
 365                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 366                 reg = <0xfffc8000 0x18>;
 367                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 371                 status = "disabled";
 372         };
 373
 374         hspi2: spi@fffc6000 {
 375                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 376                 reg = <0xfffc6000 0x18>;
 377                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 381                 status = "disabled";
 382         };
 383
 384         du: display@fff80000 {
 385                 compatible = "renesas,du-r8a7779";
 386                 reg = <0 0xfff80000 0 0x40000>;
 387                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp1_clks R8A7779_CLK_DU>;
 389                 status = "disabled";
 390
 391                 ports {
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394
 395                         port@0 {
 396                                 reg = <0>;
 397                                 du_out_rgb0: endpoint {
 398                                 };
 399                         };
 400                         port@1 {
 401                                 reg = <1>;
 402                                 du_out_rgb1: endpoint {
 403                                 };
 404                         };
 405                 };
 406         };
 407
 408         clocks {
 409                 #address-cells = <1>;
 410                 #size-cells = <1>;
 411                 ranges;
 412
 413                 /* External root clock */
 414                 extal_clk: extal_clk {
 415                         compatible = "fixed-clock";
 416                         #clock-cells = <0>;
 417                         /* This value must be overriden by the board. */
 418                         clock-frequency = <0>;
 419                         clock-output-names = "extal";
 420                 };
 421
 422                 /* Special CPG clocks */
 423                 cpg_clocks: clocks@ffc80000 {
 424                         compatible = "renesas,r8a7779-cpg-clocks";
 425                         reg = <0xffc80000 0x30>;
 426                         clocks = <&extal_clk>;
 427                         #clock-cells = <1>;
 428                         clock-output-names = "plla", "z", "zs", "s",
 429                                              "s1", "p", "b", "out";
 430                 };
 431
 432                 /* Fixed factor clocks */
 433                 i_clk: i_clk {
 434                         compatible = "fixed-factor-clock";
 435                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 436                         #clock-cells = <0>;
 437                         clock-div = <2>;
 438                         clock-mult = <1>;
 439                         clock-output-names = "i";
 440                 };
 441                 s3_clk: s3_clk {
 442                         compatible = "fixed-factor-clock";
 443                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 444                         #clock-cells = <0>;
 445                         clock-div = <8>;
 446                         clock-mult = <1>;
 447                         clock-output-names = "s3";
 448                 };
 449                 s4_clk: s4_clk {
 450                         compatible = "fixed-factor-clock";
 451                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 452                         #clock-cells = <0>;
 453                         clock-div = <16>;
 454                         clock-mult = <1>;
 455                         clock-output-names = "s4";
 456                 };
 457                 g_clk: g_clk {
 458                         compatible = "fixed-factor-clock";
 459                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 460                         #clock-cells = <0>;
 461                         clock-div = <24>;
 462                         clock-mult = <1>;
 463                         clock-output-names = "g";
 464                 };
 465
 466                 /* Gate clocks */
 467                 mstp0_clks: clocks@ffc80030 {
 468                         compatible = "renesas,r8a7779-mstp-clocks",
 469                                      "renesas,cpg-mstp-clocks";
 470                         reg = <0xffc80030 4>;
 471                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 472                                  <&cpg_clocks R8A7779_CLK_P>,
 473                                  <&cpg_clocks R8A7779_CLK_P>,
 474                                  <&cpg_clocks R8A7779_CLK_P>,
 475                                  <&cpg_clocks R8A7779_CLK_S>,
 476                                  <&cpg_clocks R8A7779_CLK_S>,
 477                                  <&cpg_clocks R8A7779_CLK_P>,
 478                                  <&cpg_clocks R8A7779_CLK_P>,
 479                                  <&cpg_clocks R8A7779_CLK_P>,
 480                                  <&cpg_clocks R8A7779_CLK_P>,
 481                                  <&cpg_clocks R8A7779_CLK_P>,
 482                                  <&cpg_clocks R8A7779_CLK_P>,
 483                                  <&cpg_clocks R8A7779_CLK_P>,
 484                                  <&cpg_clocks R8A7779_CLK_P>,
 485                                  <&cpg_clocks R8A7779_CLK_P>,
 486                                  <&cpg_clocks R8A7779_CLK_P>;
 487                         #clock-cells = <1>;
 488                         clock-indices = <
 489                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 490                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 491                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 492                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 493                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 494                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 495                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 496                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 497                         >;
 498                         clock-output-names =
 499                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 500                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 501                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 502                                 "i2c0";
 503                 };
 504                 mstp1_clks: clocks@ffc80034 {
 505                         compatible = "renesas,r8a7779-mstp-clocks",
 506                                      "renesas,cpg-mstp-clocks";
 507                         reg = <0xffc80034 4>, <0xffc80044 4>;
 508                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 509                                  <&cpg_clocks R8A7779_CLK_P>,
 510                                  <&cpg_clocks R8A7779_CLK_S>,
 511                                  <&cpg_clocks R8A7779_CLK_S>,
 512                                  <&cpg_clocks R8A7779_CLK_S>,
 513                                  <&cpg_clocks R8A7779_CLK_S>,
 514                                  <&cpg_clocks R8A7779_CLK_P>,
 515                                  <&cpg_clocks R8A7779_CLK_P>,
 516                                  <&cpg_clocks R8A7779_CLK_P>,
 517                                  <&cpg_clocks R8A7779_CLK_S>;
 518                         #clock-cells = <1>;
 519                         clock-indices = <
 520                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 521                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 522                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 523                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 524                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 525                         >;
 526                         clock-output-names =
 527                                 "usb01", "usb2",
 528                                 "du", "vin2",
 529                                 "vin1", "vin0",
 530                                 "ether", "sata",
 531                                 "pcie", "vin3";
 532                 };
 533                 mstp3_clks: clocks@ffc8003c {
 534                         compatible = "renesas,r8a7779-mstp-clocks",
 535                                      "renesas,cpg-mstp-clocks";
 536                         reg = <0xffc8003c 4>;
 537                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 538                                  <&s4_clk>, <&s4_clk>;
 539                         #clock-cells = <1>;
 540                         clock-indices = <
 541                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 542                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 543                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 544                         >;
 545                         clock-output-names =
 546                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 547                                 "mmc1", "mmc0";
 548                 };
 549         };
 550 };