2 * Device Tree Source for Renesas r8a7779
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 /include/ "skeleton.dtsi"
14 #include <dt-bindings/clock/r8a7779-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
19 compatible = "renesas,r8a7779";
20 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a9";
30 clock-frequency = <1000000000>;
34 compatible = "arm,cortex-a9";
36 clock-frequency = <1000000000>;
40 compatible = "arm,cortex-a9";
42 clock-frequency = <1000000000>;
46 compatible = "arm,cortex-a9";
48 clock-frequency = <1000000000>;
58 gic: interrupt-controller@f0001000 {
59 compatible = "arm,cortex-a9-gic";
60 #interrupt-cells = <3>;
62 reg = <0xf0001000 0x1000>,
67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0xf0000600 0x20>;
69 interrupts = <GIC_PPI 13
70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
71 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
74 gpio0: gpio@ffc40000 {
75 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
76 reg = <0xffc40000 0x2c>;
77 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
80 gpio-ranges = <&pfc 0 0 32>;
81 #interrupt-cells = <2>;
85 gpio1: gpio@ffc41000 {
86 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
87 reg = <0xffc41000 0x2c>;
88 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
91 gpio-ranges = <&pfc 0 32 32>;
92 #interrupt-cells = <2>;
96 gpio2: gpio@ffc42000 {
97 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
98 reg = <0xffc42000 0x2c>;
99 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
102 gpio-ranges = <&pfc 0 64 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
107 gpio3: gpio@ffc43000 {
108 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
109 reg = <0xffc43000 0x2c>;
110 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
113 gpio-ranges = <&pfc 0 96 32>;
114 #interrupt-cells = <2>;
115 interrupt-controller;
118 gpio4: gpio@ffc44000 {
119 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
120 reg = <0xffc44000 0x2c>;
121 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
124 gpio-ranges = <&pfc 0 128 32>;
125 #interrupt-cells = <2>;
126 interrupt-controller;
129 gpio5: gpio@ffc45000 {
130 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
131 reg = <0xffc45000 0x2c>;
132 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
135 gpio-ranges = <&pfc 0 160 32>;
136 #interrupt-cells = <2>;
137 interrupt-controller;
140 gpio6: gpio@ffc46000 {
141 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
142 reg = <0xffc46000 0x2c>;
143 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
146 gpio-ranges = <&pfc 0 192 9>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
151 irqpin0: interrupt-controller@fe78001c {
152 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
153 #interrupt-cells = <2>;
155 interrupt-controller;
156 reg = <0xfe78001c 4>,
162 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
163 0 28 IRQ_TYPE_LEVEL_HIGH
164 0 29 IRQ_TYPE_LEVEL_HIGH
165 0 30 IRQ_TYPE_LEVEL_HIGH>;
166 sense-bitfield-width = <2>;
170 #address-cells = <1>;
172 compatible = "renesas,i2c-r8a7779";
173 reg = <0xffc70000 0x1000>;
174 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
180 #address-cells = <1>;
182 compatible = "renesas,i2c-r8a7779";
183 reg = <0xffc71000 0x1000>;
184 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
190 #address-cells = <1>;
192 compatible = "renesas,i2c-r8a7779";
193 reg = <0xffc72000 0x1000>;
194 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
200 #address-cells = <1>;
202 compatible = "renesas,i2c-r8a7779";
203 reg = <0xffc73000 0x1000>;
204 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
209 scif0: serial@ffe40000 {
210 compatible = "renesas,scif-r8a7779", "renesas,scif";
211 reg = <0xffe40000 0x100>;
212 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
214 clock-names = "sci_ick";
218 scif1: serial@ffe41000 {
219 compatible = "renesas,scif-r8a7779", "renesas,scif";
220 reg = <0xffe41000 0x100>;
221 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
223 clock-names = "sci_ick";
227 scif2: serial@ffe42000 {
228 compatible = "renesas,scif-r8a7779", "renesas,scif";
229 reg = <0xffe42000 0x100>;
230 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
232 clock-names = "sci_ick";
236 scif3: serial@ffe43000 {
237 compatible = "renesas,scif-r8a7779", "renesas,scif";
238 reg = <0xffe43000 0x100>;
239 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
241 clock-names = "sci_ick";
245 scif4: serial@ffe44000 {
246 compatible = "renesas,scif-r8a7779", "renesas,scif";
247 reg = <0xffe44000 0x100>;
248 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
250 clock-names = "sci_ick";
254 scif5: serial@ffe45000 {
255 compatible = "renesas,scif-r8a7779", "renesas,scif";
256 reg = <0xffe45000 0x100>;
257 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
259 clock-names = "sci_ick";
264 compatible = "renesas,pfc-r8a7779";
265 reg = <0xfffc0000 0x23c>;
269 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
270 reg = <0xffc48000 0x38>;
273 tmu0: timer@ffd80000 {
274 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
275 reg = <0xffd80000 0x30>;
276 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
277 <0 33 IRQ_TYPE_LEVEL_HIGH>,
278 <0 34 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
282 #renesas,channels = <3>;
287 tmu1: timer@ffd81000 {
288 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
289 reg = <0xffd81000 0x30>;
290 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
291 <0 37 IRQ_TYPE_LEVEL_HIGH>,
292 <0 38 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
296 #renesas,channels = <3>;
301 tmu2: timer@ffd82000 {
302 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
303 reg = <0xffd82000 0x30>;
304 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
305 <0 41 IRQ_TYPE_LEVEL_HIGH>,
306 <0 42 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
310 #renesas,channels = <3>;
315 sata: sata@fc600000 {
316 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
317 reg = <0xfc600000 0x2000>;
318 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
323 compatible = "renesas,sdhi-r8a7779";
324 reg = <0xffe4c000 0x100>;
325 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
331 compatible = "renesas,sdhi-r8a7779";
332 reg = <0xffe4d000 0x100>;
333 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
339 compatible = "renesas,sdhi-r8a7779";
340 reg = <0xffe4e000 0x100>;
341 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
347 compatible = "renesas,sdhi-r8a7779";
348 reg = <0xffe4f000 0x100>;
349 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
354 hspi0: spi@fffc7000 {
355 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
356 reg = <0xfffc7000 0x18>;
357 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
360 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
364 hspi1: spi@fffc8000 {
365 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
366 reg = <0xfffc8000 0x18>;
367 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
370 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
374 hspi2: spi@fffc6000 {
375 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
376 reg = <0xfffc6000 0x18>;
377 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
384 du: display@fff80000 {
385 compatible = "renesas,du-r8a7779";
386 reg = <0 0xfff80000 0 0x40000>;
387 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp1_clks R8A7779_CLK_DU>;
392 #address-cells = <1>;
397 du_out_rgb0: endpoint {
402 du_out_rgb1: endpoint {
409 #address-cells = <1>;
413 /* External root clock */
414 extal_clk: extal_clk {
415 compatible = "fixed-clock";
417 /* This value must be overriden by the board. */
418 clock-frequency = <0>;
419 clock-output-names = "extal";
422 /* Special CPG clocks */
423 cpg_clocks: clocks@ffc80000 {
424 compatible = "renesas,r8a7779-cpg-clocks";
425 reg = <0xffc80000 0x30>;
426 clocks = <&extal_clk>;
428 clock-output-names = "plla", "z", "zs", "s",
429 "s1", "p", "b", "out";
432 /* Fixed factor clocks */
434 compatible = "fixed-factor-clock";
435 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
439 clock-output-names = "i";
442 compatible = "fixed-factor-clock";
443 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
447 clock-output-names = "s3";
450 compatible = "fixed-factor-clock";
451 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
455 clock-output-names = "s4";
458 compatible = "fixed-factor-clock";
459 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
463 clock-output-names = "g";
467 mstp0_clks: clocks@ffc80030 {
468 compatible = "renesas,r8a7779-mstp-clocks",
469 "renesas,cpg-mstp-clocks";
470 reg = <0xffc80030 4>;
471 clocks = <&cpg_clocks R8A7779_CLK_S>,
472 <&cpg_clocks R8A7779_CLK_P>,
473 <&cpg_clocks R8A7779_CLK_P>,
474 <&cpg_clocks R8A7779_CLK_P>,
475 <&cpg_clocks R8A7779_CLK_S>,
476 <&cpg_clocks R8A7779_CLK_S>,
477 <&cpg_clocks R8A7779_CLK_P>,
478 <&cpg_clocks R8A7779_CLK_P>,
479 <&cpg_clocks R8A7779_CLK_P>,
480 <&cpg_clocks R8A7779_CLK_P>,
481 <&cpg_clocks R8A7779_CLK_P>,
482 <&cpg_clocks R8A7779_CLK_P>,
483 <&cpg_clocks R8A7779_CLK_P>,
484 <&cpg_clocks R8A7779_CLK_P>,
485 <&cpg_clocks R8A7779_CLK_P>,
486 <&cpg_clocks R8A7779_CLK_P>;
489 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
490 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
491 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
492 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
493 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
494 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
495 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
496 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
499 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
500 "hscif0", "scif5", "scif4", "scif3", "scif2",
501 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
504 mstp1_clks: clocks@ffc80034 {
505 compatible = "renesas,r8a7779-mstp-clocks",
506 "renesas,cpg-mstp-clocks";
507 reg = <0xffc80034 4>, <0xffc80044 4>;
508 clocks = <&cpg_clocks R8A7779_CLK_P>,
509 <&cpg_clocks R8A7779_CLK_P>,
510 <&cpg_clocks R8A7779_CLK_S>,
511 <&cpg_clocks R8A7779_CLK_S>,
512 <&cpg_clocks R8A7779_CLK_S>,
513 <&cpg_clocks R8A7779_CLK_S>,
514 <&cpg_clocks R8A7779_CLK_P>,
515 <&cpg_clocks R8A7779_CLK_P>,
516 <&cpg_clocks R8A7779_CLK_P>,
517 <&cpg_clocks R8A7779_CLK_S>;
520 R8A7779_CLK_USB01 R8A7779_CLK_USB2
521 R8A7779_CLK_DU R8A7779_CLK_VIN2
522 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
523 R8A7779_CLK_ETHER R8A7779_CLK_SATA
524 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
533 mstp3_clks: clocks@ffc8003c {
534 compatible = "renesas,r8a7779-mstp-clocks",
535 "renesas,cpg-mstp-clocks";
536 reg = <0xffc8003c 4>;
537 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
538 <&s4_clk>, <&s4_clk>;
541 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
542 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
543 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
546 "sdhi3", "sdhi2", "sdhi1", "sdhi0",