2 * Device Tree Source for Renesas r8a7779
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 /include/ "skeleton.dtsi"
14 #include <dt-bindings/clock/r8a7779-clock.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7779";
19 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a9";
29 clock-frequency = <1000000000>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <1000000000>;
39 compatible = "arm,cortex-a9";
41 clock-frequency = <1000000000>;
45 compatible = "arm,cortex-a9";
47 clock-frequency = <1000000000>;
57 gic: interrupt-controller@f0001000 {
58 compatible = "arm,cortex-a9-gic";
59 #interrupt-cells = <3>;
61 reg = <0xf0001000 0x1000>,
65 gpio0: gpio@ffc40000 {
66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
67 reg = <0xffc40000 0x2c>;
68 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
76 gpio1: gpio@ffc41000 {
77 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
78 reg = <0xffc41000 0x2c>;
79 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
82 gpio-ranges = <&pfc 0 32 32>;
83 #interrupt-cells = <2>;
87 gpio2: gpio@ffc42000 {
88 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
89 reg = <0xffc42000 0x2c>;
90 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
93 gpio-ranges = <&pfc 0 64 32>;
94 #interrupt-cells = <2>;
98 gpio3: gpio@ffc43000 {
99 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
100 reg = <0xffc43000 0x2c>;
101 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
104 gpio-ranges = <&pfc 0 96 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
109 gpio4: gpio@ffc44000 {
110 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
111 reg = <0xffc44000 0x2c>;
112 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
115 gpio-ranges = <&pfc 0 128 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
120 gpio5: gpio@ffc45000 {
121 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
122 reg = <0xffc45000 0x2c>;
123 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
126 gpio-ranges = <&pfc 0 160 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
131 gpio6: gpio@ffc46000 {
132 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
133 reg = <0xffc46000 0x2c>;
134 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
137 gpio-ranges = <&pfc 0 192 9>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
142 irqpin0: irqpin@fe780010 {
143 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
144 #interrupt-cells = <2>;
146 interrupt-controller;
147 reg = <0xfe78001c 4>,
152 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
153 0 28 IRQ_TYPE_LEVEL_HIGH
154 0 29 IRQ_TYPE_LEVEL_HIGH
155 0 30 IRQ_TYPE_LEVEL_HIGH>;
156 sense-bitfield-width = <2>;
160 #address-cells = <1>;
162 compatible = "renesas,i2c-r8a7779";
163 reg = <0xffc70000 0x1000>;
164 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
170 #address-cells = <1>;
172 compatible = "renesas,i2c-r8a7779";
173 reg = <0xffc71000 0x1000>;
174 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
180 #address-cells = <1>;
182 compatible = "renesas,i2c-r8a7779";
183 reg = <0xffc72000 0x1000>;
184 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
190 #address-cells = <1>;
192 compatible = "renesas,i2c-r8a7779";
193 reg = <0xffc73000 0x1000>;
194 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>;
202 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cpg_clocks R8A7779_CLK_P>;
204 clock-names = "sci_ick";
208 scif1: serial@ffe41000 {
209 compatible = "renesas,scif-r8a7779", "renesas,scif";
210 reg = <0xffe41000 0x100>;
211 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cpg_clocks R8A7779_CLK_P>;
213 clock-names = "sci_ick";
217 scif2: serial@ffe42000 {
218 compatible = "renesas,scif-r8a7779", "renesas,scif";
219 reg = <0xffe42000 0x100>;
220 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cpg_clocks R8A7779_CLK_P>;
222 clock-names = "sci_ick";
226 scif3: serial@ffe43000 {
227 compatible = "renesas,scif-r8a7779", "renesas,scif";
228 reg = <0xffe43000 0x100>;
229 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cpg_clocks R8A7779_CLK_P>;
231 clock-names = "sci_ick";
235 scif4: serial@ffe44000 {
236 compatible = "renesas,scif-r8a7779", "renesas,scif";
237 reg = <0xffe44000 0x100>;
238 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpg_clocks R8A7779_CLK_P>;
240 clock-names = "sci_ick";
244 scif5: serial@ffe45000 {
245 compatible = "renesas,scif-r8a7779", "renesas,scif";
246 reg = <0xffe45000 0x100>;
247 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cpg_clocks R8A7779_CLK_P>;
249 clock-names = "sci_ick";
254 compatible = "renesas,pfc-r8a7779";
255 reg = <0xfffc0000 0x23c>;
259 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
260 reg = <0xffc48000 0x38>;
263 tmu0: timer@ffd80000 {
264 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
265 reg = <0xffd80000 0x30>;
266 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
267 <0 33 IRQ_TYPE_LEVEL_HIGH>,
268 <0 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
272 #renesas,channels = <3>;
277 tmu1: timer@ffd81000 {
278 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
279 reg = <0xffd81000 0x30>;
280 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
281 <0 37 IRQ_TYPE_LEVEL_HIGH>,
282 <0 38 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
286 #renesas,channels = <3>;
291 tmu2: timer@ffd82000 {
292 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
293 reg = <0xffd82000 0x30>;
294 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
295 <0 41 IRQ_TYPE_LEVEL_HIGH>,
296 <0 42 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
300 #renesas,channels = <3>;
305 sata: sata@fc600000 {
306 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
307 reg = <0xfc600000 0x2000>;
308 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
313 compatible = "renesas,sdhi-r8a7779";
314 reg = <0xffe4c000 0x100>;
315 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
321 compatible = "renesas,sdhi-r8a7779";
322 reg = <0xffe4d000 0x100>;
323 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
329 compatible = "renesas,sdhi-r8a7779";
330 reg = <0xffe4e000 0x100>;
331 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
337 compatible = "renesas,sdhi-r8a7779";
338 reg = <0xffe4f000 0x100>;
339 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
344 hspi0: spi@fffc7000 {
345 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
346 reg = <0xfffc7000 0x18>;
347 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
350 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
354 hspi1: spi@fffc8000 {
355 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
356 reg = <0xfffc8000 0x18>;
357 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
360 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
364 hspi2: spi@fffc6000 {
365 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
366 reg = <0xfffc6000 0x18>;
367 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
370 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
374 du: display@fff80000 {
375 compatible = "renesas,du-r8a7779";
376 reg = <0 0xfff80000 0 0x40000>;
377 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp1_clks R8A7779_CLK_DU>;
382 #address-cells = <1>;
387 du_out_rgb0: endpoint {
392 du_out_rgb1: endpoint {
399 #address-cells = <1>;
403 /* External root clock */
404 extal_clk: extal_clk {
405 compatible = "fixed-clock";
407 /* This value must be overriden by the board. */
408 clock-frequency = <0>;
409 clock-output-names = "extal";
412 /* Special CPG clocks */
413 cpg_clocks: clocks@ffc80000 {
414 compatible = "renesas,r8a7779-cpg-clocks";
415 reg = <0xffc80000 0x30>;
416 clocks = <&extal_clk>;
418 clock-output-names = "plla", "z", "zs", "s",
419 "s1", "p", "b", "out";
422 /* Fixed factor clocks */
424 compatible = "fixed-factor-clock";
425 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
429 clock-output-names = "i";
432 compatible = "fixed-factor-clock";
433 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
437 clock-output-names = "s3";
440 compatible = "fixed-factor-clock";
441 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
445 clock-output-names = "s4";
448 compatible = "fixed-factor-clock";
449 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
453 clock-output-names = "g";
457 mstp0_clks: clocks@ffc80030 {
458 compatible = "renesas,r8a7779-mstp-clocks",
459 "renesas,cpg-mstp-clocks";
460 reg = <0xffc80030 4>;
461 clocks = <&cpg_clocks R8A7779_CLK_S>,
462 <&cpg_clocks R8A7779_CLK_P>,
463 <&cpg_clocks R8A7779_CLK_P>,
464 <&cpg_clocks R8A7779_CLK_P>,
465 <&cpg_clocks R8A7779_CLK_S>,
466 <&cpg_clocks R8A7779_CLK_S>,
467 <&cpg_clocks R8A7779_CLK_S1>,
468 <&cpg_clocks R8A7779_CLK_S1>,
469 <&cpg_clocks R8A7779_CLK_S1>,
470 <&cpg_clocks R8A7779_CLK_S1>,
471 <&cpg_clocks R8A7779_CLK_S1>,
472 <&cpg_clocks R8A7779_CLK_S1>,
473 <&cpg_clocks R8A7779_CLK_P>,
474 <&cpg_clocks R8A7779_CLK_P>,
475 <&cpg_clocks R8A7779_CLK_P>,
476 <&cpg_clocks R8A7779_CLK_P>;
478 renesas,clock-indices = <
479 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
480 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
481 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
482 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
483 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
484 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
485 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
486 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
489 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
490 "hscif0", "scif5", "scif4", "scif3", "scif2",
491 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
494 mstp1_clks: clocks@ffc80034 {
495 compatible = "renesas,r8a7779-mstp-clocks",
496 "renesas,cpg-mstp-clocks";
497 reg = <0xffc80034 4>, <0xffc80044 4>;
498 clocks = <&cpg_clocks R8A7779_CLK_P>,
499 <&cpg_clocks R8A7779_CLK_P>,
500 <&cpg_clocks R8A7779_CLK_S>,
501 <&cpg_clocks R8A7779_CLK_S>,
502 <&cpg_clocks R8A7779_CLK_S>,
503 <&cpg_clocks R8A7779_CLK_S>,
504 <&cpg_clocks R8A7779_CLK_P>,
505 <&cpg_clocks R8A7779_CLK_P>,
506 <&cpg_clocks R8A7779_CLK_P>,
507 <&cpg_clocks R8A7779_CLK_S>;
509 renesas,clock-indices = <
510 R8A7779_CLK_USB01 R8A7779_CLK_USB2
511 R8A7779_CLK_DU R8A7779_CLK_VIN2
512 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
513 R8A7779_CLK_ETHER R8A7779_CLK_SATA
514 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
523 mstp3_clks: clocks@ffc8003c {
524 compatible = "renesas,r8a7779-mstp-clocks",
525 "renesas,cpg-mstp-clocks";
526 reg = <0xffc8003c 4>;
527 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
528 <&s4_clk>, <&s4_clk>;
530 renesas,clock-indices = <
531 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
532 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
533 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
536 "sdhi3", "sdhi2", "sdhi1", "sdhi0",