2 * Device Tree Source for the r8a7790 SoC
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <dt-bindings/clock/r8a7790-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
49 compatible = "arm,cortex-a15";
51 clock-frequency = <1300000000>;
52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
55 next-level-cache = <&L2_CA15>;
57 /* kHz - uV - OPPs unknown yet */
58 operating-points = <1400000 1000000>,
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1300000000>;
71 next-level-cache = <&L2_CA15>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1300000000>;
79 next-level-cache = <&L2_CA15>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1300000000>;
87 next-level-cache = <&L2_CA15>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <780000000>;
95 next-level-cache = <&L2_CA7>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <780000000>;
103 next-level-cache = <&L2_CA7>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <780000000>;
111 next-level-cache = <&L2_CA7>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <780000000>;
119 next-level-cache = <&L2_CA7>;
124 cpu_thermal: cpu-thermal {
125 polling-delay-passive = <0>;
128 thermal-sensors = <&thermal>;
132 temperature = <115000>;
142 L2_CA15: cache-controller@0 {
143 compatible = "cache";
148 L2_CA7: cache-controller@1 {
149 compatible = "cache";
154 gic: interrupt-controller@f1001000 {
155 compatible = "arm,gic-400";
156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
159 reg = <0 0xf1001000 0 0x1000>,
160 <0 0xf1002000 0 0x1000>,
161 <0 0xf1004000 0 0x2000>,
162 <0 0xf1006000 0 0x2000>;
163 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
166 gpio0: gpio@e6050000 {
167 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
168 reg = <0 0xe6050000 0 0x50>;
169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 gpio-ranges = <&pfc 0 0 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
176 power-domains = <&cpg_clocks>;
179 gpio1: gpio@e6051000 {
180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
181 reg = <0 0xe6051000 0 0x50>;
182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
185 gpio-ranges = <&pfc 0 32 30>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
188 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
189 power-domains = <&cpg_clocks>;
192 gpio2: gpio@e6052000 {
193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
194 reg = <0 0xe6052000 0 0x50>;
195 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
198 gpio-ranges = <&pfc 0 64 30>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
202 power-domains = <&cpg_clocks>;
205 gpio3: gpio@e6053000 {
206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
207 reg = <0 0xe6053000 0 0x50>;
208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
211 gpio-ranges = <&pfc 0 96 32>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
215 power-domains = <&cpg_clocks>;
218 gpio4: gpio@e6054000 {
219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
220 reg = <0 0xe6054000 0 0x50>;
221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
224 gpio-ranges = <&pfc 0 128 32>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
228 power-domains = <&cpg_clocks>;
231 gpio5: gpio@e6055000 {
232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
233 reg = <0 0xe6055000 0 0x50>;
234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
237 gpio-ranges = <&pfc 0 160 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
241 power-domains = <&cpg_clocks>;
244 thermal: thermal@e61f0000 {
245 compatible = "renesas,thermal-r8a7790",
246 "renesas,rcar-gen2-thermal",
247 "renesas,rcar-thermal";
248 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
251 power-domains = <&cpg_clocks>;
252 #thermal-sensor-cells = <0>;
256 compatible = "arm,armv7-timer";
257 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
258 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
260 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
263 cmt0: timer@ffca0000 {
264 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
265 reg = <0 0xffca0000 0 0x1004>;
266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
270 power-domains = <&cpg_clocks>;
272 renesas,channels-mask = <0x60>;
277 cmt1: timer@e6130000 {
278 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
279 reg = <0 0xe6130000 0 0x1004>;
280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
290 power-domains = <&cpg_clocks>;
292 renesas,channels-mask = <0xff>;
297 irqc0: interrupt-controller@e61c0000 {
298 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
299 #interrupt-cells = <2>;
300 interrupt-controller;
301 reg = <0 0xe61c0000 0 0x200>;
302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
307 power-domains = <&cpg_clocks>;
310 dmac0: dma-controller@e6700000 {
311 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
312 reg = <0 0xe6700000 0 0x20000>;
313 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-names = "error",
330 "ch0", "ch1", "ch2", "ch3",
331 "ch4", "ch5", "ch6", "ch7",
332 "ch8", "ch9", "ch10", "ch11",
333 "ch12", "ch13", "ch14";
334 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
336 power-domains = <&cpg_clocks>;
341 dmac1: dma-controller@e6720000 {
342 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
343 reg = <0 0xe6720000 0 0x20000>;
344 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "error",
361 "ch0", "ch1", "ch2", "ch3",
362 "ch4", "ch5", "ch6", "ch7",
363 "ch8", "ch9", "ch10", "ch11",
364 "ch12", "ch13", "ch14";
365 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
367 power-domains = <&cpg_clocks>;
372 audma0: dma-controller@ec700000 {
373 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
374 reg = <0 0xec700000 0 0x10000>;
375 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "error",
390 "ch0", "ch1", "ch2", "ch3",
391 "ch4", "ch5", "ch6", "ch7",
392 "ch8", "ch9", "ch10", "ch11",
394 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
396 power-domains = <&cpg_clocks>;
401 audma1: dma-controller@ec720000 {
402 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
403 reg = <0 0xec720000 0 0x10000>;
404 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "error",
419 "ch0", "ch1", "ch2", "ch3",
420 "ch4", "ch5", "ch6", "ch7",
421 "ch8", "ch9", "ch10", "ch11",
423 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
425 power-domains = <&cpg_clocks>;
430 usb_dmac0: dma-controller@e65a0000 {
431 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
432 reg = <0 0xe65a0000 0 0x100>;
433 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "ch0", "ch1";
436 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
437 power-domains = <&cpg_clocks>;
442 usb_dmac1: dma-controller@e65b0000 {
443 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
444 reg = <0 0xe65b0000 0 0x100>;
445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "ch0", "ch1";
448 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
449 power-domains = <&cpg_clocks>;
455 #address-cells = <1>;
457 compatible = "renesas,i2c-r8a7790";
458 reg = <0 0xe6508000 0 0x40>;
459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
461 power-domains = <&cpg_clocks>;
462 i2c-scl-internal-delay-ns = <110>;
467 #address-cells = <1>;
469 compatible = "renesas,i2c-r8a7790";
470 reg = <0 0xe6518000 0 0x40>;
471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
473 power-domains = <&cpg_clocks>;
474 i2c-scl-internal-delay-ns = <6>;
479 #address-cells = <1>;
481 compatible = "renesas,i2c-r8a7790";
482 reg = <0 0xe6530000 0 0x40>;
483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
485 power-domains = <&cpg_clocks>;
486 i2c-scl-internal-delay-ns = <6>;
491 #address-cells = <1>;
493 compatible = "renesas,i2c-r8a7790";
494 reg = <0 0xe6540000 0 0x40>;
495 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
497 power-domains = <&cpg_clocks>;
498 i2c-scl-internal-delay-ns = <110>;
503 #address-cells = <1>;
505 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
506 reg = <0 0xe6500000 0 0x425>;
507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
509 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
510 dma-names = "tx", "rx";
511 power-domains = <&cpg_clocks>;
516 #address-cells = <1>;
518 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
519 reg = <0 0xe6510000 0 0x425>;
520 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
522 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
523 dma-names = "tx", "rx";
524 power-domains = <&cpg_clocks>;
529 #address-cells = <1>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6520000 0 0x425>;
533 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
535 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
536 dma-names = "tx", "rx";
537 power-domains = <&cpg_clocks>;
542 #address-cells = <1>;
544 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
545 reg = <0 0xe60b0000 0 0x425>;
546 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
548 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
549 dma-names = "tx", "rx";
550 power-domains = <&cpg_clocks>;
554 mmcif0: mmc@ee200000 {
555 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
556 reg = <0 0xee200000 0 0x80>;
557 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
560 dma-names = "tx", "rx";
561 power-domains = <&cpg_clocks>;
564 max-frequency = <97500000>;
567 mmcif1: mmc@ee220000 {
568 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
569 reg = <0 0xee220000 0 0x80>;
570 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
572 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
573 dma-names = "tx", "rx";
574 power-domains = <&cpg_clocks>;
577 max-frequency = <97500000>;
581 compatible = "renesas,pfc-r8a7790";
582 reg = <0 0xe6060000 0 0x250>;
586 compatible = "renesas,sdhi-r8a7790";
587 reg = <0 0xee100000 0 0x328>;
588 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx";
592 power-domains = <&cpg_clocks>;
597 compatible = "renesas,sdhi-r8a7790";
598 reg = <0 0xee120000 0 0x328>;
599 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
601 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
602 dma-names = "tx", "rx";
603 power-domains = <&cpg_clocks>;
608 compatible = "renesas,sdhi-r8a7790";
609 reg = <0 0xee140000 0 0x100>;
610 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
612 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
613 dma-names = "tx", "rx";
614 power-domains = <&cpg_clocks>;
619 compatible = "renesas,sdhi-r8a7790";
620 reg = <0 0xee160000 0 0x100>;
621 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
623 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
624 dma-names = "tx", "rx";
625 power-domains = <&cpg_clocks>;
629 scifa0: serial@e6c40000 {
630 compatible = "renesas,scifa-r8a7790",
631 "renesas,rcar-gen2-scifa", "renesas,scifa";
632 reg = <0 0xe6c40000 0 64>;
633 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
636 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
637 dma-names = "tx", "rx";
638 power-domains = <&cpg_clocks>;
642 scifa1: serial@e6c50000 {
643 compatible = "renesas,scifa-r8a7790",
644 "renesas,rcar-gen2-scifa", "renesas,scifa";
645 reg = <0 0xe6c50000 0 64>;
646 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
649 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
650 dma-names = "tx", "rx";
651 power-domains = <&cpg_clocks>;
655 scifa2: serial@e6c60000 {
656 compatible = "renesas,scifa-r8a7790",
657 "renesas,rcar-gen2-scifa", "renesas,scifa";
658 reg = <0 0xe6c60000 0 64>;
659 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
662 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
663 dma-names = "tx", "rx";
664 power-domains = <&cpg_clocks>;
668 scifb0: serial@e6c20000 {
669 compatible = "renesas,scifb-r8a7790",
670 "renesas,rcar-gen2-scifb", "renesas,scifb";
671 reg = <0 0xe6c20000 0 64>;
672 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
675 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
676 dma-names = "tx", "rx";
677 power-domains = <&cpg_clocks>;
681 scifb1: serial@e6c30000 {
682 compatible = "renesas,scifb-r8a7790",
683 "renesas,rcar-gen2-scifb", "renesas,scifb";
684 reg = <0 0xe6c30000 0 64>;
685 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
688 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
689 dma-names = "tx", "rx";
690 power-domains = <&cpg_clocks>;
694 scifb2: serial@e6ce0000 {
695 compatible = "renesas,scifb-r8a7790",
696 "renesas,rcar-gen2-scifb", "renesas,scifb";
697 reg = <0 0xe6ce0000 0 64>;
698 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
701 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
702 dma-names = "tx", "rx";
703 power-domains = <&cpg_clocks>;
707 scif0: serial@e6e60000 {
708 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
710 reg = <0 0xe6e60000 0 64>;
711 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
714 clock-names = "fck", "brg_int", "scif_clk";
715 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
716 dma-names = "tx", "rx";
717 power-domains = <&cpg_clocks>;
721 scif1: serial@e6e68000 {
722 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
724 reg = <0 0xe6e68000 0 64>;
725 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
728 clock-names = "fck", "brg_int", "scif_clk";
729 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
730 dma-names = "tx", "rx";
731 power-domains = <&cpg_clocks>;
735 hscif0: serial@e62c0000 {
736 compatible = "renesas,hscif-r8a7790",
737 "renesas,rcar-gen2-hscif", "renesas,hscif";
738 reg = <0 0xe62c0000 0 96>;
739 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
742 clock-names = "fck", "brg_int", "scif_clk";
743 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
744 dma-names = "tx", "rx";
745 power-domains = <&cpg_clocks>;
749 hscif1: serial@e62c8000 {
750 compatible = "renesas,hscif-r8a7790",
751 "renesas,rcar-gen2-hscif", "renesas,hscif";
752 reg = <0 0xe62c8000 0 96>;
753 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
756 clock-names = "fck", "brg_int", "scif_clk";
757 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
758 dma-names = "tx", "rx";
759 power-domains = <&cpg_clocks>;
763 ether: ethernet@ee700000 {
764 compatible = "renesas,ether-r8a7790";
765 reg = <0 0xee700000 0 0x400>;
766 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
768 power-domains = <&cpg_clocks>;
770 #address-cells = <1>;
775 avb: ethernet@e6800000 {
776 compatible = "renesas,etheravb-r8a7790",
777 "renesas,etheravb-rcar-gen2";
778 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
779 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
781 power-domains = <&cpg_clocks>;
782 #address-cells = <1>;
787 sata0: sata@ee300000 {
788 compatible = "renesas,sata-r8a7790";
789 reg = <0 0xee300000 0 0x2000>;
790 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
792 power-domains = <&cpg_clocks>;
796 sata1: sata@ee500000 {
797 compatible = "renesas,sata-r8a7790";
798 reg = <0 0xee500000 0 0x2000>;
799 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
801 power-domains = <&cpg_clocks>;
805 hsusb: usb@e6590000 {
806 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
807 reg = <0 0xe6590000 0 0x100>;
808 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
810 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
811 <&usb_dmac1 0>, <&usb_dmac1 1>;
812 dma-names = "ch0", "ch1", "ch2", "ch3";
813 power-domains = <&cpg_clocks>;
814 renesas,buswait = <4>;
820 usbphy: usb-phy@e6590100 {
821 compatible = "renesas,usb-phy-r8a7790";
822 reg = <0 0xe6590100 0 0x100>;
823 #address-cells = <1>;
825 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
826 clock-names = "usbhs";
827 power-domains = <&cpg_clocks>;
830 usb0: usb-channel@0 {
834 usb2: usb-channel@2 {
840 vin0: video@e6ef0000 {
841 compatible = "renesas,vin-r8a7790";
842 reg = <0 0xe6ef0000 0 0x1000>;
843 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
845 power-domains = <&cpg_clocks>;
849 vin1: video@e6ef1000 {
850 compatible = "renesas,vin-r8a7790";
851 reg = <0 0xe6ef1000 0 0x1000>;
852 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
854 power-domains = <&cpg_clocks>;
858 vin2: video@e6ef2000 {
859 compatible = "renesas,vin-r8a7790";
860 reg = <0 0xe6ef2000 0 0x1000>;
861 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
863 power-domains = <&cpg_clocks>;
867 vin3: video@e6ef3000 {
868 compatible = "renesas,vin-r8a7790";
869 reg = <0 0xe6ef3000 0 0x1000>;
870 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
872 power-domains = <&cpg_clocks>;
877 compatible = "renesas,vsp1";
878 reg = <0 0xfe920000 0 0x8000>;
879 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
881 power-domains = <&cpg_clocks>;
890 compatible = "renesas,vsp1";
891 reg = <0 0xfe928000 0 0x8000>;
892 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
894 power-domains = <&cpg_clocks>;
904 compatible = "renesas,vsp1";
905 reg = <0 0xfe930000 0 0x8000>;
906 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
908 power-domains = <&cpg_clocks>;
918 compatible = "renesas,vsp1";
919 reg = <0 0xfe938000 0 0x8000>;
920 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
922 power-domains = <&cpg_clocks>;
931 du: display@feb00000 {
932 compatible = "renesas,du-r8a7790";
933 reg = <0 0xfeb00000 0 0x70000>,
934 <0 0xfeb90000 0 0x1c>,
935 <0 0xfeb94000 0 0x1c>;
936 reg-names = "du", "lvds.0", "lvds.1";
937 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
941 <&mstp7_clks R8A7790_CLK_DU1>,
942 <&mstp7_clks R8A7790_CLK_DU2>,
943 <&mstp7_clks R8A7790_CLK_LVDS0>,
944 <&mstp7_clks R8A7790_CLK_LVDS1>;
945 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
949 #address-cells = <1>;
954 du_out_rgb: endpoint {
959 du_out_lvds0: endpoint {
964 du_out_lvds1: endpoint {
971 compatible = "renesas,can-r8a7790";
972 reg = <0 0xe6e80000 0 0x1000>;
973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
975 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
976 clock-names = "clkp1", "clkp2", "can_clk";
977 power-domains = <&cpg_clocks>;
982 compatible = "renesas,can-r8a7790";
983 reg = <0 0xe6e88000 0 0x1000>;
984 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
986 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
987 clock-names = "clkp1", "clkp2", "can_clk";
988 power-domains = <&cpg_clocks>;
992 jpu: jpeg-codec@fe980000 {
993 compatible = "renesas,jpu-r8a7790";
994 reg = <0 0xfe980000 0 0x10300>;
995 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
997 power-domains = <&cpg_clocks>;
1001 #address-cells = <2>;
1005 /* External root clock */
1007 compatible = "fixed-clock";
1009 /* This value must be overriden by the board. */
1010 clock-frequency = <0>;
1013 /* External PCIe clock - can be overridden by the board */
1014 pcie_bus_clk: pcie_bus {
1015 compatible = "fixed-clock";
1017 clock-frequency = <100000000>;
1018 status = "disabled";
1022 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1023 * default. Boards that provide audio clocks should override them.
1025 audio_clk_a: audio_clk_a {
1026 compatible = "fixed-clock";
1028 clock-frequency = <0>;
1030 audio_clk_b: audio_clk_b {
1031 compatible = "fixed-clock";
1033 clock-frequency = <0>;
1035 audio_clk_c: audio_clk_c {
1036 compatible = "fixed-clock";
1038 clock-frequency = <0>;
1041 /* External SCIF clock */
1043 compatible = "fixed-clock";
1045 /* This value must be overridden by the board. */
1046 clock-frequency = <0>;
1047 status = "disabled";
1050 /* External USB clock - can be overridden by the board */
1051 usb_extal_clk: usb_extal {
1052 compatible = "fixed-clock";
1054 clock-frequency = <48000000>;
1057 /* External CAN clock */
1059 compatible = "fixed-clock";
1061 /* This value must be overridden by the board. */
1062 clock-frequency = <0>;
1063 status = "disabled";
1066 /* Special CPG clocks */
1067 cpg_clocks: cpg_clocks@e6150000 {
1068 compatible = "renesas,r8a7790-cpg-clocks",
1069 "renesas,rcar-gen2-cpg-clocks";
1070 reg = <0 0xe6150000 0 0x1000>;
1071 clocks = <&extal_clk &usb_extal_clk>;
1073 clock-output-names = "main", "pll0", "pll1", "pll3",
1074 "lb", "qspi", "sdh", "sd0", "sd1",
1075 "z", "rcan", "adsp";
1076 #power-domain-cells = <0>;
1079 /* Variable factor clocks */
1080 sd2_clk: sd2@e6150078 {
1081 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1082 reg = <0 0xe6150078 0 4>;
1083 clocks = <&pll1_div2_clk>;
1086 sd3_clk: sd3@e615026c {
1087 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1088 reg = <0 0xe615026c 0 4>;
1089 clocks = <&pll1_div2_clk>;
1092 mmc0_clk: mmc0@e6150240 {
1093 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1094 reg = <0 0xe6150240 0 4>;
1095 clocks = <&pll1_div2_clk>;
1098 mmc1_clk: mmc1@e6150244 {
1099 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1100 reg = <0 0xe6150244 0 4>;
1101 clocks = <&pll1_div2_clk>;
1104 ssp_clk: ssp@e6150248 {
1105 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1106 reg = <0 0xe6150248 0 4>;
1107 clocks = <&pll1_div2_clk>;
1110 ssprs_clk: ssprs@e615024c {
1111 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1112 reg = <0 0xe615024c 0 4>;
1113 clocks = <&pll1_div2_clk>;
1117 /* Fixed factor clocks */
1118 pll1_div2_clk: pll1_div2 {
1119 compatible = "fixed-factor-clock";
1120 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1126 compatible = "fixed-factor-clock";
1127 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1133 compatible = "fixed-factor-clock";
1134 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1140 compatible = "fixed-factor-clock";
1141 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1147 compatible = "fixed-factor-clock";
1148 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1154 compatible = "fixed-factor-clock";
1155 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1161 compatible = "fixed-factor-clock";
1162 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1168 compatible = "fixed-factor-clock";
1169 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1175 compatible = "fixed-factor-clock";
1176 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1182 compatible = "fixed-factor-clock";
1183 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1189 compatible = "fixed-factor-clock";
1190 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1196 compatible = "fixed-factor-clock";
1197 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1203 compatible = "fixed-factor-clock";
1204 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1206 clock-div = <(48 * 1024)>;
1209 oscclk_clk: oscclk {
1210 compatible = "fixed-factor-clock";
1211 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1213 clock-div = <(12 * 1024)>;
1217 compatible = "fixed-factor-clock";
1218 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1224 compatible = "fixed-factor-clock";
1225 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1231 compatible = "fixed-factor-clock";
1232 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1238 compatible = "fixed-factor-clock";
1239 clocks = <&pll1_div2_clk>;
1245 compatible = "fixed-factor-clock";
1246 clocks = <&extal_clk>;
1253 mstp0_clks: mstp0_clks@e6150130 {
1254 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1255 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1258 clock-indices = <R8A7790_CLK_MSIOF0>;
1259 clock-output-names = "msiof0";
1261 mstp1_clks: mstp1_clks@e6150134 {
1262 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1263 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1264 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1265 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1266 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1267 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1270 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1271 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1272 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1273 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1274 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1275 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1276 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1278 clock-output-names =
1279 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1280 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1281 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1282 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1284 mstp2_clks: mstp2_clks@e6150138 {
1285 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1286 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1287 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1288 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1292 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1293 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1294 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1295 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1297 clock-output-names =
1298 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1299 "scifb1", "msiof1", "msiof3", "scifb2",
1300 "sys-dmac1", "sys-dmac0";
1302 mstp3_clks: mstp3_clks@e615013c {
1303 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1304 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1305 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1306 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1307 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1308 <&hp_clk>, <&hp_clk>;
1311 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1312 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1313 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1314 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1316 clock-output-names =
1317 "iic2", "tpu0", "mmcif1", "sdhi3",
1318 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1319 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1320 "usbdmac0", "usbdmac1";
1322 mstp4_clks: mstp4_clks@e6150140 {
1323 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1324 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1327 clock-indices = <R8A7790_CLK_IRQC>;
1328 clock-output-names = "irqc";
1330 mstp5_clks: mstp5_clks@e6150144 {
1331 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1332 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1333 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1334 <&extal_clk>, <&p_clk>;
1337 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1338 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1341 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1344 mstp7_clks: mstp7_clks@e615014c {
1345 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1346 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1347 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1348 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1352 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1353 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1354 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1355 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1357 clock-output-names =
1358 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1359 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1361 mstp8_clks: mstp8_clks@e6150990 {
1362 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1363 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1364 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1365 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1369 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1370 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1371 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1372 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1374 clock-output-names =
1375 "mlb", "vin3", "vin2", "vin1", "vin0",
1376 "etheravb", "ether", "sata1", "sata0";
1378 mstp9_clks: mstp9_clks@e6150994 {
1379 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1380 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1381 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1382 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1383 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1384 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1387 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1388 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1389 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1390 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1392 clock-output-names =
1393 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1394 "rcan1", "rcan0", "qspi_mod", "iic3",
1395 "i2c3", "i2c2", "i2c1", "i2c0";
1397 mstp10_clks: mstp10_clks@e6150998 {
1398 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1399 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1401 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1402 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1404 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1405 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1406 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1407 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1408 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1409 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1410 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1415 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1416 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1418 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1419 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1420 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1421 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1423 clock-output-names =
1425 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1426 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1428 "scu-dvc1", "scu-dvc0",
1429 "scu-ctu1-mix1", "scu-ctu0-mix0",
1430 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1431 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1435 qspi: spi@e6b10000 {
1436 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1437 reg = <0 0xe6b10000 0 0x2c>;
1438 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1439 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1440 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1441 dma-names = "tx", "rx";
1442 power-domains = <&cpg_clocks>;
1444 #address-cells = <1>;
1446 status = "disabled";
1449 msiof0: spi@e6e20000 {
1450 compatible = "renesas,msiof-r8a7790";
1451 reg = <0 0xe6e20000 0 0x0064>;
1452 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1454 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1455 dma-names = "tx", "rx";
1456 power-domains = <&cpg_clocks>;
1457 #address-cells = <1>;
1459 status = "disabled";
1462 msiof1: spi@e6e10000 {
1463 compatible = "renesas,msiof-r8a7790";
1464 reg = <0 0xe6e10000 0 0x0064>;
1465 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1466 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1467 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1468 dma-names = "tx", "rx";
1469 power-domains = <&cpg_clocks>;
1470 #address-cells = <1>;
1472 status = "disabled";
1475 msiof2: spi@e6e00000 {
1476 compatible = "renesas,msiof-r8a7790";
1477 reg = <0 0xe6e00000 0 0x0064>;
1478 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1480 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1481 dma-names = "tx", "rx";
1482 power-domains = <&cpg_clocks>;
1483 #address-cells = <1>;
1485 status = "disabled";
1488 msiof3: spi@e6c90000 {
1489 compatible = "renesas,msiof-r8a7790";
1490 reg = <0 0xe6c90000 0 0x0064>;
1491 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1492 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1493 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1494 dma-names = "tx", "rx";
1495 power-domains = <&cpg_clocks>;
1496 #address-cells = <1>;
1498 status = "disabled";
1501 xhci: usb@ee000000 {
1502 compatible = "renesas,xhci-r8a7790";
1503 reg = <0 0xee000000 0 0xc00>;
1504 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1506 power-domains = <&cpg_clocks>;
1509 status = "disabled";
1512 pci0: pci@ee090000 {
1513 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1514 device_type = "pci";
1515 reg = <0 0xee090000 0 0xc00>,
1516 <0 0xee080000 0 0x1100>;
1517 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1518 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1519 power-domains = <&cpg_clocks>;
1520 status = "disabled";
1523 #address-cells = <3>;
1525 #interrupt-cells = <1>;
1526 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1527 interrupt-map-mask = <0xff00 0 0 0x7>;
1528 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1529 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1530 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1533 reg = <0x800 0 0 0 0>;
1534 device_type = "pci";
1540 reg = <0x1000 0 0 0 0>;
1541 device_type = "pci";
1547 pci1: pci@ee0b0000 {
1548 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1549 device_type = "pci";
1550 reg = <0 0xee0b0000 0 0xc00>,
1551 <0 0xee0a0000 0 0x1100>;
1552 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1553 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1554 power-domains = <&cpg_clocks>;
1555 status = "disabled";
1558 #address-cells = <3>;
1560 #interrupt-cells = <1>;
1561 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1562 interrupt-map-mask = <0xff00 0 0 0x7>;
1563 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1564 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1565 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1568 pci2: pci@ee0d0000 {
1569 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1570 device_type = "pci";
1571 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1572 power-domains = <&cpg_clocks>;
1573 reg = <0 0xee0d0000 0 0xc00>,
1574 <0 0xee0c0000 0 0x1100>;
1575 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1576 status = "disabled";
1579 #address-cells = <3>;
1581 #interrupt-cells = <1>;
1582 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1583 interrupt-map-mask = <0xff00 0 0 0x7>;
1584 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1585 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1586 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1589 reg = <0x800 0 0 0 0>;
1590 device_type = "pci";
1596 reg = <0x1000 0 0 0 0>;
1597 device_type = "pci";
1603 pciec: pcie@fe000000 {
1604 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1605 reg = <0 0xfe000000 0 0x80000>;
1606 #address-cells = <3>;
1608 bus-range = <0x00 0xff>;
1609 device_type = "pci";
1610 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1611 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1612 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1613 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1614 /* Map all possible DDR as inbound ranges */
1615 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1616 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1617 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1618 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1620 #interrupt-cells = <1>;
1621 interrupt-map-mask = <0 0 0 0>;
1622 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1624 clock-names = "pcie", "pcie_bus";
1625 power-domains = <&cpg_clocks>;
1626 status = "disabled";
1629 rcar_sound: sound@ec500000 {
1631 * #sound-dai-cells is required
1633 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1634 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1636 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1637 reg = <0 0xec500000 0 0x1000>, /* SCU */
1638 <0 0xec5a0000 0 0x100>, /* ADG */
1639 <0 0xec540000 0 0x1000>, /* SSIU */
1640 <0 0xec541000 0 0x280>, /* SSI */
1641 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1642 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1644 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1645 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1646 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1647 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1648 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1649 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1650 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1651 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1652 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1653 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1654 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1655 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1656 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1657 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1658 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1659 clock-names = "ssi-all",
1660 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1661 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1662 "src.9", "src.8", "src.7", "src.6", "src.5",
1663 "src.4", "src.3", "src.2", "src.1", "src.0",
1667 "clk_a", "clk_b", "clk_c", "clk_i";
1668 power-domains = <&cpg_clocks>;
1670 status = "disabled";
1674 dmas = <&audma0 0xbc>;
1678 dmas = <&audma0 0xbe>;
1701 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1702 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1703 dma-names = "rx", "tx";
1706 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1707 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1708 dma-names = "rx", "tx";
1711 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1712 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1713 dma-names = "rx", "tx";
1716 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1717 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1718 dma-names = "rx", "tx";
1721 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1722 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1723 dma-names = "rx", "tx";
1726 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1727 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1728 dma-names = "rx", "tx";
1731 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1732 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1733 dma-names = "rx", "tx";
1736 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1737 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1738 dma-names = "rx", "tx";
1741 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1742 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1743 dma-names = "rx", "tx";
1746 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1747 dmas = <&audma0 0x97>, <&audma1 0xba>;
1748 dma-names = "rx", "tx";
1754 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1755 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1756 dma-names = "rx", "tx", "rxu", "txu";
1759 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1760 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1761 dma-names = "rx", "tx", "rxu", "txu";
1764 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1765 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1766 dma-names = "rx", "tx", "rxu", "txu";
1769 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1770 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1771 dma-names = "rx", "tx", "rxu", "txu";
1774 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1775 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1776 dma-names = "rx", "tx", "rxu", "txu";
1779 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1780 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1781 dma-names = "rx", "tx", "rxu", "txu";
1784 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1785 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1786 dma-names = "rx", "tx", "rxu", "txu";
1789 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1790 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1791 dma-names = "rx", "tx", "rxu", "txu";
1794 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1795 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1796 dma-names = "rx", "tx", "rxu", "txu";
1799 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1800 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1801 dma-names = "rx", "tx", "rxu", "txu";
1806 ipmmu_sy0: mmu@e6280000 {
1807 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1808 reg = <0 0xe6280000 0 0x1000>;
1809 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1810 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1812 status = "disabled";
1815 ipmmu_sy1: mmu@e6290000 {
1816 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1817 reg = <0 0xe6290000 0 0x1000>;
1818 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1820 status = "disabled";
1823 ipmmu_ds: mmu@e6740000 {
1824 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1825 reg = <0 0xe6740000 0 0x1000>;
1826 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1829 status = "disabled";
1832 ipmmu_mp: mmu@ec680000 {
1833 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1834 reg = <0 0xec680000 0 0x1000>;
1835 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1837 status = "disabled";
1840 ipmmu_mx: mmu@fe951000 {
1841 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1842 reg = <0 0xfe951000 0 0x1000>;
1843 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1846 status = "disabled";
1849 ipmmu_rt: mmu@ffc80000 {
1850 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1851 reg = <0 0xffc80000 0 0x1000>;
1852 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1854 status = "disabled";