2 * Device Tree Source for the r8a7790 SoC
4 * Copyright (C) 2013 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7790-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,r8a7790";
17 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a15";
29 clock-frequency = <1300000000>;
34 compatible = "arm,cortex-a15";
36 clock-frequency = <1300000000>;
41 compatible = "arm,cortex-a15";
43 clock-frequency = <1300000000>;
48 compatible = "arm,cortex-a15";
50 clock-frequency = <1300000000>;
55 compatible = "arm,cortex-a7";
57 clock-frequency = <780000000>;
62 compatible = "arm,cortex-a7";
64 clock-frequency = <780000000>;
69 compatible = "arm,cortex-a7";
71 clock-frequency = <780000000>;
76 compatible = "arm,cortex-a7";
78 clock-frequency = <780000000>;
82 gic: interrupt-controller@f1001000 {
83 compatible = "arm,cortex-a15-gic";
84 #interrupt-cells = <3>;
87 reg = <0 0xf1001000 0 0x1000>,
88 <0 0xf1002000 0 0x1000>,
89 <0 0xf1004000 0 0x2000>,
90 <0 0xf1006000 0 0x2000>;
91 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
94 gpio0: gpio@e6050000 {
95 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
96 reg = <0 0xe6050000 0 0x50>;
97 interrupt-parent = <&gic>;
98 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
101 gpio-ranges = <&pfc 0 0 32>;
102 #interrupt-cells = <2>;
103 interrupt-controller;
106 gpio1: gpio@e6051000 {
107 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
108 reg = <0 0xe6051000 0 0x50>;
109 interrupt-parent = <&gic>;
110 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
113 gpio-ranges = <&pfc 0 32 32>;
114 #interrupt-cells = <2>;
115 interrupt-controller;
118 gpio2: gpio@e6052000 {
119 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
120 reg = <0 0xe6052000 0 0x50>;
121 interrupt-parent = <&gic>;
122 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
125 gpio-ranges = <&pfc 0 64 32>;
126 #interrupt-cells = <2>;
127 interrupt-controller;
130 gpio3: gpio@e6053000 {
131 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
132 reg = <0 0xe6053000 0 0x50>;
133 interrupt-parent = <&gic>;
134 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
137 gpio-ranges = <&pfc 0 96 32>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
142 gpio4: gpio@e6054000 {
143 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
144 reg = <0 0xe6054000 0 0x50>;
145 interrupt-parent = <&gic>;
146 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
149 gpio-ranges = <&pfc 0 128 32>;
150 #interrupt-cells = <2>;
151 interrupt-controller;
154 gpio5: gpio@e6055000 {
155 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
156 reg = <0 0xe6055000 0 0x50>;
157 interrupt-parent = <&gic>;
158 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
161 gpio-ranges = <&pfc 0 160 32>;
162 #interrupt-cells = <2>;
163 interrupt-controller;
167 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
168 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
169 interrupt-parent = <&gic>;
170 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
174 compatible = "arm,armv7-timer";
175 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
176 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
177 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
178 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
181 irqc0: interrupt-controller@e61c0000 {
182 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
183 #interrupt-cells = <2>;
184 interrupt-controller;
185 reg = <0 0xe61c0000 0 0x200>;
186 interrupt-parent = <&gic>;
187 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
188 <0 1 IRQ_TYPE_LEVEL_HIGH>,
189 <0 2 IRQ_TYPE_LEVEL_HIGH>,
190 <0 3 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
196 compatible = "renesas,i2c-r8a7790";
197 reg = <0 0xe6508000 0 0x40>;
198 interrupt-parent = <&gic>;
199 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp3_clks R8A7790_CLK_I2C0>;
205 #address-cells = <1>;
207 compatible = "renesas,i2c-r8a7790";
208 reg = <0 0xe6518000 0 0x40>;
209 interrupt-parent = <&gic>;
210 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&mstp3_clks R8A7790_CLK_I2C1>;
216 #address-cells = <1>;
218 compatible = "renesas,i2c-r8a7790";
219 reg = <0 0xe6530000 0 0x40>;
220 interrupt-parent = <&gic>;
221 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp3_clks R8A7790_CLK_I2C2>;
227 #address-cells = <1>;
229 compatible = "renesas,i2c-r8a7790";
230 reg = <0 0xe6540000 0 0x40>;
231 interrupt-parent = <&gic>;
232 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp3_clks R8A7790_CLK_I2C3>;
237 mmcif0: mmcif@ee200000 {
238 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
239 reg = <0 0xee200000 0 0x80>;
240 interrupt-parent = <&gic>;
241 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
247 mmcif1: mmc@ee220000 {
248 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
249 reg = <0 0xee220000 0 0x80>;
250 interrupt-parent = <&gic>;
251 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
258 compatible = "renesas,pfc-r8a7790";
259 reg = <0 0xe6060000 0 0x250>;
263 compatible = "renesas,sdhi-r8a7790";
264 reg = <0 0xee100000 0 0x200>;
265 interrupt-parent = <&gic>;
266 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
273 compatible = "renesas,sdhi-r8a7790";
274 reg = <0 0xee120000 0 0x200>;
275 interrupt-parent = <&gic>;
276 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
283 compatible = "renesas,sdhi-r8a7790";
284 reg = <0 0xee140000 0 0x100>;
285 interrupt-parent = <&gic>;
286 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
293 compatible = "renesas,sdhi-r8a7790";
294 reg = <0 0xee160000 0 0x100>;
295 interrupt-parent = <&gic>;
296 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
303 #address-cells = <2>;
307 /* External root clock */
308 extal_clk: extal_clk {
309 compatible = "fixed-clock";
311 /* This value must be overriden by the board. */
312 clock-frequency = <0>;
313 clock-output-names = "extal";
316 /* Special CPG clocks */
317 cpg_clocks: cpg_clocks@e6150000 {
318 compatible = "renesas,r8a7790-cpg-clocks",
319 "renesas,rcar-gen2-cpg-clocks";
320 reg = <0 0xe6150000 0 0x1000>;
321 clocks = <&extal_clk>;
323 clock-output-names = "main", "pll0", "pll1", "pll3",
324 "lb", "qspi", "sdh", "sd0", "sd1",
328 /* Variable factor clocks */
329 sd2_clk: sd2_clk@e6150078 {
330 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
331 reg = <0 0xe6150078 0 4>;
332 clocks = <&pll1_div2_clk>;
334 clock-output-names = "sd2";
336 sd3_clk: sd3_clk@e615007c {
337 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
338 reg = <0 0xe615007c 0 4>;
339 clocks = <&pll1_div2_clk>;
341 clock-output-names = "sd3";
343 mmc0_clk: mmc0_clk@e6150240 {
344 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
345 reg = <0 0xe6150240 0 4>;
346 clocks = <&pll1_div2_clk>;
348 clock-output-names = "mmc0";
350 mmc1_clk: mmc1_clk@e6150244 {
351 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
352 reg = <0 0xe6150244 0 4>;
353 clocks = <&pll1_div2_clk>;
355 clock-output-names = "mmc1";
357 ssp_clk: ssp_clk@e6150248 {
358 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
359 reg = <0 0xe6150248 0 4>;
360 clocks = <&pll1_div2_clk>;
362 clock-output-names = "ssp";
364 ssprs_clk: ssprs_clk@e615024c {
365 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
366 reg = <0 0xe615024c 0 4>;
367 clocks = <&pll1_div2_clk>;
369 clock-output-names = "ssprs";
372 /* Fixed factor clocks */
373 pll1_div2_clk: pll1_div2_clk {
374 compatible = "fixed-factor-clock";
375 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
379 clock-output-names = "pll1_div2";
382 compatible = "fixed-factor-clock";
383 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
387 clock-output-names = "z2";
390 compatible = "fixed-factor-clock";
391 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
395 clock-output-names = "zg";
398 compatible = "fixed-factor-clock";
399 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
403 clock-output-names = "zx";
406 compatible = "fixed-factor-clock";
407 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
411 clock-output-names = "zs";
414 compatible = "fixed-factor-clock";
415 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
419 clock-output-names = "hp";
422 compatible = "fixed-factor-clock";
423 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
427 clock-output-names = "i";
430 compatible = "fixed-factor-clock";
431 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
435 clock-output-names = "b";
438 compatible = "fixed-factor-clock";
439 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
443 clock-output-names = "p";
446 compatible = "fixed-factor-clock";
447 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
451 clock-output-names = "cl";
454 compatible = "fixed-factor-clock";
455 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
459 clock-output-names = "m2";
462 compatible = "fixed-factor-clock";
463 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
467 clock-output-names = "imp";
470 compatible = "fixed-factor-clock";
471 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
473 clock-div = <(48 * 1024)>;
475 clock-output-names = "rclk";
477 oscclk_clk: oscclk_clk {
478 compatible = "fixed-factor-clock";
479 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
481 clock-div = <(12 * 1024)>;
483 clock-output-names = "oscclk";
486 compatible = "fixed-factor-clock";
487 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
491 clock-output-names = "zb3";
493 zb3d2_clk: zb3d2_clk {
494 compatible = "fixed-factor-clock";
495 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
499 clock-output-names = "zb3d2";
502 compatible = "fixed-factor-clock";
503 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
507 clock-output-names = "ddr";
510 compatible = "fixed-factor-clock";
511 clocks = <&pll1_div2_clk>;
515 clock-output-names = "mp";
518 compatible = "fixed-factor-clock";
519 clocks = <&extal_clk>;
523 clock-output-names = "cp";
527 mstp0_clks: mstp0_clks@e6150130 {
528 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
529 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
532 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
533 clock-output-names = "msiof0";
535 mstp1_clks: mstp1_clks@e6150134 {
536 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
537 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
538 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
539 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
542 renesas,clock-indices = <
543 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
544 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
545 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
548 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
549 "vsp1-du0", "vsp1-rt", "vsp1-sy";
551 mstp2_clks: mstp2_clks@e6150138 {
552 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
553 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
554 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
555 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
557 renesas,clock-indices = <
558 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
559 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
560 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
563 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
564 "scifb1", "msiof1", "msiof3", "scifb2";
566 mstp3_clks: mstp3_clks@e615013c {
567 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
568 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
569 clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
570 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
571 <&mmc0_clk>, <&rclk_clk>;
573 renesas,clock-indices = <
574 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
575 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
576 R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
579 "tpu0", "mmcif1", "sdhi3", "sdhi2",
580 "sdhi1", "sdhi0", "mmcif0", "cmt1";
582 mstp5_clks: mstp5_clks@e6150144 {
583 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
584 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
585 clocks = <&extal_clk>, <&p_clk>;
587 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
588 clock-output-names = "thermal", "pwm";
590 mstp7_clks: mstp7_clks@e615014c {
591 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
592 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
593 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
594 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
597 renesas,clock-indices = <
598 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
599 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
600 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
601 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
604 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
605 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
607 mstp8_clks: mstp8_clks@e6150990 {
608 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
609 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
612 renesas,clock-indices = <R8A7790_CLK_ETHER>;
613 clock-output-names = "ether";
615 mstp9_clks: mstp9_clks@e6150994 {
616 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
617 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
618 clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
619 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
621 renesas,clock-indices = <
622 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
623 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
627 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";