arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7790-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7790";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &iic0;
  29                 i2c5 = &iic1;
  30                 i2c6 = &iic2;
  31                 i2c7 = &iic3;
  32                 spi0 = &qspi;
  33                 spi1 = &msiof0;
  34                 spi2 = &msiof1;
  35                 spi3 = &msiof2;
  36                 spi4 = &msiof3;
  37                 vin0 = &vin0;
  38                 vin1 = &vin1;
  39                 vin2 = &vin2;
  40                 vin3 = &vin3;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0>;
  51                         clock-frequency = <1300000000>;
  52                         voltage-tolerance = <1>; /* 1% */
  53                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  54                         clock-latency = <300000>; /* 300 us */
  55
  56                         /* kHz - uV - OPPs unknown yet */
  57                         operating-points = <1400000 1000000>,
  58                                            <1225000 1000000>,
  59                                            <1050000 1000000>,
  60                                            < 875000 1000000>,
  61                                            < 700000 1000000>,
  62                                            < 350000 1000000>;
  63                 };
  64
  65                 cpu1: cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <1>;
  69                         clock-frequency = <1300000000>;
  70                 };
  71
  72                 cpu2: cpu@2 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a15";
  75                         reg = <2>;
  76                         clock-frequency = <1300000000>;
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a15";
  82                         reg = <3>;
  83                         clock-frequency = <1300000000>;
  84                 };
  85
  86                 cpu4: cpu@4 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a7";
  89                         reg = <0x100>;
  90                         clock-frequency = <780000000>;
  91                 };
  92
  93                 cpu5: cpu@5 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         reg = <0x101>;
  97                         clock-frequency = <780000000>;
  98                 };
  99
 100                 cpu6: cpu@6 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a7";
 103                         reg = <0x102>;
 104                         clock-frequency = <780000000>;
 105                 };
 106
 107                 cpu7: cpu@7 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a7";
 110                         reg = <0x103>;
 111                         clock-frequency = <780000000>;
 112                 };
 113         };
 114
 115         gic: interrupt-controller@f1001000 {
 116                 compatible = "arm,gic-400";
 117                 #interrupt-cells = <3>;
 118                 #address-cells = <0>;
 119                 interrupt-controller;
 120                 reg = <0 0xf1001000 0 0x1000>,
 121                         <0 0xf1002000 0 0x1000>,
 122                         <0 0xf1004000 0 0x2000>,
 123                         <0 0xf1006000 0 0x2000>;
 124                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 125         };
 126
 127         gpio0: gpio@e6050000 {
 128                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 129                 reg = <0 0xe6050000 0 0x50>;
 130                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 131                 #gpio-cells = <2>;
 132                 gpio-controller;
 133                 gpio-ranges = <&pfc 0 0 32>;
 134                 #interrupt-cells = <2>;
 135                 interrupt-controller;
 136                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 137         };
 138
 139         gpio1: gpio@e6051000 {
 140                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 141                 reg = <0 0xe6051000 0 0x50>;
 142                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 143                 #gpio-cells = <2>;
 144                 gpio-controller;
 145                 gpio-ranges = <&pfc 0 32 32>;
 146                 #interrupt-cells = <2>;
 147                 interrupt-controller;
 148                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 149         };
 150
 151         gpio2: gpio@e6052000 {
 152                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 153                 reg = <0 0xe6052000 0 0x50>;
 154                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 155                 #gpio-cells = <2>;
 156                 gpio-controller;
 157                 gpio-ranges = <&pfc 0 64 32>;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 161         };
 162
 163         gpio3: gpio@e6053000 {
 164                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 165                 reg = <0 0xe6053000 0 0x50>;
 166                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 167                 #gpio-cells = <2>;
 168                 gpio-controller;
 169                 gpio-ranges = <&pfc 0 96 32>;
 170                 #interrupt-cells = <2>;
 171                 interrupt-controller;
 172                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 173         };
 174
 175         gpio4: gpio@e6054000 {
 176                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 177                 reg = <0 0xe6054000 0 0x50>;
 178                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 179                 #gpio-cells = <2>;
 180                 gpio-controller;
 181                 gpio-ranges = <&pfc 0 128 32>;
 182                 #interrupt-cells = <2>;
 183                 interrupt-controller;
 184                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 185         };
 186
 187         gpio5: gpio@e6055000 {
 188                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 189                 reg = <0 0xe6055000 0 0x50>;
 190                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 191                 #gpio-cells = <2>;
 192                 gpio-controller;
 193                 gpio-ranges = <&pfc 0 160 32>;
 194                 #interrupt-cells = <2>;
 195                 interrupt-controller;
 196                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 197         };
 198
 199         thermal@e61f0000 {
 200                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 201                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 202                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 204         };
 205
 206         timer {
 207                 compatible = "arm,armv7-timer";
 208                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 211                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 212         };
 213
 214         cmt0: timer@ffca0000 {
 215                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 216                 reg = <0 0xffca0000 0 0x1004>;
 217                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 218                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 220                 clock-names = "fck";
 221
 222                 renesas,channels-mask = <0x60>;
 223
 224                 status = "disabled";
 225         };
 226
 227         cmt1: timer@e6130000 {
 228                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 229                 reg = <0 0xe6130000 0 0x1004>;
 230                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 231                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 232                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 237                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 239                 clock-names = "fck";
 240
 241                 renesas,channels-mask = <0xff>;
 242
 243                 status = "disabled";
 244         };
 245
 246         irqc0: interrupt-controller@e61c0000 {
 247                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 248                 #interrupt-cells = <2>;
 249                 interrupt-controller;
 250                 reg = <0 0xe61c0000 0 0x200>;
 251                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 252                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 253                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 254                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
 256         };
 257
 258         dmac0: dma-controller@e6700000 {
 259                 compatible = "renesas,rcar-dmac";
 260                 reg = <0 0xe6700000 0 0x20000>;
 261                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 262                               0 200 IRQ_TYPE_LEVEL_HIGH
 263                               0 201 IRQ_TYPE_LEVEL_HIGH
 264                               0 202 IRQ_TYPE_LEVEL_HIGH
 265                               0 203 IRQ_TYPE_LEVEL_HIGH
 266                               0 204 IRQ_TYPE_LEVEL_HIGH
 267                               0 205 IRQ_TYPE_LEVEL_HIGH
 268                               0 206 IRQ_TYPE_LEVEL_HIGH
 269                               0 207 IRQ_TYPE_LEVEL_HIGH
 270                               0 208 IRQ_TYPE_LEVEL_HIGH
 271                               0 209 IRQ_TYPE_LEVEL_HIGH
 272                               0 210 IRQ_TYPE_LEVEL_HIGH
 273                               0 211 IRQ_TYPE_LEVEL_HIGH
 274                               0 212 IRQ_TYPE_LEVEL_HIGH
 275                               0 213 IRQ_TYPE_LEVEL_HIGH
 276                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 277                 interrupt-names = "error",
 278                                 "ch0", "ch1", "ch2", "ch3",
 279                                 "ch4", "ch5", "ch6", "ch7",
 280                                 "ch8", "ch9", "ch10", "ch11",
 281                                 "ch12", "ch13", "ch14";
 282                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 283                 clock-names = "fck";
 284                 #dma-cells = <1>;
 285                 dma-channels = <15>;
 286         };
 287
 288         dmac1: dma-controller@e6720000 {
 289                 compatible = "renesas,rcar-dmac";
 290                 reg = <0 0xe6720000 0 0x20000>;
 291                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 292                               0 216 IRQ_TYPE_LEVEL_HIGH
 293                               0 217 IRQ_TYPE_LEVEL_HIGH
 294                               0 218 IRQ_TYPE_LEVEL_HIGH
 295                               0 219 IRQ_TYPE_LEVEL_HIGH
 296                               0 308 IRQ_TYPE_LEVEL_HIGH
 297                               0 309 IRQ_TYPE_LEVEL_HIGH
 298                               0 310 IRQ_TYPE_LEVEL_HIGH
 299                               0 311 IRQ_TYPE_LEVEL_HIGH
 300                               0 312 IRQ_TYPE_LEVEL_HIGH
 301                               0 313 IRQ_TYPE_LEVEL_HIGH
 302                               0 314 IRQ_TYPE_LEVEL_HIGH
 303                               0 315 IRQ_TYPE_LEVEL_HIGH
 304                               0 316 IRQ_TYPE_LEVEL_HIGH
 305                               0 317 IRQ_TYPE_LEVEL_HIGH
 306                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 307                 interrupt-names = "error",
 308                                 "ch0", "ch1", "ch2", "ch3",
 309                                 "ch4", "ch5", "ch6", "ch7",
 310                                 "ch8", "ch9", "ch10", "ch11",
 311                                 "ch12", "ch13", "ch14";
 312                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 313                 clock-names = "fck";
 314                 #dma-cells = <1>;
 315                 dma-channels = <15>;
 316         };
 317
 318         audma0: dma-controller@ec700000 {
 319                 compatible = "renesas,rcar-dmac";
 320                 reg = <0 0xec700000 0 0x10000>;
 321                 interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
 322                                  0 320 IRQ_TYPE_LEVEL_HIGH
 323                                  0 321 IRQ_TYPE_LEVEL_HIGH
 324                                  0 322 IRQ_TYPE_LEVEL_HIGH
 325                                  0 323 IRQ_TYPE_LEVEL_HIGH
 326                                  0 324 IRQ_TYPE_LEVEL_HIGH
 327                                  0 325 IRQ_TYPE_LEVEL_HIGH
 328                                  0 326 IRQ_TYPE_LEVEL_HIGH
 329                                  0 327 IRQ_TYPE_LEVEL_HIGH
 330                                  0 328 IRQ_TYPE_LEVEL_HIGH
 331                                  0 329 IRQ_TYPE_LEVEL_HIGH
 332                                  0 330 IRQ_TYPE_LEVEL_HIGH
 333                                  0 331 IRQ_TYPE_LEVEL_HIGH
 334                                  0 332 IRQ_TYPE_LEVEL_HIGH>;
 335                 interrupt-names = "error",
 336                                 "ch0", "ch1", "ch2", "ch3",
 337                                 "ch4", "ch5", "ch6", "ch7",
 338                                 "ch8", "ch9", "ch10", "ch11",
 339                                 "ch12";
 340                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
 341                 clock-names = "fck";
 342                 #dma-cells = <1>;
 343                 dma-channels = <13>;
 344         };
 345
 346         audma1: dma-controller@ec720000 {
 347                 compatible = "renesas,rcar-dmac";
 348                 reg = <0 0xec720000 0 0x10000>;
 349                 interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
 350                                  0 333 IRQ_TYPE_LEVEL_HIGH
 351                                  0 334 IRQ_TYPE_LEVEL_HIGH
 352                                  0 335 IRQ_TYPE_LEVEL_HIGH
 353                                  0 336 IRQ_TYPE_LEVEL_HIGH
 354                                  0 337 IRQ_TYPE_LEVEL_HIGH
 355                                  0 338 IRQ_TYPE_LEVEL_HIGH
 356                                  0 339 IRQ_TYPE_LEVEL_HIGH
 357                                  0 340 IRQ_TYPE_LEVEL_HIGH
 358                                  0 341 IRQ_TYPE_LEVEL_HIGH
 359                                  0 342 IRQ_TYPE_LEVEL_HIGH
 360                                  0 343 IRQ_TYPE_LEVEL_HIGH
 361                                  0 344 IRQ_TYPE_LEVEL_HIGH
 362                                  0 345 IRQ_TYPE_LEVEL_HIGH>;
 363                 interrupt-names = "error",
 364                                 "ch0", "ch1", "ch2", "ch3",
 365                                 "ch4", "ch5", "ch6", "ch7",
 366                                 "ch8", "ch9", "ch10", "ch11",
 367                                 "ch12";
 368                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
 369                 clock-names = "fck";
 370                 #dma-cells = <1>;
 371                 dma-channels = <13>;
 372         };
 373
 374         usb_dmac0: dma-controller@e65a0000 {
 375                 compatible = "renesas,usb-dmac";
 376                 reg = <0 0xe65a0000 0 0x100>;
 377                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
 378                               0 109 IRQ_TYPE_LEVEL_HIGH>;
 379                 interrupt-names = "ch0", "ch1";
 380                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
 381                 #dma-cells = <1>;
 382                 dma-channels = <2>;
 383         };
 384
 385         usb_dmac1: dma-controller@e65b0000 {
 386                 compatible = "renesas,usb-dmac";
 387                 reg = <0 0xe65b0000 0 0x100>;
 388                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
 389                               0 110 IRQ_TYPE_LEVEL_HIGH>;
 390                 interrupt-names = "ch0", "ch1";
 391                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
 392                 #dma-cells = <1>;
 393                 dma-channels = <2>;
 394         };
 395
 396         i2c0: i2c@e6508000 {
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 compatible = "renesas,i2c-r8a7790";
 400                 reg = <0 0xe6508000 0 0x40>;
 401                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 403                 status = "disabled";
 404         };
 405
 406         i2c1: i2c@e6518000 {
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 compatible = "renesas,i2c-r8a7790";
 410                 reg = <0 0xe6518000 0 0x40>;
 411                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 413                 status = "disabled";
 414         };
 415
 416         i2c2: i2c@e6530000 {
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 compatible = "renesas,i2c-r8a7790";
 420                 reg = <0 0xe6530000 0 0x40>;
 421                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 423                 status = "disabled";
 424         };
 425
 426         i2c3: i2c@e6540000 {
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 compatible = "renesas,i2c-r8a7790";
 430                 reg = <0 0xe6540000 0 0x40>;
 431                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 432                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 433                 status = "disabled";
 434         };
 435
 436         iic0: i2c@e6500000 {
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 440                 reg = <0 0xe6500000 0 0x425>;
 441                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 443                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 444                 dma-names = "tx", "rx";
 445                 status = "disabled";
 446         };
 447
 448         iic1: i2c@e6510000 {
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 452                 reg = <0 0xe6510000 0 0x425>;
 453                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 455                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 456                 dma-names = "tx", "rx";
 457                 status = "disabled";
 458         };
 459
 460         iic2: i2c@e6520000 {
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 464                 reg = <0 0xe6520000 0 0x425>;
 465                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 466                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 467                 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
 468                 dma-names = "tx", "rx";
 469                 status = "disabled";
 470         };
 471
 472         iic3: i2c@e60b0000 {
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 476                 reg = <0 0xe60b0000 0 0x425>;
 477                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 478                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 479                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 480                 dma-names = "tx", "rx";
 481                 status = "disabled";
 482         };
 483
 484         mmcif0: mmc@ee200000 {
 485                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 486                 reg = <0 0xee200000 0 0x80>;
 487                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 489                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 490                 dma-names = "tx", "rx";
 491                 reg-io-width = <4>;
 492                 status = "disabled";
 493                 max-frequency = <97500000>;
 494         };
 495
 496         mmcif1: mmc@ee220000 {
 497                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 498                 reg = <0 0xee220000 0 0x80>;
 499                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 500                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 501                 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
 502                 dma-names = "tx", "rx";
 503                 reg-io-width = <4>;
 504                 status = "disabled";
 505                 max-frequency = <97500000>;
 506         };
 507
 508         pfc: pfc@e6060000 {
 509                 compatible = "renesas,pfc-r8a7790";
 510                 reg = <0 0xe6060000 0 0x250>;
 511         };
 512
 513         sdhi0: sd@ee100000 {
 514                 compatible = "renesas,sdhi-r8a7790";
 515                 reg = <0 0xee100000 0 0x328>;
 516                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 518                 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 519                 dma-names = "tx", "rx";
 520                 status = "disabled";
 521         };
 522
 523         sdhi1: sd@ee120000 {
 524                 compatible = "renesas,sdhi-r8a7790";
 525                 reg = <0 0xee120000 0 0x328>;
 526                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 528                 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
 529                 dma-names = "tx", "rx";
 530                 status = "disabled";
 531         };
 532
 533         sdhi2: sd@ee140000 {
 534                 compatible = "renesas,sdhi-r8a7790";
 535                 reg = <0 0xee140000 0 0x100>;
 536                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 537                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 538                 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 539                 dma-names = "tx", "rx";
 540                 status = "disabled";
 541         };
 542
 543         sdhi3: sd@ee160000 {
 544                 compatible = "renesas,sdhi-r8a7790";
 545                 reg = <0 0xee160000 0 0x100>;
 546                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 548                 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 549                 dma-names = "tx", "rx";
 550                 status = "disabled";
 551         };
 552
 553         scifa0: serial@e6c40000 {
 554                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 555                 reg = <0 0xe6c40000 0 64>;
 556                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 557                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 558                 clock-names = "sci_ick";
 559                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 560                 dma-names = "tx", "rx";
 561                 status = "disabled";
 562         };
 563
 564         scifa1: serial@e6c50000 {
 565                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 566                 reg = <0 0xe6c50000 0 64>;
 567                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 568                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 569                 clock-names = "sci_ick";
 570                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 571                 dma-names = "tx", "rx";
 572                 status = "disabled";
 573         };
 574
 575         scifa2: serial@e6c60000 {
 576                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 577                 reg = <0 0xe6c60000 0 64>;
 578                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 580                 clock-names = "sci_ick";
 581                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 582                 dma-names = "tx", "rx";
 583                 status = "disabled";
 584         };
 585
 586         scifb0: serial@e6c20000 {
 587                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 588                 reg = <0 0xe6c20000 0 64>;
 589                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 590                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 591                 clock-names = "sci_ick";
 592                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 593                 dma-names = "tx", "rx";
 594                 status = "disabled";
 595         };
 596
 597         scifb1: serial@e6c30000 {
 598                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 599                 reg = <0 0xe6c30000 0 64>;
 600                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 601                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 602                 clock-names = "sci_ick";
 603                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 604                 dma-names = "tx", "rx";
 605                 status = "disabled";
 606         };
 607
 608         scifb2: serial@e6ce0000 {
 609                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 610                 reg = <0 0xe6ce0000 0 64>;
 611                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 612                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 613                 clock-names = "sci_ick";
 614                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 615                 dma-names = "tx", "rx";
 616                 status = "disabled";
 617         };
 618
 619         scif0: serial@e6e60000 {
 620                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 621                 reg = <0 0xe6e60000 0 64>;
 622                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 624                 clock-names = "sci_ick";
 625                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 626                 dma-names = "tx", "rx";
 627                 status = "disabled";
 628         };
 629
 630         scif1: serial@e6e68000 {
 631                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 632                 reg = <0 0xe6e68000 0 64>;
 633                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 635                 clock-names = "sci_ick";
 636                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 637                 dma-names = "tx", "rx";
 638                 status = "disabled";
 639         };
 640
 641         hscif0: serial@e62c0000 {
 642                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 643                 reg = <0 0xe62c0000 0 96>;
 644                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 646                 clock-names = "sci_ick";
 647                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 648                 dma-names = "tx", "rx";
 649                 status = "disabled";
 650         };
 651
 652         hscif1: serial@e62c8000 {
 653                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 654                 reg = <0 0xe62c8000 0 96>;
 655                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 656                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 657                 clock-names = "sci_ick";
 658                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 659                 dma-names = "tx", "rx";
 660                 status = "disabled";
 661         };
 662
 663         ether: ethernet@ee700000 {
 664                 compatible = "renesas,ether-r8a7790";
 665                 reg = <0 0xee700000 0 0x400>;
 666                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 667                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 668                 phy-mode = "rmii";
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 status = "disabled";
 672         };
 673
 674         avb: ethernet@e6800000 {
 675                 compatible = "renesas,etheravb-r8a7790";
 676                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 677                 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 status = "disabled";
 682         };
 683
 684         sata0: sata@ee300000 {
 685                 compatible = "renesas,sata-r8a7790";
 686                 reg = <0 0xee300000 0 0x2000>;
 687                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 689                 status = "disabled";
 690         };
 691
 692         sata1: sata@ee500000 {
 693                 compatible = "renesas,sata-r8a7790";
 694                 reg = <0 0xee500000 0 0x2000>;
 695                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 696                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 697                 status = "disabled";
 698         };
 699
 700         hsusb: usb@e6590000 {
 701                 compatible = "renesas,usbhs-r8a7790";
 702                 reg = <0 0xe6590000 0 0x100>;
 703                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 704                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 705                 renesas,buswait = <4>;
 706                 phys = <&usb0 1>;
 707                 phy-names = "usb";
 708                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 709                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 710                 dma-names = "ch0", "ch1", "ch2", "ch3";
 711                 status = "disabled";
 712         };
 713
 714         usbphy: usb-phy@e6590100 {
 715                 compatible = "renesas,usb-phy-r8a7790";
 716                 reg = <0 0xe6590100 0 0x100>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 720                 clock-names = "usbhs";
 721                 status = "disabled";
 722
 723                 usb0: usb-channel@0 {
 724                         reg = <0>;
 725                         #phy-cells = <1>;
 726                 };
 727                 usb2: usb-channel@2 {
 728                         reg = <2>;
 729                         #phy-cells = <1>;
 730                 };
 731         };
 732
 733         vin0: video@e6ef0000 {
 734                 compatible = "renesas,vin-r8a7790";
 735                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 736                 reg = <0 0xe6ef0000 0 0x1000>;
 737                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 738                 status = "disabled";
 739         };
 740
 741         vin1: video@e6ef1000 {
 742                 compatible = "renesas,vin-r8a7790";
 743                 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 744                 reg = <0 0xe6ef1000 0 0x1000>;
 745                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 746                 status = "disabled";
 747         };
 748
 749         vin2: video@e6ef2000 {
 750                 compatible = "renesas,vin-r8a7790";
 751                 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 752                 reg = <0 0xe6ef2000 0 0x1000>;
 753                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 754                 status = "disabled";
 755         };
 756
 757         vin3: video@e6ef3000 {
 758                 compatible = "renesas,vin-r8a7790";
 759                 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 760                 reg = <0 0xe6ef3000 0 0x1000>;
 761                 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
 762                 status = "disabled";
 763         };
 764
 765         vsp1@fe920000 {
 766                 compatible = "renesas,vsp1";
 767                 reg = <0 0xfe920000 0 0x8000>;
 768                 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
 770
 771                 renesas,has-sru;
 772                 renesas,#rpf = <5>;
 773                 renesas,#uds = <1>;
 774                 renesas,#wpf = <4>;
 775         };
 776
 777         vsp1@fe928000 {
 778                 compatible = "renesas,vsp1";
 779                 reg = <0 0xfe928000 0 0x8000>;
 780                 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 781                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
 782
 783                 renesas,has-lut;
 784                 renesas,has-sru;
 785                 renesas,#rpf = <5>;
 786                 renesas,#uds = <3>;
 787                 renesas,#wpf = <4>;
 788         };
 789
 790         vsp1@fe930000 {
 791                 compatible = "renesas,vsp1";
 792                 reg = <0 0xfe930000 0 0x8000>;
 793                 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 794                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
 795
 796                 renesas,has-lif;
 797                 renesas,has-lut;
 798                 renesas,#rpf = <4>;
 799                 renesas,#uds = <1>;
 800                 renesas,#wpf = <4>;
 801         };
 802
 803         vsp1@fe938000 {
 804                 compatible = "renesas,vsp1";
 805                 reg = <0 0xfe938000 0 0x8000>;
 806                 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 807                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
 808
 809                 renesas,has-lif;
 810                 renesas,has-lut;
 811                 renesas,#rpf = <4>;
 812                 renesas,#uds = <1>;
 813                 renesas,#wpf = <4>;
 814         };
 815
 816         du: display@feb00000 {
 817                 compatible = "renesas,du-r8a7790";
 818                 reg = <0 0xfeb00000 0 0x70000>,
 819                       <0 0xfeb90000 0 0x1c>,
 820                       <0 0xfeb94000 0 0x1c>;
 821                 reg-names = "du", "lvds.0", "lvds.1";
 822                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 823                              <0 268 IRQ_TYPE_LEVEL_HIGH>,
 824                              <0 269 IRQ_TYPE_LEVEL_HIGH>;
 825                 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
 826                          <&mstp7_clks R8A7790_CLK_DU1>,
 827                          <&mstp7_clks R8A7790_CLK_DU2>,
 828                          <&mstp7_clks R8A7790_CLK_LVDS0>,
 829                          <&mstp7_clks R8A7790_CLK_LVDS1>;
 830                 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
 831                 status = "disabled";
 832
 833                 ports {
 834                         #address-cells = <1>;
 835                         #size-cells = <0>;
 836
 837                         port@0 {
 838                                 reg = <0>;
 839                                 du_out_rgb: endpoint {
 840                                 };
 841                         };
 842                         port@1 {
 843                                 reg = <1>;
 844                                 du_out_lvds0: endpoint {
 845                                 };
 846                         };
 847                         port@2 {
 848                                 reg = <2>;
 849                                 du_out_lvds1: endpoint {
 850                                 };
 851                         };
 852                 };
 853         };
 854
 855         can0: can@e6e80000 {
 856                 compatible = "renesas,can-r8a7790";
 857                 reg = <0 0xe6e80000 0 0x1000>;
 858                 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
 859                 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
 860                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 861                 clock-names = "clkp1", "clkp2", "can_clk";
 862                 status = "disabled";
 863         };
 864
 865         can1: can@e6e88000 {
 866                 compatible = "renesas,can-r8a7790";
 867                 reg = <0 0xe6e88000 0 0x1000>;
 868                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
 870                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 871                 clock-names = "clkp1", "clkp2", "can_clk";
 872                 status = "disabled";
 873         };
 874
 875         jpu: jpeg-codec@fe980000 {
 876                 compatible = "renesas,jpu-r8a7790";
 877                 reg = <0 0xfe980000 0 0x10300>;
 878                 interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
 879                 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
 880         };
 881
 882         clocks {
 883                 #address-cells = <2>;
 884                 #size-cells = <2>;
 885                 ranges;
 886
 887                 /* External root clock */
 888                 extal_clk: extal_clk {
 889                         compatible = "fixed-clock";
 890                         #clock-cells = <0>;
 891                         /* This value must be overriden by the board. */
 892                         clock-frequency = <0>;
 893                         clock-output-names = "extal";
 894                 };
 895
 896                 /* External PCIe clock - can be overridden by the board */
 897                 pcie_bus_clk: pcie_bus_clk {
 898                         compatible = "fixed-clock";
 899                         #clock-cells = <0>;
 900                         clock-frequency = <100000000>;
 901                         clock-output-names = "pcie_bus";
 902                         status = "disabled";
 903                 };
 904
 905                 /*
 906                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 907                  * default. Boards that provide audio clocks should override them.
 908                  */
 909                 audio_clk_a: audio_clk_a {
 910                         compatible = "fixed-clock";
 911                         #clock-cells = <0>;
 912                         clock-frequency = <0>;
 913                         clock-output-names = "audio_clk_a";
 914                 };
 915                 audio_clk_b: audio_clk_b {
 916                         compatible = "fixed-clock";
 917                         #clock-cells = <0>;
 918                         clock-frequency = <0>;
 919                         clock-output-names = "audio_clk_b";
 920                 };
 921                 audio_clk_c: audio_clk_c {
 922                         compatible = "fixed-clock";
 923                         #clock-cells = <0>;
 924                         clock-frequency = <0>;
 925                         clock-output-names = "audio_clk_c";
 926                 };
 927
 928                 /* External USB clock - can be overridden by the board */
 929                 usb_extal_clk: usb_extal_clk {
 930                         compatible = "fixed-clock";
 931                         #clock-cells = <0>;
 932                         clock-frequency = <48000000>;
 933                         clock-output-names = "usb_extal";
 934                 };
 935
 936                 /* External CAN clock */
 937                 can_clk: can_clk {
 938                         compatible = "fixed-clock";
 939                         #clock-cells = <0>;
 940                         /* This value must be overridden by the board. */
 941                         clock-frequency = <0>;
 942                         clock-output-names = "can_clk";
 943                         status = "disabled";
 944                 };
 945
 946                 /* Special CPG clocks */
 947                 cpg_clocks: cpg_clocks@e6150000 {
 948                         compatible = "renesas,r8a7790-cpg-clocks",
 949                                      "renesas,rcar-gen2-cpg-clocks";
 950                         reg = <0 0xe6150000 0 0x1000>;
 951                         clocks = <&extal_clk &usb_extal_clk>;
 952                         #clock-cells = <1>;
 953                         clock-output-names = "main", "pll0", "pll1", "pll3",
 954                                              "lb", "qspi", "sdh", "sd0", "sd1",
 955                                              "z", "rcan", "adsp";
 956                 };
 957
 958                 /* Variable factor clocks */
 959                 sd2_clk: sd2_clk@e6150078 {
 960                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 961                         reg = <0 0xe6150078 0 4>;
 962                         clocks = <&pll1_div2_clk>;
 963                         #clock-cells = <0>;
 964                         clock-output-names = "sd2";
 965                 };
 966                 sd3_clk: sd3_clk@e615026c {
 967                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 968                         reg = <0 0xe615026c 0 4>;
 969                         clocks = <&pll1_div2_clk>;
 970                         #clock-cells = <0>;
 971                         clock-output-names = "sd3";
 972                 };
 973                 mmc0_clk: mmc0_clk@e6150240 {
 974                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 975                         reg = <0 0xe6150240 0 4>;
 976                         clocks = <&pll1_div2_clk>;
 977                         #clock-cells = <0>;
 978                         clock-output-names = "mmc0";
 979                 };
 980                 mmc1_clk: mmc1_clk@e6150244 {
 981                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 982                         reg = <0 0xe6150244 0 4>;
 983                         clocks = <&pll1_div2_clk>;
 984                         #clock-cells = <0>;
 985                         clock-output-names = "mmc1";
 986                 };
 987                 ssp_clk: ssp_clk@e6150248 {
 988                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 989                         reg = <0 0xe6150248 0 4>;
 990                         clocks = <&pll1_div2_clk>;
 991                         #clock-cells = <0>;
 992                         clock-output-names = "ssp";
 993                 };
 994                 ssprs_clk: ssprs_clk@e615024c {
 995                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 996                         reg = <0 0xe615024c 0 4>;
 997                         clocks = <&pll1_div2_clk>;
 998                         #clock-cells = <0>;
 999                         clock-output-names = "ssprs";
1000                 };
1001
1002                 /* Fixed factor clocks */
1003                 pll1_div2_clk: pll1_div2_clk {
1004                         compatible = "fixed-factor-clock";
1005                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1006                         #clock-cells = <0>;
1007                         clock-div = <2>;
1008                         clock-mult = <1>;
1009                         clock-output-names = "pll1_div2";
1010                 };
1011                 z2_clk: z2_clk {
1012                         compatible = "fixed-factor-clock";
1013                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1014                         #clock-cells = <0>;
1015                         clock-div = <2>;
1016                         clock-mult = <1>;
1017                         clock-output-names = "z2";
1018                 };
1019                 zg_clk: zg_clk {
1020                         compatible = "fixed-factor-clock";
1021                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1022                         #clock-cells = <0>;
1023                         clock-div = <3>;
1024                         clock-mult = <1>;
1025                         clock-output-names = "zg";
1026                 };
1027                 zx_clk: zx_clk {
1028                         compatible = "fixed-factor-clock";
1029                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1030                         #clock-cells = <0>;
1031                         clock-div = <3>;
1032                         clock-mult = <1>;
1033                         clock-output-names = "zx";
1034                 };
1035                 zs_clk: zs_clk {
1036                         compatible = "fixed-factor-clock";
1037                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1038                         #clock-cells = <0>;
1039                         clock-div = <6>;
1040                         clock-mult = <1>;
1041                         clock-output-names = "zs";
1042                 };
1043                 hp_clk: hp_clk {
1044                         compatible = "fixed-factor-clock";
1045                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1046                         #clock-cells = <0>;
1047                         clock-div = <12>;
1048                         clock-mult = <1>;
1049                         clock-output-names = "hp";
1050                 };
1051                 i_clk: i_clk {
1052                         compatible = "fixed-factor-clock";
1053                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1054                         #clock-cells = <0>;
1055                         clock-div = <2>;
1056                         clock-mult = <1>;
1057                         clock-output-names = "i";
1058                 };
1059                 b_clk: b_clk {
1060                         compatible = "fixed-factor-clock";
1061                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1062                         #clock-cells = <0>;
1063                         clock-div = <12>;
1064                         clock-mult = <1>;
1065                         clock-output-names = "b";
1066                 };
1067                 p_clk: p_clk {
1068                         compatible = "fixed-factor-clock";
1069                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1070                         #clock-cells = <0>;
1071                         clock-div = <24>;
1072                         clock-mult = <1>;
1073                         clock-output-names = "p";
1074                 };
1075                 cl_clk: cl_clk {
1076                         compatible = "fixed-factor-clock";
1077                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1078                         #clock-cells = <0>;
1079                         clock-div = <48>;
1080                         clock-mult = <1>;
1081                         clock-output-names = "cl";
1082                 };
1083                 m2_clk: m2_clk {
1084                         compatible = "fixed-factor-clock";
1085                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1086                         #clock-cells = <0>;
1087                         clock-div = <8>;
1088                         clock-mult = <1>;
1089                         clock-output-names = "m2";
1090                 };
1091                 imp_clk: imp_clk {
1092                         compatible = "fixed-factor-clock";
1093                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1094                         #clock-cells = <0>;
1095                         clock-div = <4>;
1096                         clock-mult = <1>;
1097                         clock-output-names = "imp";
1098                 };
1099                 rclk_clk: rclk_clk {
1100                         compatible = "fixed-factor-clock";
1101                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1102                         #clock-cells = <0>;
1103                         clock-div = <(48 * 1024)>;
1104                         clock-mult = <1>;
1105                         clock-output-names = "rclk";
1106                 };
1107                 oscclk_clk: oscclk_clk {
1108                         compatible = "fixed-factor-clock";
1109                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1110                         #clock-cells = <0>;
1111                         clock-div = <(12 * 1024)>;
1112                         clock-mult = <1>;
1113                         clock-output-names = "oscclk";
1114                 };
1115                 zb3_clk: zb3_clk {
1116                         compatible = "fixed-factor-clock";
1117                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1118                         #clock-cells = <0>;
1119                         clock-div = <4>;
1120                         clock-mult = <1>;
1121                         clock-output-names = "zb3";
1122                 };
1123                 zb3d2_clk: zb3d2_clk {
1124                         compatible = "fixed-factor-clock";
1125                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1126                         #clock-cells = <0>;
1127                         clock-div = <8>;
1128                         clock-mult = <1>;
1129                         clock-output-names = "zb3d2";
1130                 };
1131                 ddr_clk: ddr_clk {
1132                         compatible = "fixed-factor-clock";
1133                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1134                         #clock-cells = <0>;
1135                         clock-div = <8>;
1136                         clock-mult = <1>;
1137                         clock-output-names = "ddr";
1138                 };
1139                 mp_clk: mp_clk {
1140                         compatible = "fixed-factor-clock";
1141                         clocks = <&pll1_div2_clk>;
1142                         #clock-cells = <0>;
1143                         clock-div = <15>;
1144                         clock-mult = <1>;
1145                         clock-output-names = "mp";
1146                 };
1147                 cp_clk: cp_clk {
1148                         compatible = "fixed-factor-clock";
1149                         clocks = <&extal_clk>;
1150                         #clock-cells = <0>;
1151                         clock-div = <2>;
1152                         clock-mult = <1>;
1153                         clock-output-names = "cp";
1154                 };
1155
1156                 /* Gate clocks */
1157                 mstp0_clks: mstp0_clks@e6150130 {
1158                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1159                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1160                         clocks = <&mp_clk>;
1161                         #clock-cells = <1>;
1162                         clock-indices = <R8A7790_CLK_MSIOF0>;
1163                         clock-output-names = "msiof0";
1164                 };
1165                 mstp1_clks: mstp1_clks@e6150134 {
1166                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1167                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1168                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1169                                  <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1170                                  <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1171                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1172                         #clock-cells = <1>;
1173                         clock-indices = <
1174                                 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1175                                 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1176                                 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1177                                 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1178                                 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1179                                 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1180                                 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1181                         >;
1182                         clock-output-names =
1183                                 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1184                                 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1185                                 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1186                                 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1187                 };
1188                 mstp2_clks: mstp2_clks@e6150138 {
1189                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1190                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1191                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1192                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1193                                  <&zs_clk>;
1194                         #clock-cells = <1>;
1195                         clock-indices = <
1196                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1197                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1198                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1199                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1200                         >;
1201                         clock-output-names =
1202                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1203                                 "scifb1", "msiof1", "msiof3", "scifb2",
1204                                 "sys-dmac1", "sys-dmac0";
1205                 };
1206                 mstp3_clks: mstp3_clks@e615013c {
1207                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1208                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1209                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1210                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1211                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1212                                  <&hp_clk>, <&hp_clk>;
1213                         #clock-cells = <1>;
1214                         clock-indices = <
1215                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1216                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1217                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1218                                 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1219                         >;
1220                         clock-output-names =
1221                                 "iic2", "tpu0", "mmcif1", "sdhi3",
1222                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1223                                 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1224                                 "usbdmac0", "usbdmac1";
1225                 };
1226                 mstp4_clks: mstp4_clks@e6150140 {
1227                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1228                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1229                         clocks = <&cp_clk>;
1230                         #clock-cells = <1>;
1231                         clock-indices = <R8A7790_CLK_IRQC>;
1232                         clock-output-names = "irqc";
1233                 };
1234                 mstp5_clks: mstp5_clks@e6150144 {
1235                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1236                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1237                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1238                                  <&extal_clk>, <&p_clk>;
1239                         #clock-cells = <1>;
1240                         clock-indices = <
1241                                 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1242                                 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1243                                 R8A7790_CLK_PWM
1244                         >;
1245                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1246                                              "thermal", "pwm";
1247                 };
1248                 mstp7_clks: mstp7_clks@e615014c {
1249                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1250                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1251                         clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1252                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1253                                  <&zx_clk>;
1254                         #clock-cells = <1>;
1255                         clock-indices = <
1256                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1257                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1258                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1259                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1260                         >;
1261                         clock-output-names =
1262                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1263                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1264                 };
1265                 mstp8_clks: mstp8_clks@e6150990 {
1266                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1267                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1268                         clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1269                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1270                                  <&zs_clk>;
1271                         #clock-cells = <1>;
1272                         clock-indices = <
1273                                 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1274                                 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1275                                 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1276                                 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1277                         >;
1278                         clock-output-names =
1279                                 "mlb", "vin3", "vin2", "vin1", "vin0",
1280                                 "etheravb", "ether", "sata1", "sata0";
1281                 };
1282                 mstp9_clks: mstp9_clks@e6150994 {
1283                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1284                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1285                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1286                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
1287                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1288                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1289                         #clock-cells = <1>;
1290                         clock-indices = <
1291                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1292                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1293                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1294                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1295                         >;
1296                         clock-output-names =
1297                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1298                                 "rcan1", "rcan0", "qspi_mod", "iic3",
1299                                 "i2c3", "i2c2", "i2c1", "i2c0";
1300                 };
1301                 mstp10_clks: mstp10_clks@e6150998 {
1302                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1303                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1304                         clocks = <&p_clk>,
1305                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1306                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1307                                 <&p_clk>,
1308                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1309                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1310                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1311                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1312                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1313                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1314                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1315
1316                         #clock-cells = <1>;
1317                         clock-indices = <
1318                                 R8A7790_CLK_SSI_ALL
1319                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1320                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1321                                 R8A7790_CLK_SCU_ALL
1322                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1323                                 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1324                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1325                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1326                         >;
1327                         clock-output-names =
1328                                 "ssi-all",
1329                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1330                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1331                                 "scu-all",
1332                                 "scu-dvc1", "scu-dvc0",
1333                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1334                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1335                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1336                 };
1337         };
1338
1339         qspi: spi@e6b10000 {
1340                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1341                 reg = <0 0xe6b10000 0 0x2c>;
1342                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1343                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1344                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1345                 dma-names = "tx", "rx";
1346                 num-cs = <1>;
1347                 #address-cells = <1>;
1348                 #size-cells = <0>;
1349                 status = "disabled";
1350         };
1351
1352         msiof0: spi@e6e20000 {
1353                 compatible = "renesas,msiof-r8a7790";
1354                 reg = <0 0xe6e20000 0 0x0064>;
1355                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1356                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1357                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1358                 dma-names = "tx", "rx";
1359                 #address-cells = <1>;
1360                 #size-cells = <0>;
1361                 status = "disabled";
1362         };
1363
1364         msiof1: spi@e6e10000 {
1365                 compatible = "renesas,msiof-r8a7790";
1366                 reg = <0 0xe6e10000 0 0x0064>;
1367                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1368                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1369                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1370                 dma-names = "tx", "rx";
1371                 #address-cells = <1>;
1372                 #size-cells = <0>;
1373                 status = "disabled";
1374         };
1375
1376         msiof2: spi@e6e00000 {
1377                 compatible = "renesas,msiof-r8a7790";
1378                 reg = <0 0xe6e00000 0 0x0064>;
1379                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1380                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1381                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1382                 dma-names = "tx", "rx";
1383                 #address-cells = <1>;
1384                 #size-cells = <0>;
1385                 status = "disabled";
1386         };
1387
1388         msiof3: spi@e6c90000 {
1389                 compatible = "renesas,msiof-r8a7790";
1390                 reg = <0 0xe6c90000 0 0x0064>;
1391                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1392                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1393                 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1394                 dma-names = "tx", "rx";
1395                 #address-cells = <1>;
1396                 #size-cells = <0>;
1397                 status = "disabled";
1398         };
1399
1400         xhci: usb@ee000000 {
1401                 compatible = "renesas,xhci-r8a7790";
1402                 reg = <0 0xee000000 0 0xc00>;
1403                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1404                 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1405                 phys = <&usb2 1>;
1406                 phy-names = "usb";
1407                 status = "disabled";
1408         };
1409
1410         pci0: pci@ee090000 {
1411                 compatible = "renesas,pci-r8a7790";
1412                 device_type = "pci";
1413                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1414                 reg = <0 0xee090000 0 0xc00>,
1415                       <0 0xee080000 0 0x1100>;
1416                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1417                 status = "disabled";
1418
1419                 bus-range = <0 0>;
1420                 #address-cells = <3>;
1421                 #size-cells = <2>;
1422                 #interrupt-cells = <1>;
1423                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1424                 interrupt-map-mask = <0xff00 0 0 0x7>;
1425                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1426                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1427                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1428
1429                 usb@0,1 {
1430                         reg = <0x800 0 0 0 0>;
1431                         device_type = "pci";
1432                         phys = <&usb0 0>;
1433                         phy-names = "usb";
1434                 };
1435
1436                 usb@0,2 {
1437                         reg = <0x1000 0 0 0 0>;
1438                         device_type = "pci";
1439                         phys = <&usb0 0>;
1440                         phy-names = "usb";
1441                 };
1442         };
1443
1444         pci1: pci@ee0b0000 {
1445                 compatible = "renesas,pci-r8a7790";
1446                 device_type = "pci";
1447                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1448                 reg = <0 0xee0b0000 0 0xc00>,
1449                       <0 0xee0a0000 0 0x1100>;
1450                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1451                 status = "disabled";
1452
1453                 bus-range = <1 1>;
1454                 #address-cells = <3>;
1455                 #size-cells = <2>;
1456                 #interrupt-cells = <1>;
1457                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1458                 interrupt-map-mask = <0xff00 0 0 0x7>;
1459                 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1460                                  0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1461                                  0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1462         };
1463
1464         pci2: pci@ee0d0000 {
1465                 compatible = "renesas,pci-r8a7790";
1466                 device_type = "pci";
1467                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1468                 reg = <0 0xee0d0000 0 0xc00>,
1469                       <0 0xee0c0000 0 0x1100>;
1470                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1471                 status = "disabled";
1472
1473                 bus-range = <2 2>;
1474                 #address-cells = <3>;
1475                 #size-cells = <2>;
1476                 #interrupt-cells = <1>;
1477                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1478                 interrupt-map-mask = <0xff00 0 0 0x7>;
1479                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1480                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1481                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1482
1483                 usb@0,1 {
1484                         reg = <0x800 0 0 0 0>;
1485                         device_type = "pci";
1486                         phys = <&usb2 0>;
1487                         phy-names = "usb";
1488                 };
1489
1490                 usb@0,2 {
1491                         reg = <0x1000 0 0 0 0>;
1492                         device_type = "pci";
1493                         phys = <&usb2 0>;
1494                         phy-names = "usb";
1495                 };
1496         };
1497
1498         pciec: pcie@fe000000 {
1499                 compatible = "renesas,pcie-r8a7790";
1500                 reg = <0 0xfe000000 0 0x80000>;
1501                 #address-cells = <3>;
1502                 #size-cells = <2>;
1503                 bus-range = <0x00 0xff>;
1504                 device_type = "pci";
1505                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1506                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1507                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1508                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1509                 /* Map all possible DDR as inbound ranges */
1510                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1511                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1512                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1513                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1514                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1515                 #interrupt-cells = <1>;
1516                 interrupt-map-mask = <0 0 0 0>;
1517                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1518                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1519                 clock-names = "pcie", "pcie_bus";
1520                 status = "disabled";
1521         };
1522
1523         rcar_sound: sound@ec500000 {
1524                 /*
1525                  * #sound-dai-cells is required
1526                  *
1527                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1528                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1529                  */
1530                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1531                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1532                         <0 0xec5a0000 0 0x100>,  /* ADG */
1533                         <0 0xec540000 0 0x1000>, /* SSIU */
1534                         <0 0xec541000 0 0x1280>, /* SSI */
1535                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1536                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1537
1538                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1539                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1540                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1541                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1542                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1543                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1544                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1545                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1546                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1547                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1548                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1549                         <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1550                         <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1551                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1552                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1553                 clock-names = "ssi-all",
1554                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1555                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1556                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1557                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1558                                 "ctu.0", "ctu.1",
1559                                 "mix.0", "mix.1",
1560                                 "dvc.0", "dvc.1",
1561                                 "clk_a", "clk_b", "clk_c", "clk_i";
1562
1563                 status = "disabled";
1564
1565                 rcar_sound,dvc {
1566                         dvc0: dvc@0 {
1567                                 dmas = <&audma0 0xbc>;
1568                                 dma-names = "tx";
1569                         };
1570                         dvc1: dvc@1 {
1571                                 dmas = <&audma0 0xbe>;
1572                                 dma-names = "tx";
1573                         };
1574                 };
1575
1576                 rcar_sound,mix {
1577                         mix0: mix@0 { };
1578                         mix1: mix@1 { };
1579                 };
1580
1581                 rcar_sound,ctu {
1582                         ctu00: ctu@0 { };
1583                         ctu01: ctu@1 { };
1584                         ctu02: ctu@2 { };
1585                         ctu03: ctu@3 { };
1586                         ctu10: ctu@4 { };
1587                         ctu11: ctu@5 { };
1588                         ctu12: ctu@6 { };
1589                         ctu13: ctu@7 { };
1590                 };
1591
1592                 rcar_sound,src {
1593                         src0: src@0 {
1594                                 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1595                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1596                                 dma-names = "rx", "tx";
1597                         };
1598                         src1: src@1 {
1599                                 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1600                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1601                                 dma-names = "rx", "tx";
1602                         };
1603                         src2: src@2 {
1604                                 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1605                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1606                                 dma-names = "rx", "tx";
1607                         };
1608                         src3: src@3 {
1609                                 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1610                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1611                                 dma-names = "rx", "tx";
1612                         };
1613                         src4: src@4 {
1614                                 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1615                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1616                                 dma-names = "rx", "tx";
1617                         };
1618                         src5: src@5 {
1619                                 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1620                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1621                                 dma-names = "rx", "tx";
1622                         };
1623                         src6: src@6 {
1624                                 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1625                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1626                                 dma-names = "rx", "tx";
1627                         };
1628                         src7: src@7 {
1629                                 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1630                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1631                                 dma-names = "rx", "tx";
1632                         };
1633                         src8: src@8 {
1634                                 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1635                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1636                                 dma-names = "rx", "tx";
1637                         };
1638                         src9: src@9 {
1639                                 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1640                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1641                                 dma-names = "rx", "tx";
1642                         };
1643                 };
1644
1645                 rcar_sound,ssi {
1646                         ssi0: ssi@0 {
1647                                 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1648                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1649                                 dma-names = "rx", "tx", "rxu", "txu";
1650                         };
1651                         ssi1: ssi@1 {
1652                                  interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1653                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1654                                 dma-names = "rx", "tx", "rxu", "txu";
1655                         };
1656                         ssi2: ssi@2 {
1657                                 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1658                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1659                                 dma-names = "rx", "tx", "rxu", "txu";
1660                         };
1661                         ssi3: ssi@3 {
1662                                 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1663                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1664                                 dma-names = "rx", "tx", "rxu", "txu";
1665                         };
1666                         ssi4: ssi@4 {
1667                                 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1668                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1669                                 dma-names = "rx", "tx", "rxu", "txu";
1670                         };
1671                         ssi5: ssi@5 {
1672                                 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1673                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1674                                 dma-names = "rx", "tx", "rxu", "txu";
1675                         };
1676                         ssi6: ssi@6 {
1677                                 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1678                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1679                                 dma-names = "rx", "tx", "rxu", "txu";
1680                         };
1681                         ssi7: ssi@7 {
1682                                 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1683                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1684                                 dma-names = "rx", "tx", "rxu", "txu";
1685                         };
1686                         ssi8: ssi@8 {
1687                                 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1688                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1689                                 dma-names = "rx", "tx", "rxu", "txu";
1690                         };
1691                         ssi9: ssi@9 {
1692                                 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1693                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1694                                 dma-names = "rx", "tx", "rxu", "txu";
1695                         };
1696                 };
1697         };
1698
1699         ipmmu_sy0: mmu@e6280000 {
1700                 compatible = "renesas,ipmmu-vmsa";
1701                 reg = <0 0xe6280000 0 0x1000>;
1702                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1703                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
1704                 #iommu-cells = <1>;
1705                 status = "disabled";
1706         };
1707
1708         ipmmu_sy1: mmu@e6290000 {
1709                 compatible = "renesas,ipmmu-vmsa";
1710                 reg = <0 0xe6290000 0 0x1000>;
1711                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1712                 #iommu-cells = <1>;
1713                 status = "disabled";
1714         };
1715
1716         ipmmu_ds: mmu@e6740000 {
1717                 compatible = "renesas,ipmmu-vmsa";
1718                 reg = <0 0xe6740000 0 0x1000>;
1719                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1720                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
1721                 #iommu-cells = <1>;
1722                 status = "disabled";
1723         };
1724
1725         ipmmu_mp: mmu@ec680000 {
1726                 compatible = "renesas,ipmmu-vmsa";
1727                 reg = <0 0xec680000 0 0x1000>;
1728                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1729                 #iommu-cells = <1>;
1730                 status = "disabled";
1731         };
1732
1733         ipmmu_mx: mmu@fe951000 {
1734                 compatible = "renesas,ipmmu-vmsa";
1735                 reg = <0 0xfe951000 0 0x1000>;
1736                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1737                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
1738                 #iommu-cells = <1>;
1739                 status = "disabled";
1740         };
1741
1742         ipmmu_rt: mmu@ffc80000 {
1743                 compatible = "renesas,ipmmu-vmsa";
1744                 reg = <0 0xffc80000 0 0x1000>;
1745                 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1746                 #iommu-cells = <1>;
1747                 status = "disabled";
1748         };
1749 };