arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7790-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7790";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &iic0;
  29                 i2c5 = &iic1;
  30                 i2c6 = &iic2;
  31                 i2c7 = &iic3;
  32                 spi0 = &qspi;
  33                 spi1 = &msiof0;
  34                 spi2 = &msiof1;
  35                 spi3 = &msiof2;
  36                 spi4 = &msiof3;
  37                 vin0 = &vin0;
  38                 vin1 = &vin1;
  39                 vin2 = &vin2;
  40                 vin3 = &vin3;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0>;
  51                         clock-frequency = <1300000000>;
  52                         voltage-tolerance = <1>; /* 1% */
  53                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  54                         clock-latency = <300000>; /* 300 us */
  55
  56                         /* kHz - uV - OPPs unknown yet */
  57                         operating-points = <1400000 1000000>,
  58                                            <1225000 1000000>,
  59                                            <1050000 1000000>,
  60                                            < 875000 1000000>,
  61                                            < 700000 1000000>,
  62                                            < 350000 1000000>;
  63                 };
  64
  65                 cpu1: cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <1>;
  69                         clock-frequency = <1300000000>;
  70                 };
  71
  72                 cpu2: cpu@2 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a15";
  75                         reg = <2>;
  76                         clock-frequency = <1300000000>;
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a15";
  82                         reg = <3>;
  83                         clock-frequency = <1300000000>;
  84                 };
  85
  86                 cpu4: cpu@4 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a7";
  89                         reg = <0x100>;
  90                         clock-frequency = <780000000>;
  91                 };
  92
  93                 cpu5: cpu@5 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         reg = <0x101>;
  97                         clock-frequency = <780000000>;
  98                 };
  99
 100                 cpu6: cpu@6 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a7";
 103                         reg = <0x102>;
 104                         clock-frequency = <780000000>;
 105                 };
 106
 107                 cpu7: cpu@7 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a7";
 110                         reg = <0x103>;
 111                         clock-frequency = <780000000>;
 112                 };
 113         };
 114
 115         gic: interrupt-controller@f1001000 {
 116                 compatible = "arm,gic-400";
 117                 #interrupt-cells = <3>;
 118                 #address-cells = <0>;
 119                 interrupt-controller;
 120                 reg = <0 0xf1001000 0 0x1000>,
 121                         <0 0xf1002000 0 0x1000>,
 122                         <0 0xf1004000 0 0x2000>,
 123                         <0 0xf1006000 0 0x2000>;
 124                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 125         };
 126
 127         gpio0: gpio@e6050000 {
 128                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 129                 reg = <0 0xe6050000 0 0x50>;
 130                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 131                 #gpio-cells = <2>;
 132                 gpio-controller;
 133                 gpio-ranges = <&pfc 0 0 32>;
 134                 #interrupt-cells = <2>;
 135                 interrupt-controller;
 136                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 137         };
 138
 139         gpio1: gpio@e6051000 {
 140                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 141                 reg = <0 0xe6051000 0 0x50>;
 142                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 143                 #gpio-cells = <2>;
 144                 gpio-controller;
 145                 gpio-ranges = <&pfc 0 32 32>;
 146                 #interrupt-cells = <2>;
 147                 interrupt-controller;
 148                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 149         };
 150
 151         gpio2: gpio@e6052000 {
 152                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 153                 reg = <0 0xe6052000 0 0x50>;
 154                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 155                 #gpio-cells = <2>;
 156                 gpio-controller;
 157                 gpio-ranges = <&pfc 0 64 32>;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 161         };
 162
 163         gpio3: gpio@e6053000 {
 164                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 165                 reg = <0 0xe6053000 0 0x50>;
 166                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 167                 #gpio-cells = <2>;
 168                 gpio-controller;
 169                 gpio-ranges = <&pfc 0 96 32>;
 170                 #interrupt-cells = <2>;
 171                 interrupt-controller;
 172                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 173         };
 174
 175         gpio4: gpio@e6054000 {
 176                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 177                 reg = <0 0xe6054000 0 0x50>;
 178                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 179                 #gpio-cells = <2>;
 180                 gpio-controller;
 181                 gpio-ranges = <&pfc 0 128 32>;
 182                 #interrupt-cells = <2>;
 183                 interrupt-controller;
 184                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 185         };
 186
 187         gpio5: gpio@e6055000 {
 188                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 189                 reg = <0 0xe6055000 0 0x50>;
 190                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 191                 #gpio-cells = <2>;
 192                 gpio-controller;
 193                 gpio-ranges = <&pfc 0 160 32>;
 194                 #interrupt-cells = <2>;
 195                 interrupt-controller;
 196                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 197         };
 198
 199         thermal@e61f0000 {
 200                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 201                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 202                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 204         };
 205
 206         timer {
 207                 compatible = "arm,armv7-timer";
 208                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 211                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 212         };
 213
 214         cmt0: timer@ffca0000 {
 215                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 216                 reg = <0 0xffca0000 0 0x1004>;
 217                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 218                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 220                 clock-names = "fck";
 221
 222                 renesas,channels-mask = <0x60>;
 223
 224                 status = "disabled";
 225         };
 226
 227         cmt1: timer@e6130000 {
 228                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 229                 reg = <0 0xe6130000 0 0x1004>;
 230                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 231                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 232                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 237                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 239                 clock-names = "fck";
 240
 241                 renesas,channels-mask = <0xff>;
 242
 243                 status = "disabled";
 244         };
 245
 246         irqc0: interrupt-controller@e61c0000 {
 247                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 248                 #interrupt-cells = <2>;
 249                 interrupt-controller;
 250                 reg = <0 0xe61c0000 0 0x200>;
 251                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 252                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 253                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 254                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
 256         };
 257
 258         dmac0: dma-controller@e6700000 {
 259                 compatible = "renesas,rcar-dmac";
 260                 reg = <0 0xe6700000 0 0x20000>;
 261                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 262                               0 200 IRQ_TYPE_LEVEL_HIGH
 263                               0 201 IRQ_TYPE_LEVEL_HIGH
 264                               0 202 IRQ_TYPE_LEVEL_HIGH
 265                               0 203 IRQ_TYPE_LEVEL_HIGH
 266                               0 204 IRQ_TYPE_LEVEL_HIGH
 267                               0 205 IRQ_TYPE_LEVEL_HIGH
 268                               0 206 IRQ_TYPE_LEVEL_HIGH
 269                               0 207 IRQ_TYPE_LEVEL_HIGH
 270                               0 208 IRQ_TYPE_LEVEL_HIGH
 271                               0 209 IRQ_TYPE_LEVEL_HIGH
 272                               0 210 IRQ_TYPE_LEVEL_HIGH
 273                               0 211 IRQ_TYPE_LEVEL_HIGH
 274                               0 212 IRQ_TYPE_LEVEL_HIGH
 275                               0 213 IRQ_TYPE_LEVEL_HIGH
 276                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 277                 interrupt-names = "error",
 278                                 "ch0", "ch1", "ch2", "ch3",
 279                                 "ch4", "ch5", "ch6", "ch7",
 280                                 "ch8", "ch9", "ch10", "ch11",
 281                                 "ch12", "ch13", "ch14";
 282                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 283                 clock-names = "fck";
 284                 #dma-cells = <1>;
 285                 dma-channels = <15>;
 286         };
 287
 288         dmac1: dma-controller@e6720000 {
 289                 compatible = "renesas,rcar-dmac";
 290                 reg = <0 0xe6720000 0 0x20000>;
 291                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 292                               0 216 IRQ_TYPE_LEVEL_HIGH
 293                               0 217 IRQ_TYPE_LEVEL_HIGH
 294                               0 218 IRQ_TYPE_LEVEL_HIGH
 295                               0 219 IRQ_TYPE_LEVEL_HIGH
 296                               0 308 IRQ_TYPE_LEVEL_HIGH
 297                               0 309 IRQ_TYPE_LEVEL_HIGH
 298                               0 310 IRQ_TYPE_LEVEL_HIGH
 299                               0 311 IRQ_TYPE_LEVEL_HIGH
 300                               0 312 IRQ_TYPE_LEVEL_HIGH
 301                               0 313 IRQ_TYPE_LEVEL_HIGH
 302                               0 314 IRQ_TYPE_LEVEL_HIGH
 303                               0 315 IRQ_TYPE_LEVEL_HIGH
 304                               0 316 IRQ_TYPE_LEVEL_HIGH
 305                               0 317 IRQ_TYPE_LEVEL_HIGH
 306                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 307                 interrupt-names = "error",
 308                                 "ch0", "ch1", "ch2", "ch3",
 309                                 "ch4", "ch5", "ch6", "ch7",
 310                                 "ch8", "ch9", "ch10", "ch11",
 311                                 "ch12", "ch13", "ch14";
 312                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 313                 clock-names = "fck";
 314                 #dma-cells = <1>;
 315                 dma-channels = <15>;
 316         };
 317
 318         audma0: dma-controller@ec700000 {
 319                 compatible = "renesas,rcar-dmac";
 320                 reg = <0 0xec700000 0 0x10000>;
 321                 interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
 322                                  0 320 IRQ_TYPE_LEVEL_HIGH
 323                                  0 321 IRQ_TYPE_LEVEL_HIGH
 324                                  0 322 IRQ_TYPE_LEVEL_HIGH
 325                                  0 323 IRQ_TYPE_LEVEL_HIGH
 326                                  0 324 IRQ_TYPE_LEVEL_HIGH
 327                                  0 325 IRQ_TYPE_LEVEL_HIGH
 328                                  0 326 IRQ_TYPE_LEVEL_HIGH
 329                                  0 327 IRQ_TYPE_LEVEL_HIGH
 330                                  0 328 IRQ_TYPE_LEVEL_HIGH
 331                                  0 329 IRQ_TYPE_LEVEL_HIGH
 332                                  0 330 IRQ_TYPE_LEVEL_HIGH
 333                                  0 331 IRQ_TYPE_LEVEL_HIGH
 334                                  0 332 IRQ_TYPE_LEVEL_HIGH>;
 335                 interrupt-names = "error",
 336                                 "ch0", "ch1", "ch2", "ch3",
 337                                 "ch4", "ch5", "ch6", "ch7",
 338                                 "ch8", "ch9", "ch10", "ch11",
 339                                 "ch12";
 340                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
 341                 clock-names = "fck";
 342                 #dma-cells = <1>;
 343                 dma-channels = <13>;
 344         };
 345
 346         audma1: dma-controller@ec720000 {
 347                 compatible = "renesas,rcar-dmac";
 348                 reg = <0 0xec720000 0 0x10000>;
 349                 interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
 350                                  0 333 IRQ_TYPE_LEVEL_HIGH
 351                                  0 334 IRQ_TYPE_LEVEL_HIGH
 352                                  0 335 IRQ_TYPE_LEVEL_HIGH
 353                                  0 336 IRQ_TYPE_LEVEL_HIGH
 354                                  0 337 IRQ_TYPE_LEVEL_HIGH
 355                                  0 338 IRQ_TYPE_LEVEL_HIGH
 356                                  0 339 IRQ_TYPE_LEVEL_HIGH
 357                                  0 340 IRQ_TYPE_LEVEL_HIGH
 358                                  0 341 IRQ_TYPE_LEVEL_HIGH
 359                                  0 342 IRQ_TYPE_LEVEL_HIGH
 360                                  0 343 IRQ_TYPE_LEVEL_HIGH
 361                                  0 344 IRQ_TYPE_LEVEL_HIGH
 362                                  0 345 IRQ_TYPE_LEVEL_HIGH>;
 363                 interrupt-names = "error",
 364                                 "ch0", "ch1", "ch2", "ch3",
 365                                 "ch4", "ch5", "ch6", "ch7",
 366                                 "ch8", "ch9", "ch10", "ch11",
 367                                 "ch12";
 368                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
 369                 clock-names = "fck";
 370                 #dma-cells = <1>;
 371                 dma-channels = <13>;
 372         };
 373
 374         usb_dmac0: dma-controller@e65a0000 {
 375                 compatible = "renesas,usb-dmac";
 376                 reg = <0 0xe65a0000 0 0x100>;
 377                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
 378                               0 109 IRQ_TYPE_LEVEL_HIGH>;
 379                 interrupt-names = "ch0", "ch1";
 380                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
 381                 #dma-cells = <1>;
 382                 dma-channels = <2>;
 383         };
 384
 385         usb_dmac1: dma-controller@e65b0000 {
 386                 compatible = "renesas,usb-dmac";
 387                 reg = <0 0xe65b0000 0 0x100>;
 388                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
 389                               0 110 IRQ_TYPE_LEVEL_HIGH>;
 390                 interrupt-names = "ch0", "ch1";
 391                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
 392                 #dma-cells = <1>;
 393                 dma-channels = <2>;
 394         };
 395
 396         i2c0: i2c@e6508000 {
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 compatible = "renesas,i2c-r8a7790";
 400                 reg = <0 0xe6508000 0 0x40>;
 401                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 403                 status = "disabled";
 404         };
 405
 406         i2c1: i2c@e6518000 {
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 compatible = "renesas,i2c-r8a7790";
 410                 reg = <0 0xe6518000 0 0x40>;
 411                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 413                 status = "disabled";
 414         };
 415
 416         i2c2: i2c@e6530000 {
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 compatible = "renesas,i2c-r8a7790";
 420                 reg = <0 0xe6530000 0 0x40>;
 421                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 423                 status = "disabled";
 424         };
 425
 426         i2c3: i2c@e6540000 {
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 compatible = "renesas,i2c-r8a7790";
 430                 reg = <0 0xe6540000 0 0x40>;
 431                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 432                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 433                 status = "disabled";
 434         };
 435
 436         iic0: i2c@e6500000 {
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 440                 reg = <0 0xe6500000 0 0x425>;
 441                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 443                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 444                 dma-names = "tx", "rx";
 445                 status = "disabled";
 446         };
 447
 448         iic1: i2c@e6510000 {
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 452                 reg = <0 0xe6510000 0 0x425>;
 453                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 455                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 456                 dma-names = "tx", "rx";
 457                 status = "disabled";
 458         };
 459
 460         iic2: i2c@e6520000 {
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 464                 reg = <0 0xe6520000 0 0x425>;
 465                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 466                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 467                 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
 468                 dma-names = "tx", "rx";
 469                 status = "disabled";
 470         };
 471
 472         iic3: i2c@e60b0000 {
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 476                 reg = <0 0xe60b0000 0 0x425>;
 477                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 478                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 479                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 480                 dma-names = "tx", "rx";
 481                 status = "disabled";
 482         };
 483
 484         mmcif0: mmc@ee200000 {
 485                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 486                 reg = <0 0xee200000 0 0x80>;
 487                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 489                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 490                 dma-names = "tx", "rx";
 491                 reg-io-width = <4>;
 492                 status = "disabled";
 493                 max-frequency = <97500000>;
 494         };
 495
 496         mmcif1: mmc@ee220000 {
 497                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 498                 reg = <0 0xee220000 0 0x80>;
 499                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 500                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 501                 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
 502                 dma-names = "tx", "rx";
 503                 reg-io-width = <4>;
 504                 status = "disabled";
 505                 max-frequency = <97500000>;
 506         };
 507
 508         pfc: pfc@e6060000 {
 509                 compatible = "renesas,pfc-r8a7790";
 510                 reg = <0 0xe6060000 0 0x250>;
 511         };
 512
 513         sdhi0: sd@ee100000 {
 514                 compatible = "renesas,sdhi-r8a7790";
 515                 reg = <0 0xee100000 0 0x328>;
 516                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 518                 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 519                 dma-names = "tx", "rx";
 520                 status = "disabled";
 521         };
 522
 523         sdhi1: sd@ee120000 {
 524                 compatible = "renesas,sdhi-r8a7790";
 525                 reg = <0 0xee120000 0 0x328>;
 526                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 528                 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
 529                 dma-names = "tx", "rx";
 530                 status = "disabled";
 531         };
 532
 533         sdhi2: sd@ee140000 {
 534                 compatible = "renesas,sdhi-r8a7790";
 535                 reg = <0 0xee140000 0 0x100>;
 536                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 537                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 538                 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 539                 dma-names = "tx", "rx";
 540                 status = "disabled";
 541         };
 542
 543         sdhi3: sd@ee160000 {
 544                 compatible = "renesas,sdhi-r8a7790";
 545                 reg = <0 0xee160000 0 0x100>;
 546                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 548                 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 549                 dma-names = "tx", "rx";
 550                 status = "disabled";
 551         };
 552
 553         scifa0: serial@e6c40000 {
 554                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 555                 reg = <0 0xe6c40000 0 64>;
 556                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 557                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 558                 clock-names = "sci_ick";
 559                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 560                 dma-names = "tx", "rx";
 561                 status = "disabled";
 562         };
 563
 564         scifa1: serial@e6c50000 {
 565                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 566                 reg = <0 0xe6c50000 0 64>;
 567                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 568                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 569                 clock-names = "sci_ick";
 570                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 571                 dma-names = "tx", "rx";
 572                 status = "disabled";
 573         };
 574
 575         scifa2: serial@e6c60000 {
 576                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 577                 reg = <0 0xe6c60000 0 64>;
 578                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 580                 clock-names = "sci_ick";
 581                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 582                 dma-names = "tx", "rx";
 583                 status = "disabled";
 584         };
 585
 586         scifb0: serial@e6c20000 {
 587                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 588                 reg = <0 0xe6c20000 0 64>;
 589                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 590                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 591                 clock-names = "sci_ick";
 592                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 593                 dma-names = "tx", "rx";
 594                 status = "disabled";
 595         };
 596
 597         scifb1: serial@e6c30000 {
 598                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 599                 reg = <0 0xe6c30000 0 64>;
 600                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 601                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 602                 clock-names = "sci_ick";
 603                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 604                 dma-names = "tx", "rx";
 605                 status = "disabled";
 606         };
 607
 608         scifb2: serial@e6ce0000 {
 609                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 610                 reg = <0 0xe6ce0000 0 64>;
 611                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 612                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 613                 clock-names = "sci_ick";
 614                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 615                 dma-names = "tx", "rx";
 616                 status = "disabled";
 617         };
 618
 619         scif0: serial@e6e60000 {
 620                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 621                 reg = <0 0xe6e60000 0 64>;
 622                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 623                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 624                 clock-names = "sci_ick";
 625                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 626                 dma-names = "tx", "rx";
 627                 status = "disabled";
 628         };
 629
 630         scif1: serial@e6e68000 {
 631                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 632                 reg = <0 0xe6e68000 0 64>;
 633                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 635                 clock-names = "sci_ick";
 636                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 637                 dma-names = "tx", "rx";
 638                 status = "disabled";
 639         };
 640
 641         hscif0: serial@e62c0000 {
 642                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 643                 reg = <0 0xe62c0000 0 96>;
 644                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 646                 clock-names = "sci_ick";
 647                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 648                 dma-names = "tx", "rx";
 649                 status = "disabled";
 650         };
 651
 652         hscif1: serial@e62c8000 {
 653                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 654                 reg = <0 0xe62c8000 0 96>;
 655                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 656                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 657                 clock-names = "sci_ick";
 658                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 659                 dma-names = "tx", "rx";
 660                 status = "disabled";
 661         };
 662
 663         ether: ethernet@ee700000 {
 664                 compatible = "renesas,ether-r8a7790";
 665                 reg = <0 0xee700000 0 0x400>;
 666                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 667                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 668                 phy-mode = "rmii";
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 status = "disabled";
 672         };
 673
 674         avb: ethernet@e6800000 {
 675                 compatible = "renesas,etheravb-r8a7790";
 676                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 677                 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 status = "disabled";
 682         };
 683
 684         sata0: sata@ee300000 {
 685                 compatible = "renesas,sata-r8a7790";
 686                 reg = <0 0xee300000 0 0x2000>;
 687                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 689                 status = "disabled";
 690         };
 691
 692         sata1: sata@ee500000 {
 693                 compatible = "renesas,sata-r8a7790";
 694                 reg = <0 0xee500000 0 0x2000>;
 695                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 696                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 697                 status = "disabled";
 698         };
 699
 700         hsusb: usb@e6590000 {
 701                 compatible = "renesas,usbhs-r8a7790";
 702                 reg = <0 0xe6590000 0 0x100>;
 703                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 704                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 705                 renesas,buswait = <4>;
 706                 phys = <&usb0 1>;
 707                 phy-names = "usb";
 708                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 709                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 710                 dma-names = "ch0", "ch1", "ch2", "ch3";
 711                 status = "disabled";
 712         };
 713
 714         usbphy: usb-phy@e6590100 {
 715                 compatible = "renesas,usb-phy-r8a7790";
 716                 reg = <0 0xe6590100 0 0x100>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 720                 clock-names = "usbhs";
 721                 status = "disabled";
 722
 723                 usb0: usb-channel@0 {
 724                         reg = <0>;
 725                         #phy-cells = <1>;
 726                 };
 727                 usb2: usb-channel@2 {
 728                         reg = <2>;
 729                         #phy-cells = <1>;
 730                 };
 731         };
 732
 733         vin0: video@e6ef0000 {
 734                 compatible = "renesas,vin-r8a7790";
 735                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 736                 reg = <0 0xe6ef0000 0 0x1000>;
 737                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 738                 status = "disabled";
 739         };
 740
 741         vin1: video@e6ef1000 {
 742                 compatible = "renesas,vin-r8a7790";
 743                 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 744                 reg = <0 0xe6ef1000 0 0x1000>;
 745                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 746                 status = "disabled";
 747         };
 748
 749         vin2: video@e6ef2000 {
 750                 compatible = "renesas,vin-r8a7790";
 751                 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 752                 reg = <0 0xe6ef2000 0 0x1000>;
 753                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 754                 status = "disabled";
 755         };
 756
 757         vin3: video@e6ef3000 {
 758                 compatible = "renesas,vin-r8a7790";
 759                 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 760                 reg = <0 0xe6ef3000 0 0x1000>;
 761                 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
 762                 status = "disabled";
 763         };
 764
 765         vsp1@fe920000 {
 766                 compatible = "renesas,vsp1";
 767                 reg = <0 0xfe920000 0 0x8000>;
 768                 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
 770
 771                 renesas,has-sru;
 772                 renesas,#rpf = <5>;
 773                 renesas,#uds = <1>;
 774                 renesas,#wpf = <4>;
 775         };
 776
 777         vsp1@fe928000 {
 778                 compatible = "renesas,vsp1";
 779                 reg = <0 0xfe928000 0 0x8000>;
 780                 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 781                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
 782
 783                 renesas,has-lut;
 784                 renesas,has-sru;
 785                 renesas,#rpf = <5>;
 786                 renesas,#uds = <3>;
 787                 renesas,#wpf = <4>;
 788         };
 789
 790         vsp1@fe930000 {
 791                 compatible = "renesas,vsp1";
 792                 reg = <0 0xfe930000 0 0x8000>;
 793                 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 794                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
 795
 796                 renesas,has-lif;
 797                 renesas,has-lut;
 798                 renesas,#rpf = <4>;
 799                 renesas,#uds = <1>;
 800                 renesas,#wpf = <4>;
 801         };
 802
 803         vsp1@fe938000 {
 804                 compatible = "renesas,vsp1";
 805                 reg = <0 0xfe938000 0 0x8000>;
 806                 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 807                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
 808
 809                 renesas,has-lif;
 810                 renesas,has-lut;
 811                 renesas,#rpf = <4>;
 812                 renesas,#uds = <1>;
 813                 renesas,#wpf = <4>;
 814         };
 815
 816         du: display@feb00000 {
 817                 compatible = "renesas,du-r8a7790";
 818                 reg = <0 0xfeb00000 0 0x70000>,
 819                       <0 0xfeb90000 0 0x1c>,
 820                       <0 0xfeb94000 0 0x1c>;
 821                 reg-names = "du", "lvds.0", "lvds.1";
 822                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 823                              <0 268 IRQ_TYPE_LEVEL_HIGH>,
 824                              <0 269 IRQ_TYPE_LEVEL_HIGH>;
 825                 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
 826                          <&mstp7_clks R8A7790_CLK_DU1>,
 827                          <&mstp7_clks R8A7790_CLK_DU2>,
 828                          <&mstp7_clks R8A7790_CLK_LVDS0>,
 829                          <&mstp7_clks R8A7790_CLK_LVDS1>;
 830                 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
 831                 status = "disabled";
 832
 833                 ports {
 834                         #address-cells = <1>;
 835                         #size-cells = <0>;
 836
 837                         port@0 {
 838                                 reg = <0>;
 839                                 du_out_rgb: endpoint {
 840                                 };
 841                         };
 842                         port@1 {
 843                                 reg = <1>;
 844                                 du_out_lvds0: endpoint {
 845                                 };
 846                         };
 847                         port@2 {
 848                                 reg = <2>;
 849                                 du_out_lvds1: endpoint {
 850                                 };
 851                         };
 852                 };
 853         };
 854
 855         can0: can@e6e80000 {
 856                 compatible = "renesas,can-r8a7790";
 857                 reg = <0 0xe6e80000 0 0x1000>;
 858                 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
 859                 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
 860                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 861                 clock-names = "clkp1", "clkp2", "can_clk";
 862                 status = "disabled";
 863         };
 864
 865         can1: can@e6e88000 {
 866                 compatible = "renesas,can-r8a7790";
 867                 reg = <0 0xe6e88000 0 0x1000>;
 868                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
 870                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 871                 clock-names = "clkp1", "clkp2", "can_clk";
 872                 status = "disabled";
 873         };
 874
 875         clocks {
 876                 #address-cells = <2>;
 877                 #size-cells = <2>;
 878                 ranges;
 879
 880                 /* External root clock */
 881                 extal_clk: extal_clk {
 882                         compatible = "fixed-clock";
 883                         #clock-cells = <0>;
 884                         /* This value must be overriden by the board. */
 885                         clock-frequency = <0>;
 886                         clock-output-names = "extal";
 887                 };
 888
 889                 /* External PCIe clock - can be overridden by the board */
 890                 pcie_bus_clk: pcie_bus_clk {
 891                         compatible = "fixed-clock";
 892                         #clock-cells = <0>;
 893                         clock-frequency = <100000000>;
 894                         clock-output-names = "pcie_bus";
 895                         status = "disabled";
 896                 };
 897
 898                 /*
 899                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 900                  * default. Boards that provide audio clocks should override them.
 901                  */
 902                 audio_clk_a: audio_clk_a {
 903                         compatible = "fixed-clock";
 904                         #clock-cells = <0>;
 905                         clock-frequency = <0>;
 906                         clock-output-names = "audio_clk_a";
 907                 };
 908                 audio_clk_b: audio_clk_b {
 909                         compatible = "fixed-clock";
 910                         #clock-cells = <0>;
 911                         clock-frequency = <0>;
 912                         clock-output-names = "audio_clk_b";
 913                 };
 914                 audio_clk_c: audio_clk_c {
 915                         compatible = "fixed-clock";
 916                         #clock-cells = <0>;
 917                         clock-frequency = <0>;
 918                         clock-output-names = "audio_clk_c";
 919                 };
 920
 921                 /* External USB clock - can be overridden by the board */
 922                 usb_extal_clk: usb_extal_clk {
 923                         compatible = "fixed-clock";
 924                         #clock-cells = <0>;
 925                         clock-frequency = <48000000>;
 926                         clock-output-names = "usb_extal";
 927                 };
 928
 929                 /* External CAN clock */
 930                 can_clk: can_clk {
 931                         compatible = "fixed-clock";
 932                         #clock-cells = <0>;
 933                         /* This value must be overridden by the board. */
 934                         clock-frequency = <0>;
 935                         clock-output-names = "can_clk";
 936                         status = "disabled";
 937                 };
 938
 939                 /* Special CPG clocks */
 940                 cpg_clocks: cpg_clocks@e6150000 {
 941                         compatible = "renesas,r8a7790-cpg-clocks",
 942                                      "renesas,rcar-gen2-cpg-clocks";
 943                         reg = <0 0xe6150000 0 0x1000>;
 944                         clocks = <&extal_clk &usb_extal_clk>;
 945                         #clock-cells = <1>;
 946                         clock-output-names = "main", "pll0", "pll1", "pll3",
 947                                              "lb", "qspi", "sdh", "sd0", "sd1",
 948                                              "z", "rcan", "adsp";
 949                 };
 950
 951                 /* Variable factor clocks */
 952                 sd2_clk: sd2_clk@e6150078 {
 953                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 954                         reg = <0 0xe6150078 0 4>;
 955                         clocks = <&pll1_div2_clk>;
 956                         #clock-cells = <0>;
 957                         clock-output-names = "sd2";
 958                 };
 959                 sd3_clk: sd3_clk@e615026c {
 960                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 961                         reg = <0 0xe615026c 0 4>;
 962                         clocks = <&pll1_div2_clk>;
 963                         #clock-cells = <0>;
 964                         clock-output-names = "sd3";
 965                 };
 966                 mmc0_clk: mmc0_clk@e6150240 {
 967                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 968                         reg = <0 0xe6150240 0 4>;
 969                         clocks = <&pll1_div2_clk>;
 970                         #clock-cells = <0>;
 971                         clock-output-names = "mmc0";
 972                 };
 973                 mmc1_clk: mmc1_clk@e6150244 {
 974                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 975                         reg = <0 0xe6150244 0 4>;
 976                         clocks = <&pll1_div2_clk>;
 977                         #clock-cells = <0>;
 978                         clock-output-names = "mmc1";
 979                 };
 980                 ssp_clk: ssp_clk@e6150248 {
 981                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 982                         reg = <0 0xe6150248 0 4>;
 983                         clocks = <&pll1_div2_clk>;
 984                         #clock-cells = <0>;
 985                         clock-output-names = "ssp";
 986                 };
 987                 ssprs_clk: ssprs_clk@e615024c {
 988                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 989                         reg = <0 0xe615024c 0 4>;
 990                         clocks = <&pll1_div2_clk>;
 991                         #clock-cells = <0>;
 992                         clock-output-names = "ssprs";
 993                 };
 994
 995                 /* Fixed factor clocks */
 996                 pll1_div2_clk: pll1_div2_clk {
 997                         compatible = "fixed-factor-clock";
 998                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 999                         #clock-cells = <0>;
1000                         clock-div = <2>;
1001                         clock-mult = <1>;
1002                         clock-output-names = "pll1_div2";
1003                 };
1004                 z2_clk: z2_clk {
1005                         compatible = "fixed-factor-clock";
1006                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1007                         #clock-cells = <0>;
1008                         clock-div = <2>;
1009                         clock-mult = <1>;
1010                         clock-output-names = "z2";
1011                 };
1012                 zg_clk: zg_clk {
1013                         compatible = "fixed-factor-clock";
1014                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1015                         #clock-cells = <0>;
1016                         clock-div = <3>;
1017                         clock-mult = <1>;
1018                         clock-output-names = "zg";
1019                 };
1020                 zx_clk: zx_clk {
1021                         compatible = "fixed-factor-clock";
1022                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1023                         #clock-cells = <0>;
1024                         clock-div = <3>;
1025                         clock-mult = <1>;
1026                         clock-output-names = "zx";
1027                 };
1028                 zs_clk: zs_clk {
1029                         compatible = "fixed-factor-clock";
1030                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1031                         #clock-cells = <0>;
1032                         clock-div = <6>;
1033                         clock-mult = <1>;
1034                         clock-output-names = "zs";
1035                 };
1036                 hp_clk: hp_clk {
1037                         compatible = "fixed-factor-clock";
1038                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1039                         #clock-cells = <0>;
1040                         clock-div = <12>;
1041                         clock-mult = <1>;
1042                         clock-output-names = "hp";
1043                 };
1044                 i_clk: i_clk {
1045                         compatible = "fixed-factor-clock";
1046                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1047                         #clock-cells = <0>;
1048                         clock-div = <2>;
1049                         clock-mult = <1>;
1050                         clock-output-names = "i";
1051                 };
1052                 b_clk: b_clk {
1053                         compatible = "fixed-factor-clock";
1054                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1055                         #clock-cells = <0>;
1056                         clock-div = <12>;
1057                         clock-mult = <1>;
1058                         clock-output-names = "b";
1059                 };
1060                 p_clk: p_clk {
1061                         compatible = "fixed-factor-clock";
1062                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1063                         #clock-cells = <0>;
1064                         clock-div = <24>;
1065                         clock-mult = <1>;
1066                         clock-output-names = "p";
1067                 };
1068                 cl_clk: cl_clk {
1069                         compatible = "fixed-factor-clock";
1070                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1071                         #clock-cells = <0>;
1072                         clock-div = <48>;
1073                         clock-mult = <1>;
1074                         clock-output-names = "cl";
1075                 };
1076                 m2_clk: m2_clk {
1077                         compatible = "fixed-factor-clock";
1078                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1079                         #clock-cells = <0>;
1080                         clock-div = <8>;
1081                         clock-mult = <1>;
1082                         clock-output-names = "m2";
1083                 };
1084                 imp_clk: imp_clk {
1085                         compatible = "fixed-factor-clock";
1086                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1087                         #clock-cells = <0>;
1088                         clock-div = <4>;
1089                         clock-mult = <1>;
1090                         clock-output-names = "imp";
1091                 };
1092                 rclk_clk: rclk_clk {
1093                         compatible = "fixed-factor-clock";
1094                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1095                         #clock-cells = <0>;
1096                         clock-div = <(48 * 1024)>;
1097                         clock-mult = <1>;
1098                         clock-output-names = "rclk";
1099                 };
1100                 oscclk_clk: oscclk_clk {
1101                         compatible = "fixed-factor-clock";
1102                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1103                         #clock-cells = <0>;
1104                         clock-div = <(12 * 1024)>;
1105                         clock-mult = <1>;
1106                         clock-output-names = "oscclk";
1107                 };
1108                 zb3_clk: zb3_clk {
1109                         compatible = "fixed-factor-clock";
1110                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1111                         #clock-cells = <0>;
1112                         clock-div = <4>;
1113                         clock-mult = <1>;
1114                         clock-output-names = "zb3";
1115                 };
1116                 zb3d2_clk: zb3d2_clk {
1117                         compatible = "fixed-factor-clock";
1118                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1119                         #clock-cells = <0>;
1120                         clock-div = <8>;
1121                         clock-mult = <1>;
1122                         clock-output-names = "zb3d2";
1123                 };
1124                 ddr_clk: ddr_clk {
1125                         compatible = "fixed-factor-clock";
1126                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1127                         #clock-cells = <0>;
1128                         clock-div = <8>;
1129                         clock-mult = <1>;
1130                         clock-output-names = "ddr";
1131                 };
1132                 mp_clk: mp_clk {
1133                         compatible = "fixed-factor-clock";
1134                         clocks = <&pll1_div2_clk>;
1135                         #clock-cells = <0>;
1136                         clock-div = <15>;
1137                         clock-mult = <1>;
1138                         clock-output-names = "mp";
1139                 };
1140                 cp_clk: cp_clk {
1141                         compatible = "fixed-factor-clock";
1142                         clocks = <&extal_clk>;
1143                         #clock-cells = <0>;
1144                         clock-div = <2>;
1145                         clock-mult = <1>;
1146                         clock-output-names = "cp";
1147                 };
1148
1149                 /* Gate clocks */
1150                 mstp0_clks: mstp0_clks@e6150130 {
1151                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1152                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1153                         clocks = <&mp_clk>;
1154                         #clock-cells = <1>;
1155                         clock-indices = <R8A7790_CLK_MSIOF0>;
1156                         clock-output-names = "msiof0";
1157                 };
1158                 mstp1_clks: mstp1_clks@e6150134 {
1159                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1160                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1161                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1162                                  <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1163                                  <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1164                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1165                         #clock-cells = <1>;
1166                         clock-indices = <
1167                                 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1168                                 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1169                                 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1170                                 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1171                                 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1172                                 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1173                                 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1174                         >;
1175                         clock-output-names =
1176                                 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1177                                 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1178                                 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1179                                 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1180                 };
1181                 mstp2_clks: mstp2_clks@e6150138 {
1182                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1183                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1184                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1185                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1186                                  <&zs_clk>;
1187                         #clock-cells = <1>;
1188                         clock-indices = <
1189                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1190                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1191                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1192                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1193                         >;
1194                         clock-output-names =
1195                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1196                                 "scifb1", "msiof1", "msiof3", "scifb2",
1197                                 "sys-dmac1", "sys-dmac0";
1198                 };
1199                 mstp3_clks: mstp3_clks@e615013c {
1200                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1201                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1202                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1203                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1204                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1205                                  <&hp_clk>, <&hp_clk>;
1206                         #clock-cells = <1>;
1207                         clock-indices = <
1208                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1209                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1210                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1211                                 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1212                         >;
1213                         clock-output-names =
1214                                 "iic2", "tpu0", "mmcif1", "sdhi3",
1215                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1216                                 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1217                                 "usbdmac0", "usbdmac1";
1218                 };
1219                 mstp4_clks: mstp4_clks@e6150140 {
1220                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1221                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1222                         clocks = <&cp_clk>;
1223                         #clock-cells = <1>;
1224                         clock-indices = <R8A7790_CLK_IRQC>;
1225                         clock-output-names = "irqc";
1226                 };
1227                 mstp5_clks: mstp5_clks@e6150144 {
1228                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1229                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1230                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1231                                  <&extal_clk>, <&p_clk>;
1232                         #clock-cells = <1>;
1233                         clock-indices = <
1234                                 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1235                                 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1236                                 R8A7790_CLK_PWM
1237                         >;
1238                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1239                                              "thermal", "pwm";
1240                 };
1241                 mstp7_clks: mstp7_clks@e615014c {
1242                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1243                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1244                         clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1245                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1246                                  <&zx_clk>;
1247                         #clock-cells = <1>;
1248                         clock-indices = <
1249                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1250                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1251                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1252                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1253                         >;
1254                         clock-output-names =
1255                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1256                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1257                 };
1258                 mstp8_clks: mstp8_clks@e6150990 {
1259                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1260                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1261                         clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1262                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1263                                  <&zs_clk>;
1264                         #clock-cells = <1>;
1265                         clock-indices = <
1266                                 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1267                                 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1268                                 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1269                                 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1270                         >;
1271                         clock-output-names =
1272                                 "mlb", "vin3", "vin2", "vin1", "vin0",
1273                                 "etheravb", "ether", "sata1", "sata0";
1274                 };
1275                 mstp9_clks: mstp9_clks@e6150994 {
1276                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1277                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1278                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1279                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
1280                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1281                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1282                         #clock-cells = <1>;
1283                         clock-indices = <
1284                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1285                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1286                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1287                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1288                         >;
1289                         clock-output-names =
1290                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1291                                 "rcan1", "rcan0", "qspi_mod", "iic3",
1292                                 "i2c3", "i2c2", "i2c1", "i2c0";
1293                 };
1294                 mstp10_clks: mstp10_clks@e6150998 {
1295                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1296                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1297                         clocks = <&p_clk>,
1298                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1299                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1300                                 <&p_clk>,
1301                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1302                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1303                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1304                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1305                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1306                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1307                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1308
1309                         #clock-cells = <1>;
1310                         clock-indices = <
1311                                 R8A7790_CLK_SSI_ALL
1312                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1313                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1314                                 R8A7790_CLK_SCU_ALL
1315                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1316                                 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1317                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1318                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1319                         >;
1320                         clock-output-names =
1321                                 "ssi-all",
1322                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1323                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1324                                 "scu-all",
1325                                 "scu-dvc1", "scu-dvc0",
1326                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1327                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1328                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1329                 };
1330         };
1331
1332         qspi: spi@e6b10000 {
1333                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1334                 reg = <0 0xe6b10000 0 0x2c>;
1335                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1336                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1337                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1338                 dma-names = "tx", "rx";
1339                 num-cs = <1>;
1340                 #address-cells = <1>;
1341                 #size-cells = <0>;
1342                 status = "disabled";
1343         };
1344
1345         msiof0: spi@e6e20000 {
1346                 compatible = "renesas,msiof-r8a7790";
1347                 reg = <0 0xe6e20000 0 0x0064>;
1348                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1349                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1350                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1351                 dma-names = "tx", "rx";
1352                 #address-cells = <1>;
1353                 #size-cells = <0>;
1354                 status = "disabled";
1355         };
1356
1357         msiof1: spi@e6e10000 {
1358                 compatible = "renesas,msiof-r8a7790";
1359                 reg = <0 0xe6e10000 0 0x0064>;
1360                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1361                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1362                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1363                 dma-names = "tx", "rx";
1364                 #address-cells = <1>;
1365                 #size-cells = <0>;
1366                 status = "disabled";
1367         };
1368
1369         msiof2: spi@e6e00000 {
1370                 compatible = "renesas,msiof-r8a7790";
1371                 reg = <0 0xe6e00000 0 0x0064>;
1372                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1373                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1374                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1375                 dma-names = "tx", "rx";
1376                 #address-cells = <1>;
1377                 #size-cells = <0>;
1378                 status = "disabled";
1379         };
1380
1381         msiof3: spi@e6c90000 {
1382                 compatible = "renesas,msiof-r8a7790";
1383                 reg = <0 0xe6c90000 0 0x0064>;
1384                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1385                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1386                 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1387                 dma-names = "tx", "rx";
1388                 #address-cells = <1>;
1389                 #size-cells = <0>;
1390                 status = "disabled";
1391         };
1392
1393         xhci: usb@ee000000 {
1394                 compatible = "renesas,xhci-r8a7790";
1395                 reg = <0 0xee000000 0 0xc00>;
1396                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1397                 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1398                 phys = <&usb2 1>;
1399                 phy-names = "usb";
1400                 status = "disabled";
1401         };
1402
1403         pci0: pci@ee090000 {
1404                 compatible = "renesas,pci-r8a7790";
1405                 device_type = "pci";
1406                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1407                 reg = <0 0xee090000 0 0xc00>,
1408                       <0 0xee080000 0 0x1100>;
1409                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1410                 status = "disabled";
1411
1412                 bus-range = <0 0>;
1413                 #address-cells = <3>;
1414                 #size-cells = <2>;
1415                 #interrupt-cells = <1>;
1416                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1417                 interrupt-map-mask = <0xff00 0 0 0x7>;
1418                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1419                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1420                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1421
1422                 usb@0,1 {
1423                         reg = <0x800 0 0 0 0>;
1424                         device_type = "pci";
1425                         phys = <&usb0 0>;
1426                         phy-names = "usb";
1427                 };
1428
1429                 usb@0,2 {
1430                         reg = <0x1000 0 0 0 0>;
1431                         device_type = "pci";
1432                         phys = <&usb0 0>;
1433                         phy-names = "usb";
1434                 };
1435         };
1436
1437         pci1: pci@ee0b0000 {
1438                 compatible = "renesas,pci-r8a7790";
1439                 device_type = "pci";
1440                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1441                 reg = <0 0xee0b0000 0 0xc00>,
1442                       <0 0xee0a0000 0 0x1100>;
1443                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1444                 status = "disabled";
1445
1446                 bus-range = <1 1>;
1447                 #address-cells = <3>;
1448                 #size-cells = <2>;
1449                 #interrupt-cells = <1>;
1450                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1451                 interrupt-map-mask = <0xff00 0 0 0x7>;
1452                 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1453                                  0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1454                                  0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1455         };
1456
1457         pci2: pci@ee0d0000 {
1458                 compatible = "renesas,pci-r8a7790";
1459                 device_type = "pci";
1460                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1461                 reg = <0 0xee0d0000 0 0xc00>,
1462                       <0 0xee0c0000 0 0x1100>;
1463                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1464                 status = "disabled";
1465
1466                 bus-range = <2 2>;
1467                 #address-cells = <3>;
1468                 #size-cells = <2>;
1469                 #interrupt-cells = <1>;
1470                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1471                 interrupt-map-mask = <0xff00 0 0 0x7>;
1472                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1473                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1474                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1475
1476                 usb@0,1 {
1477                         reg = <0x800 0 0 0 0>;
1478                         device_type = "pci";
1479                         phys = <&usb2 0>;
1480                         phy-names = "usb";
1481                 };
1482
1483                 usb@0,2 {
1484                         reg = <0x1000 0 0 0 0>;
1485                         device_type = "pci";
1486                         phys = <&usb2 0>;
1487                         phy-names = "usb";
1488                 };
1489         };
1490
1491         pciec: pcie@fe000000 {
1492                 compatible = "renesas,pcie-r8a7790";
1493                 reg = <0 0xfe000000 0 0x80000>;
1494                 #address-cells = <3>;
1495                 #size-cells = <2>;
1496                 bus-range = <0x00 0xff>;
1497                 device_type = "pci";
1498                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1499                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1500                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1501                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1502                 /* Map all possible DDR as inbound ranges */
1503                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1504                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1505                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1506                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1507                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1508                 #interrupt-cells = <1>;
1509                 interrupt-map-mask = <0 0 0 0>;
1510                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1511                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1512                 clock-names = "pcie", "pcie_bus";
1513                 status = "disabled";
1514         };
1515
1516         rcar_sound: sound@ec500000 {
1517                 /*
1518                  * #sound-dai-cells is required
1519                  *
1520                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1521                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1522                  */
1523                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1524                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1525                         <0 0xec5a0000 0 0x100>,  /* ADG */
1526                         <0 0xec540000 0 0x1000>, /* SSIU */
1527                         <0 0xec541000 0 0x1280>, /* SSI */
1528                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1529                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1530
1531                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1532                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1533                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1534                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1535                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1536                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1537                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1538                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1539                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1540                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1541                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1542                         <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1543                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1544                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1545                 clock-names = "ssi-all",
1546                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1547                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1548                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1549                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1550                                 "ctu.0", "ctu.1",
1551                                 "dvc.0", "dvc.1",
1552                                 "clk_a", "clk_b", "clk_c", "clk_i";
1553
1554                 status = "disabled";
1555
1556                 rcar_sound,dvc {
1557                         dvc0: dvc@0 {
1558                                 dmas = <&audma0 0xbc>;
1559                                 dma-names = "tx";
1560                         };
1561                         dvc1: dvc@1 {
1562                                 dmas = <&audma0 0xbe>;
1563                                 dma-names = "tx";
1564                         };
1565                 };
1566
1567                 rcar_sound,ctu {
1568                         ctu00: ctu@0 { };
1569                         ctu01: ctu@1 { };
1570                         ctu02: ctu@2 { };
1571                         ctu03: ctu@3 { };
1572                         ctu10: ctu@4 { };
1573                         ctu11: ctu@5 { };
1574                         ctu12: ctu@6 { };
1575                         ctu13: ctu@7 { };
1576                 };
1577
1578                 rcar_sound,src {
1579                         src0: src@0 {
1580                                 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1581                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1582                                 dma-names = "rx", "tx";
1583                         };
1584                         src1: src@1 {
1585                                 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1586                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1587                                 dma-names = "rx", "tx";
1588                         };
1589                         src2: src@2 {
1590                                 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1591                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1592                                 dma-names = "rx", "tx";
1593                         };
1594                         src3: src@3 {
1595                                 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1596                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1597                                 dma-names = "rx", "tx";
1598                         };
1599                         src4: src@4 {
1600                                 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1601                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1602                                 dma-names = "rx", "tx";
1603                         };
1604                         src5: src@5 {
1605                                 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1606                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1607                                 dma-names = "rx", "tx";
1608                         };
1609                         src6: src@6 {
1610                                 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1611                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1612                                 dma-names = "rx", "tx";
1613                         };
1614                         src7: src@7 {
1615                                 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1616                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1617                                 dma-names = "rx", "tx";
1618                         };
1619                         src8: src@8 {
1620                                 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1621                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1622                                 dma-names = "rx", "tx";
1623                         };
1624                         src9: src@9 {
1625                                 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1626                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1627                                 dma-names = "rx", "tx";
1628                         };
1629                 };
1630
1631                 rcar_sound,ssi {
1632                         ssi0: ssi@0 {
1633                                 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1634                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1635                                 dma-names = "rx", "tx", "rxu", "txu";
1636                         };
1637                         ssi1: ssi@1 {
1638                                  interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1639                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1640                                 dma-names = "rx", "tx", "rxu", "txu";
1641                         };
1642                         ssi2: ssi@2 {
1643                                 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1644                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1645                                 dma-names = "rx", "tx", "rxu", "txu";
1646                         };
1647                         ssi3: ssi@3 {
1648                                 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1649                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1650                                 dma-names = "rx", "tx", "rxu", "txu";
1651                         };
1652                         ssi4: ssi@4 {
1653                                 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1654                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1655                                 dma-names = "rx", "tx", "rxu", "txu";
1656                         };
1657                         ssi5: ssi@5 {
1658                                 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1659                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1660                                 dma-names = "rx", "tx", "rxu", "txu";
1661                         };
1662                         ssi6: ssi@6 {
1663                                 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1664                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1665                                 dma-names = "rx", "tx", "rxu", "txu";
1666                         };
1667                         ssi7: ssi@7 {
1668                                 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1669                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1670                                 dma-names = "rx", "tx", "rxu", "txu";
1671                         };
1672                         ssi8: ssi@8 {
1673                                 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1674                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1675                                 dma-names = "rx", "tx", "rxu", "txu";
1676                         };
1677                         ssi9: ssi@9 {
1678                                 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1679                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1680                                 dma-names = "rx", "tx", "rxu", "txu";
1681                         };
1682                 };
1683         };
1684
1685         ipmmu_sy0: mmu@e6280000 {
1686                 compatible = "renesas,ipmmu-vmsa";
1687                 reg = <0 0xe6280000 0 0x1000>;
1688                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1689                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
1690                 #iommu-cells = <1>;
1691                 status = "disabled";
1692         };
1693
1694         ipmmu_sy1: mmu@e6290000 {
1695                 compatible = "renesas,ipmmu-vmsa";
1696                 reg = <0 0xe6290000 0 0x1000>;
1697                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1698                 #iommu-cells = <1>;
1699                 status = "disabled";
1700         };
1701
1702         ipmmu_ds: mmu@e6740000 {
1703                 compatible = "renesas,ipmmu-vmsa";
1704                 reg = <0 0xe6740000 0 0x1000>;
1705                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1706                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
1707                 #iommu-cells = <1>;
1708                 status = "disabled";
1709         };
1710
1711         ipmmu_mp: mmu@ec680000 {
1712                 compatible = "renesas,ipmmu-vmsa";
1713                 reg = <0 0xec680000 0 0x1000>;
1714                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1715                 #iommu-cells = <1>;
1716                 status = "disabled";
1717         };
1718
1719         ipmmu_mx: mmu@fe951000 {
1720                 compatible = "renesas,ipmmu-vmsa";
1721                 reg = <0 0xfe951000 0 0x1000>;
1722                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1723                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
1724                 #iommu-cells = <1>;
1725                 status = "disabled";
1726         };
1727
1728         ipmmu_rt: mmu@ffc80000 {
1729                 compatible = "renesas,ipmmu-vmsa";
1730                 reg = <0 0xffc80000 0 0x1000>;
1731                 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1732                 #iommu-cells = <1>;
1733                 status = "disabled";
1734         };
1735 };