arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7790-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/power/r8a7790-sysc.h>
  17
  18 / {
  19         compatible = "renesas,r8a7790";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 i2c4 = &iic0;
  30                 i2c5 = &iic1;
  31                 i2c6 = &iic2;
  32                 i2c7 = &iic3;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37                 spi4 = &msiof3;
  38                 vin0 = &vin0;
  39                 vin1 = &vin1;
  40                 vin2 = &vin2;
  41                 vin3 = &vin3;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a15";
  51                         reg = <0>;
  52                         clock-frequency = <1300000000>;
  53                         voltage-tolerance = <1>; /* 1% */
  54                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  55                         clock-latency = <300000>; /* 300 us */
  56                         power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
  57                         next-level-cache = <&L2_CA15>;
  58
  59                         /* kHz - uV - OPPs unknown yet */
  60                         operating-points = <1400000 1000000>,
  61                                            <1225000 1000000>,
  62                                            <1050000 1000000>,
  63                                            < 875000 1000000>,
  64                                            < 700000 1000000>,
  65                                            < 350000 1000000>;
  66                 };
  67
  68                 cpu1: cpu@1 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a15";
  71                         reg = <1>;
  72                         clock-frequency = <1300000000>;
  73                         power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
  74                         next-level-cache = <&L2_CA15>;
  75                 };
  76
  77                 cpu2: cpu@2 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a15";
  80                         reg = <2>;
  81                         clock-frequency = <1300000000>;
  82                         power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
  83                         next-level-cache = <&L2_CA15>;
  84                 };
  85
  86                 cpu3: cpu@3 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a15";
  89                         reg = <3>;
  90                         clock-frequency = <1300000000>;
  91                         power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
  92                         next-level-cache = <&L2_CA15>;
  93                 };
  94
  95                 cpu4: cpu@100 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a7";
  98                         reg = <0x100>;
  99                         clock-frequency = <780000000>;
 100                         power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
 101                         next-level-cache = <&L2_CA7>;
 102                 };
 103
 104                 cpu5: cpu@101 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a7";
 107                         reg = <0x101>;
 108                         clock-frequency = <780000000>;
 109                         power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
 110                         next-level-cache = <&L2_CA7>;
 111                 };
 112
 113                 cpu6: cpu@102 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a7";
 116                         reg = <0x102>;
 117                         clock-frequency = <780000000>;
 118                         power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
 119                         next-level-cache = <&L2_CA7>;
 120                 };
 121
 122                 cpu7: cpu@103 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a7";
 125                         reg = <0x103>;
 126                         clock-frequency = <780000000>;
 127                         power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
 128                         next-level-cache = <&L2_CA7>;
 129                 };
 130         };
 131
 132         thermal-zones {
 133                 cpu_thermal: cpu-thermal {
 134                         polling-delay-passive   = <0>;
 135                         polling-delay           = <0>;
 136
 137                         thermal-sensors = <&thermal>;
 138
 139                         trips {
 140                                 cpu-crit {
 141                                         temperature     = <115000>;
 142                                         hysteresis      = <0>;
 143                                         type            = "critical";
 144                                 };
 145                         };
 146                         cooling-maps {
 147                         };
 148                 };
 149         };
 150
 151         L2_CA15: cache-controller@0 {
 152                 compatible = "cache";
 153                 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
 154                 cache-unified;
 155                 cache-level = <2>;
 156         };
 157
 158         L2_CA7: cache-controller@1 {
 159                 compatible = "cache";
 160                 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
 161                 cache-unified;
 162                 cache-level = <2>;
 163         };
 164
 165         gic: interrupt-controller@f1001000 {
 166                 compatible = "arm,gic-400";
 167                 #interrupt-cells = <3>;
 168                 #address-cells = <0>;
 169                 interrupt-controller;
 170                 reg = <0 0xf1001000 0 0x1000>,
 171                         <0 0xf1002000 0 0x1000>,
 172                         <0 0xf1004000 0 0x2000>,
 173                         <0 0xf1006000 0 0x2000>;
 174                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 175         };
 176
 177         gpio0: gpio@e6050000 {
 178                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 179                 reg = <0 0xe6050000 0 0x50>;
 180                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 181                 #gpio-cells = <2>;
 182                 gpio-controller;
 183                 gpio-ranges = <&pfc 0 0 32>;
 184                 #interrupt-cells = <2>;
 185                 interrupt-controller;
 186                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 187                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 188         };
 189
 190         gpio1: gpio@e6051000 {
 191                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 192                 reg = <0 0xe6051000 0 0x50>;
 193                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 194                 #gpio-cells = <2>;
 195                 gpio-controller;
 196                 gpio-ranges = <&pfc 0 32 30>;
 197                 #interrupt-cells = <2>;
 198                 interrupt-controller;
 199                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 200                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 201         };
 202
 203         gpio2: gpio@e6052000 {
 204                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 205                 reg = <0 0xe6052000 0 0x50>;
 206                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 207                 #gpio-cells = <2>;
 208                 gpio-controller;
 209                 gpio-ranges = <&pfc 0 64 30>;
 210                 #interrupt-cells = <2>;
 211                 interrupt-controller;
 212                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 213                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 214         };
 215
 216         gpio3: gpio@e6053000 {
 217                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 218                 reg = <0 0xe6053000 0 0x50>;
 219                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 220                 #gpio-cells = <2>;
 221                 gpio-controller;
 222                 gpio-ranges = <&pfc 0 96 32>;
 223                 #interrupt-cells = <2>;
 224                 interrupt-controller;
 225                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 226                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 227         };
 228
 229         gpio4: gpio@e6054000 {
 230                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 231                 reg = <0 0xe6054000 0 0x50>;
 232                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 233                 #gpio-cells = <2>;
 234                 gpio-controller;
 235                 gpio-ranges = <&pfc 0 128 32>;
 236                 #interrupt-cells = <2>;
 237                 interrupt-controller;
 238                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 239                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 240         };
 241
 242         gpio5: gpio@e6055000 {
 243                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 244                 reg = <0 0xe6055000 0 0x50>;
 245                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 246                 #gpio-cells = <2>;
 247                 gpio-controller;
 248                 gpio-ranges = <&pfc 0 160 32>;
 249                 #interrupt-cells = <2>;
 250                 interrupt-controller;
 251                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 252                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 253         };
 254
 255         thermal: thermal@e61f0000 {
 256                 compatible =    "renesas,thermal-r8a7790",
 257                                 "renesas,rcar-gen2-thermal",
 258                                 "renesas,rcar-thermal";
 259                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 260                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 262                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 263                 #thermal-sensor-cells = <0>;
 264         };
 265
 266         timer {
 267                 compatible = "arm,armv7-timer";
 268                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 269                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 270                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 271                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 272         };
 273
 274         cmt0: timer@ffca0000 {
 275                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 276                 reg = <0 0xffca0000 0 0x1004>;
 277                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 280                 clock-names = "fck";
 281                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 282
 283                 renesas,channels-mask = <0x60>;
 284
 285                 status = "disabled";
 286         };
 287
 288         cmt1: timer@e6130000 {
 289                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 290                 reg = <0 0xe6130000 0 0x1004>;
 291                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 300                 clock-names = "fck";
 301                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 302
 303                 renesas,channels-mask = <0xff>;
 304
 305                 status = "disabled";
 306         };
 307
 308         irqc0: interrupt-controller@e61c0000 {
 309                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 310                 #interrupt-cells = <2>;
 311                 interrupt-controller;
 312                 reg = <0 0xe61c0000 0 0x200>;
 313                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
 318                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 319         };
 320
 321         dmac0: dma-controller@e6700000 {
 322                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 323                 reg = <0 0xe6700000 0 0x20000>;
 324                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 325                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 326                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 327                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 328                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 329                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 330                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 331                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 332                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 333                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 334                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 335                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 336                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 340                 interrupt-names = "error",
 341                                 "ch0", "ch1", "ch2", "ch3",
 342                                 "ch4", "ch5", "ch6", "ch7",
 343                                 "ch8", "ch9", "ch10", "ch11",
 344                                 "ch12", "ch13", "ch14";
 345                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 346                 clock-names = "fck";
 347                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 348                 #dma-cells = <1>;
 349                 dma-channels = <15>;
 350         };
 351
 352         dmac1: dma-controller@e6720000 {
 353                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 354                 reg = <0 0xe6720000 0 0x20000>;
 355                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 356                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 357                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 358                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 359                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 360                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 361                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 362                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 363                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 364                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 365                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 366                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 367                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 368                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 369                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 370                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 371                 interrupt-names = "error",
 372                                 "ch0", "ch1", "ch2", "ch3",
 373                                 "ch4", "ch5", "ch6", "ch7",
 374                                 "ch8", "ch9", "ch10", "ch11",
 375                                 "ch12", "ch13", "ch14";
 376                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 377                 clock-names = "fck";
 378                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 379                 #dma-cells = <1>;
 380                 dma-channels = <15>;
 381         };
 382
 383         audma0: dma-controller@ec700000 {
 384                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 385                 reg = <0 0xec700000 0 0x10000>;
 386                 interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 387                                  GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 388                                  GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 389                                  GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 390                                  GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 391                                  GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 392                                  GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 393                                  GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 394                                  GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 395                                  GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 396                                  GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 397                                  GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 398                                  GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 399                                  GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 400                 interrupt-names = "error",
 401                                 "ch0", "ch1", "ch2", "ch3",
 402                                 "ch4", "ch5", "ch6", "ch7",
 403                                 "ch8", "ch9", "ch10", "ch11",
 404                                 "ch12";
 405                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
 406                 clock-names = "fck";
 407                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 408                 #dma-cells = <1>;
 409                 dma-channels = <13>;
 410         };
 411
 412         audma1: dma-controller@ec720000 {
 413                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 414                 reg = <0 0xec720000 0 0x10000>;
 415                 interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 416                                  GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 417                                  GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 418                                  GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 419                                  GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 420                                  GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 421                                  GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 422                                  GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 423                                  GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 424                                  GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 425                                  GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 426                                  GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 427                                  GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 428                                  GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 429                 interrupt-names = "error",
 430                                 "ch0", "ch1", "ch2", "ch3",
 431                                 "ch4", "ch5", "ch6", "ch7",
 432                                 "ch8", "ch9", "ch10", "ch11",
 433                                 "ch12";
 434                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
 435                 clock-names = "fck";
 436                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 437                 #dma-cells = <1>;
 438                 dma-channels = <13>;
 439         };
 440
 441         usb_dmac0: dma-controller@e65a0000 {
 442                 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
 443                 reg = <0 0xe65a0000 0 0x100>;
 444                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
 445                               GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 446                 interrupt-names = "ch0", "ch1";
 447                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
 448                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 449                 #dma-cells = <1>;
 450                 dma-channels = <2>;
 451         };
 452
 453         usb_dmac1: dma-controller@e65b0000 {
 454                 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
 455                 reg = <0 0xe65b0000 0 0x100>;
 456                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
 457                               GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 458                 interrupt-names = "ch0", "ch1";
 459                 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
 460                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 461                 #dma-cells = <1>;
 462                 dma-channels = <2>;
 463         };
 464
 465         i2c0: i2c@e6508000 {
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 compatible = "renesas,i2c-r8a7790";
 469                 reg = <0 0xe6508000 0 0x40>;
 470                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 471                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 472                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 473                 i2c-scl-internal-delay-ns = <110>;
 474                 status = "disabled";
 475         };
 476
 477         i2c1: i2c@e6518000 {
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 compatible = "renesas,i2c-r8a7790";
 481                 reg = <0 0xe6518000 0 0x40>;
 482                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 483                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 484                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 485                 i2c-scl-internal-delay-ns = <6>;
 486                 status = "disabled";
 487         };
 488
 489         i2c2: i2c@e6530000 {
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 compatible = "renesas,i2c-r8a7790";
 493                 reg = <0 0xe6530000 0 0x40>;
 494                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 495                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 496                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 497                 i2c-scl-internal-delay-ns = <6>;
 498                 status = "disabled";
 499         };
 500
 501         i2c3: i2c@e6540000 {
 502                 #address-cells = <1>;
 503                 #size-cells = <0>;
 504                 compatible = "renesas,i2c-r8a7790";
 505                 reg = <0 0xe6540000 0 0x40>;
 506                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 508                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 509                 i2c-scl-internal-delay-ns = <110>;
 510                 status = "disabled";
 511         };
 512
 513         iic0: i2c@e6500000 {
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 517                 reg = <0 0xe6500000 0 0x425>;
 518                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 519                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 520                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 521                        <&dmac1 0x61>, <&dmac1 0x62>;
 522                 dma-names = "tx", "rx", "tx", "rx";
 523                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 524                 status = "disabled";
 525         };
 526
 527         iic1: i2c@e6510000 {
 528                 #address-cells = <1>;
 529                 #size-cells = <0>;
 530                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 531                 reg = <0 0xe6510000 0 0x425>;
 532                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 534                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 535                        <&dmac1 0x65>, <&dmac1 0x66>;
 536                 dma-names = "tx", "rx", "tx", "rx";
 537                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 538                 status = "disabled";
 539         };
 540
 541         iic2: i2c@e6520000 {
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 545                 reg = <0 0xe6520000 0 0x425>;
 546                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 548                 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
 549                        <&dmac1 0x69>, <&dmac1 0x6a>;
 550                 dma-names = "tx", "rx", "tx", "rx";
 551                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 552                 status = "disabled";
 553         };
 554
 555         iic3: i2c@e60b0000 {
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 559                 reg = <0 0xe60b0000 0 0x425>;
 560                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 561                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 562                 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 563                        <&dmac1 0x77>, <&dmac1 0x78>;
 564                 dma-names = "tx", "rx", "tx", "rx";
 565                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 566                 status = "disabled";
 567         };
 568
 569         mmcif0: mmc@ee200000 {
 570                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 571                 reg = <0 0xee200000 0 0x80>;
 572                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 573                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 574                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 575                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 576                 dma-names = "tx", "rx", "tx", "rx";
 577                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 578                 reg-io-width = <4>;
 579                 status = "disabled";
 580                 max-frequency = <97500000>;
 581         };
 582
 583         mmcif1: mmc@ee220000 {
 584                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 585                 reg = <0 0xee220000 0 0x80>;
 586                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 587                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 588                 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
 589                        <&dmac1 0xe1>, <&dmac1 0xe2>;
 590                 dma-names = "tx", "rx", "tx", "rx";
 591                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 592                 reg-io-width = <4>;
 593                 status = "disabled";
 594                 max-frequency = <97500000>;
 595         };
 596
 597         pfc: pfc@e6060000 {
 598                 compatible = "renesas,pfc-r8a7790";
 599                 reg = <0 0xe6060000 0 0x250>;
 600         };
 601
 602         sdhi0: sd@ee100000 {
 603                 compatible = "renesas,sdhi-r8a7790";
 604                 reg = <0 0xee100000 0 0x328>;
 605                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 607                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 608                        <&dmac1 0xcd>, <&dmac1 0xce>;
 609                 dma-names = "tx", "rx", "tx", "rx";
 610                 max-frequency = <195000000>;
 611                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 612                 status = "disabled";
 613         };
 614
 615         sdhi1: sd@ee120000 {
 616                 compatible = "renesas,sdhi-r8a7790";
 617                 reg = <0 0xee120000 0 0x328>;
 618                 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 619                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 620                 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
 621                        <&dmac1 0xc9>, <&dmac1 0xca>;
 622                 dma-names = "tx", "rx", "tx", "rx";
 623                 max-frequency = <195000000>;
 624                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 625                 status = "disabled";
 626         };
 627
 628         sdhi2: sd@ee140000 {
 629                 compatible = "renesas,sdhi-r8a7790";
 630                 reg = <0 0xee140000 0 0x100>;
 631                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 632                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 633                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 634                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 635                 dma-names = "tx", "rx", "tx", "rx";
 636                 max-frequency = <97500000>;
 637                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 638                 status = "disabled";
 639         };
 640
 641         sdhi3: sd@ee160000 {
 642                 compatible = "renesas,sdhi-r8a7790";
 643                 reg = <0 0xee160000 0 0x100>;
 644                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 646                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 647                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 648                 dma-names = "tx", "rx", "tx", "rx";
 649                 max-frequency = <97500000>;
 650                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 651                 status = "disabled";
 652         };
 653
 654         scifa0: serial@e6c40000 {
 655                 compatible = "renesas,scifa-r8a7790",
 656                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 657                 reg = <0 0xe6c40000 0 64>;
 658                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 659                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 660                 clock-names = "fck";
 661                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 662                        <&dmac1 0x21>, <&dmac1 0x22>;
 663                 dma-names = "tx", "rx", "tx", "rx";
 664                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 665                 status = "disabled";
 666         };
 667
 668         scifa1: serial@e6c50000 {
 669                 compatible = "renesas,scifa-r8a7790",
 670                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 671                 reg = <0 0xe6c50000 0 64>;
 672                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 673                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 674                 clock-names = "fck";
 675                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 676                        <&dmac1 0x25>, <&dmac1 0x26>;
 677                 dma-names = "tx", "rx", "tx", "rx";
 678                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 679                 status = "disabled";
 680         };
 681
 682         scifa2: serial@e6c60000 {
 683                 compatible = "renesas,scifa-r8a7790",
 684                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 685                 reg = <0 0xe6c60000 0 64>;
 686                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 687                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 688                 clock-names = "fck";
 689                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 690                        <&dmac1 0x27>, <&dmac1 0x28>;
 691                 dma-names = "tx", "rx", "tx", "rx";
 692                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 693                 status = "disabled";
 694         };
 695
 696         scifb0: serial@e6c20000 {
 697                 compatible = "renesas,scifb-r8a7790",
 698                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 699                 reg = <0 0xe6c20000 0 64>;
 700                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 701                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 702                 clock-names = "fck";
 703                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 704                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 705                 dma-names = "tx", "rx", "tx", "rx";
 706                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 707                 status = "disabled";
 708         };
 709
 710         scifb1: serial@e6c30000 {
 711                 compatible = "renesas,scifb-r8a7790",
 712                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 713                 reg = <0 0xe6c30000 0 64>;
 714                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 715                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 716                 clock-names = "fck";
 717                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 718                        <&dmac1 0x19>, <&dmac1 0x1a>;
 719                 dma-names = "tx", "rx", "tx", "rx";
 720                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 721                 status = "disabled";
 722         };
 723
 724         scifb2: serial@e6ce0000 {
 725                 compatible = "renesas,scifb-r8a7790",
 726                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 727                 reg = <0 0xe6ce0000 0 64>;
 728                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 730                 clock-names = "fck";
 731                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 732                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 733                 dma-names = "tx", "rx", "tx", "rx";
 734                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 735                 status = "disabled";
 736         };
 737
 738         scif0: serial@e6e60000 {
 739                 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
 740                              "renesas,scif";
 741                 reg = <0 0xe6e60000 0 64>;
 742                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 743                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
 744                          <&scif_clk>;
 745                 clock-names = "fck", "brg_int", "scif_clk";
 746                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 747                        <&dmac1 0x29>, <&dmac1 0x2a>;
 748                 dma-names = "tx", "rx", "tx", "rx";
 749                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 750                 status = "disabled";
 751         };
 752
 753         scif1: serial@e6e68000 {
 754                 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
 755                              "renesas,scif";
 756                 reg = <0 0xe6e68000 0 64>;
 757                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 758                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
 759                          <&scif_clk>;
 760                 clock-names = "fck", "brg_int", "scif_clk";
 761                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 762                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 763                 dma-names = "tx", "rx", "tx", "rx";
 764                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 765                 status = "disabled";
 766         };
 767
 768         scif2: serial@e6e56000 {
 769                 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
 770                              "renesas,scif";
 771                 reg = <0 0xe6e56000 0 64>;
 772                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 773                 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
 774                          <&scif_clk>;
 775                 clock-names = "fck", "brg_int", "scif_clk";
 776                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 777                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 778                 dma-names = "tx", "rx", "tx", "rx";
 779                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 780                 status = "disabled";
 781         };
 782
 783         hscif0: serial@e62c0000 {
 784                 compatible = "renesas,hscif-r8a7790",
 785                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 786                 reg = <0 0xe62c0000 0 96>;
 787                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 788                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
 789                          <&scif_clk>;
 790                 clock-names = "fck", "brg_int", "scif_clk";
 791                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 792                        <&dmac1 0x39>, <&dmac1 0x3a>;
 793                 dma-names = "tx", "rx", "tx", "rx";
 794                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 795                 status = "disabled";
 796         };
 797
 798         hscif1: serial@e62c8000 {
 799                 compatible = "renesas,hscif-r8a7790",
 800                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 801                 reg = <0 0xe62c8000 0 96>;
 802                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 803                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
 804                          <&scif_clk>;
 805                 clock-names = "fck", "brg_int", "scif_clk";
 806                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 807                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 808                 dma-names = "tx", "rx", "tx", "rx";
 809                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 810                 status = "disabled";
 811         };
 812
 813         ether: ethernet@ee700000 {
 814                 compatible = "renesas,ether-r8a7790";
 815                 reg = <0 0xee700000 0 0x400>;
 816                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 817                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 818                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 819                 phy-mode = "rmii";
 820                 #address-cells = <1>;
 821                 #size-cells = <0>;
 822                 status = "disabled";
 823         };
 824
 825         avb: ethernet@e6800000 {
 826                 compatible = "renesas,etheravb-r8a7790",
 827                              "renesas,etheravb-rcar-gen2";
 828                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 829                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 830                 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
 831                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 832                 #address-cells = <1>;
 833                 #size-cells = <0>;
 834                 status = "disabled";
 835         };
 836
 837         sata0: sata@ee300000 {
 838                 compatible = "renesas,sata-r8a7790";
 839                 reg = <0 0xee300000 0 0x2000>;
 840                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 841                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 842                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 843                 status = "disabled";
 844         };
 845
 846         sata1: sata@ee500000 {
 847                 compatible = "renesas,sata-r8a7790";
 848                 reg = <0 0xee500000 0 0x2000>;
 849                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 850                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 851                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 852                 status = "disabled";
 853         };
 854
 855         hsusb: usb@e6590000 {
 856                 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
 857                 reg = <0 0xe6590000 0 0x100>;
 858                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 859                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 860                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 861                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 862                 dma-names = "ch0", "ch1", "ch2", "ch3";
 863                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 864                 renesas,buswait = <4>;
 865                 phys = <&usb0 1>;
 866                 phy-names = "usb";
 867                 status = "disabled";
 868         };
 869
 870         usbphy: usb-phy@e6590100 {
 871                 compatible = "renesas,usb-phy-r8a7790";
 872                 reg = <0 0xe6590100 0 0x100>;
 873                 #address-cells = <1>;
 874                 #size-cells = <0>;
 875                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 876                 clock-names = "usbhs";
 877                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 878                 status = "disabled";
 879
 880                 usb0: usb-channel@0 {
 881                         reg = <0>;
 882                         #phy-cells = <1>;
 883                 };
 884                 usb2: usb-channel@2 {
 885                         reg = <2>;
 886                         #phy-cells = <1>;
 887                 };
 888         };
 889
 890         vin0: video@e6ef0000 {
 891                 compatible = "renesas,vin-r8a7790";
 892                 reg = <0 0xe6ef0000 0 0x1000>;
 893                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 894                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 895                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 896                 status = "disabled";
 897         };
 898
 899         vin1: video@e6ef1000 {
 900                 compatible = "renesas,vin-r8a7790";
 901                 reg = <0 0xe6ef1000 0 0x1000>;
 902                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 903                 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 904                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 905                 status = "disabled";
 906         };
 907
 908         vin2: video@e6ef2000 {
 909                 compatible = "renesas,vin-r8a7790";
 910                 reg = <0 0xe6ef2000 0 0x1000>;
 911                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 912                 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 913                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 914                 status = "disabled";
 915         };
 916
 917         vin3: video@e6ef3000 {
 918                 compatible = "renesas,vin-r8a7790";
 919                 reg = <0 0xe6ef3000 0 0x1000>;
 920                 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 921                 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 922                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 923                 status = "disabled";
 924         };
 925
 926         vsp1@fe920000 {
 927                 compatible = "renesas,vsp1";
 928                 reg = <0 0xfe920000 0 0x8000>;
 929                 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 930                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
 931                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 932
 933                 renesas,has-sru;
 934                 renesas,#rpf = <5>;
 935                 renesas,#uds = <1>;
 936                 renesas,#wpf = <4>;
 937         };
 938
 939         vsp1@fe928000 {
 940                 compatible = "renesas,vsp1";
 941                 reg = <0 0xfe928000 0 0x8000>;
 942                 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 943                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
 944                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 945
 946                 renesas,has-lut;
 947                 renesas,has-sru;
 948                 renesas,#rpf = <5>;
 949                 renesas,#uds = <3>;
 950                 renesas,#wpf = <4>;
 951         };
 952
 953         vsp1@fe930000 {
 954                 compatible = "renesas,vsp1";
 955                 reg = <0 0xfe930000 0 0x8000>;
 956                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 957                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
 958                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 959
 960                 renesas,has-lif;
 961                 renesas,has-lut;
 962                 renesas,#rpf = <4>;
 963                 renesas,#uds = <1>;
 964                 renesas,#wpf = <4>;
 965         };
 966
 967         vsp1@fe938000 {
 968                 compatible = "renesas,vsp1";
 969                 reg = <0 0xfe938000 0 0x8000>;
 970                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 971                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
 972                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 973
 974                 renesas,has-lif;
 975                 renesas,has-lut;
 976                 renesas,#rpf = <4>;
 977                 renesas,#uds = <1>;
 978                 renesas,#wpf = <4>;
 979         };
 980
 981         du: display@feb00000 {
 982                 compatible = "renesas,du-r8a7790";
 983                 reg = <0 0xfeb00000 0 0x70000>,
 984                       <0 0xfeb90000 0 0x1c>,
 985                       <0 0xfeb94000 0 0x1c>;
 986                 reg-names = "du", "lvds.0", "lvds.1";
 987                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 988                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
 989                              <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
 990                 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
 991                          <&mstp7_clks R8A7790_CLK_DU1>,
 992                          <&mstp7_clks R8A7790_CLK_DU2>,
 993                          <&mstp7_clks R8A7790_CLK_LVDS0>,
 994                          <&mstp7_clks R8A7790_CLK_LVDS1>;
 995                 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
 996                 status = "disabled";
 997
 998                 ports {
 999                         #address-cells = <1>;
1000                         #size-cells = <0>;
1001
1002                         port@0 {
1003                                 reg = <0>;
1004                                 du_out_rgb: endpoint {
1005                                 };
1006                         };
1007                         port@1 {
1008                                 reg = <1>;
1009                                 du_out_lvds0: endpoint {
1010                                 };
1011                         };
1012                         port@2 {
1013                                 reg = <2>;
1014                                 du_out_lvds1: endpoint {
1015                                 };
1016                         };
1017                 };
1018         };
1019
1020         can0: can@e6e80000 {
1021                 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1022                 reg = <0 0xe6e80000 0 0x1000>;
1023                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1024                 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
1025                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1026                 clock-names = "clkp1", "clkp2", "can_clk";
1027                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1028                 status = "disabled";
1029         };
1030
1031         can1: can@e6e88000 {
1032                 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1033                 reg = <0 0xe6e88000 0 0x1000>;
1034                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1035                 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1036                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1037                 clock-names = "clkp1", "clkp2", "can_clk";
1038                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1039                 status = "disabled";
1040         };
1041
1042         jpu: jpeg-codec@fe980000 {
1043                 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
1044                 reg = <0 0xfe980000 0 0x10300>;
1045                 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1046                 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
1047                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1048         };
1049
1050         clocks {
1051                 #address-cells = <2>;
1052                 #size-cells = <2>;
1053                 ranges;
1054
1055                 /* External root clock */
1056                 extal_clk: extal {
1057                         compatible = "fixed-clock";
1058                         #clock-cells = <0>;
1059                         /* This value must be overriden by the board. */
1060                         clock-frequency = <0>;
1061                 };
1062
1063                 /* External PCIe clock - can be overridden by the board */
1064                 pcie_bus_clk: pcie_bus {
1065                         compatible = "fixed-clock";
1066                         #clock-cells = <0>;
1067                         clock-frequency = <0>;
1068                 };
1069
1070                 /*
1071                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1072                  * default. Boards that provide audio clocks should override them.
1073                  */
1074                 audio_clk_a: audio_clk_a {
1075                         compatible = "fixed-clock";
1076                         #clock-cells = <0>;
1077                         clock-frequency = <0>;
1078                 };
1079                 audio_clk_b: audio_clk_b {
1080                         compatible = "fixed-clock";
1081                         #clock-cells = <0>;
1082                         clock-frequency = <0>;
1083                 };
1084                 audio_clk_c: audio_clk_c {
1085                         compatible = "fixed-clock";
1086                         #clock-cells = <0>;
1087                         clock-frequency = <0>;
1088                 };
1089
1090                 /* External SCIF clock */
1091                 scif_clk: scif {
1092                         compatible = "fixed-clock";
1093                         #clock-cells = <0>;
1094                         /* This value must be overridden by the board. */
1095                         clock-frequency = <0>;
1096                 };
1097
1098                 /* External USB clock - can be overridden by the board */
1099                 usb_extal_clk: usb_extal {
1100                         compatible = "fixed-clock";
1101                         #clock-cells = <0>;
1102                         clock-frequency = <48000000>;
1103                 };
1104
1105                 /* External CAN clock */
1106                 can_clk: can_clk {
1107                         compatible = "fixed-clock";
1108                         #clock-cells = <0>;
1109                         /* This value must be overridden by the board. */
1110                         clock-frequency = <0>;
1111                 };
1112
1113                 /* Special CPG clocks */
1114                 cpg_clocks: cpg_clocks@e6150000 {
1115                         compatible = "renesas,r8a7790-cpg-clocks",
1116                                      "renesas,rcar-gen2-cpg-clocks";
1117                         reg = <0 0xe6150000 0 0x1000>;
1118                         clocks = <&extal_clk &usb_extal_clk>;
1119                         #clock-cells = <1>;
1120                         clock-output-names = "main", "pll0", "pll1", "pll3",
1121                                              "lb", "qspi", "sdh", "sd0", "sd1",
1122                                              "z", "rcan", "adsp";
1123                         #power-domain-cells = <0>;
1124                 };
1125
1126                 /* Variable factor clocks */
1127                 sd2_clk: sd2@e6150078 {
1128                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1129                         reg = <0 0xe6150078 0 4>;
1130                         clocks = <&pll1_div2_clk>;
1131                         #clock-cells = <0>;
1132                 };
1133                 sd3_clk: sd3@e615026c {
1134                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1135                         reg = <0 0xe615026c 0 4>;
1136                         clocks = <&pll1_div2_clk>;
1137                         #clock-cells = <0>;
1138                 };
1139                 mmc0_clk: mmc0@e6150240 {
1140                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1141                         reg = <0 0xe6150240 0 4>;
1142                         clocks = <&pll1_div2_clk>;
1143                         #clock-cells = <0>;
1144                 };
1145                 mmc1_clk: mmc1@e6150244 {
1146                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1147                         reg = <0 0xe6150244 0 4>;
1148                         clocks = <&pll1_div2_clk>;
1149                         #clock-cells = <0>;
1150                 };
1151                 ssp_clk: ssp@e6150248 {
1152                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1153                         reg = <0 0xe6150248 0 4>;
1154                         clocks = <&pll1_div2_clk>;
1155                         #clock-cells = <0>;
1156                 };
1157                 ssprs_clk: ssprs@e615024c {
1158                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1159                         reg = <0 0xe615024c 0 4>;
1160                         clocks = <&pll1_div2_clk>;
1161                         #clock-cells = <0>;
1162                 };
1163
1164                 /* Fixed factor clocks */
1165                 pll1_div2_clk: pll1_div2 {
1166                         compatible = "fixed-factor-clock";
1167                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1168                         #clock-cells = <0>;
1169                         clock-div = <2>;
1170                         clock-mult = <1>;
1171                 };
1172                 z2_clk: z2 {
1173                         compatible = "fixed-factor-clock";
1174                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1175                         #clock-cells = <0>;
1176                         clock-div = <2>;
1177                         clock-mult = <1>;
1178                 };
1179                 zg_clk: zg {
1180                         compatible = "fixed-factor-clock";
1181                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1182                         #clock-cells = <0>;
1183                         clock-div = <3>;
1184                         clock-mult = <1>;
1185                 };
1186                 zx_clk: zx {
1187                         compatible = "fixed-factor-clock";
1188                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1189                         #clock-cells = <0>;
1190                         clock-div = <3>;
1191                         clock-mult = <1>;
1192                 };
1193                 zs_clk: zs {
1194                         compatible = "fixed-factor-clock";
1195                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1196                         #clock-cells = <0>;
1197                         clock-div = <6>;
1198                         clock-mult = <1>;
1199                 };
1200                 hp_clk: hp {
1201                         compatible = "fixed-factor-clock";
1202                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1203                         #clock-cells = <0>;
1204                         clock-div = <12>;
1205                         clock-mult = <1>;
1206                 };
1207                 i_clk: i {
1208                         compatible = "fixed-factor-clock";
1209                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1210                         #clock-cells = <0>;
1211                         clock-div = <2>;
1212                         clock-mult = <1>;
1213                 };
1214                 b_clk: b {
1215                         compatible = "fixed-factor-clock";
1216                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1217                         #clock-cells = <0>;
1218                         clock-div = <12>;
1219                         clock-mult = <1>;
1220                 };
1221                 p_clk: p {
1222                         compatible = "fixed-factor-clock";
1223                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1224                         #clock-cells = <0>;
1225                         clock-div = <24>;
1226                         clock-mult = <1>;
1227                 };
1228                 cl_clk: cl {
1229                         compatible = "fixed-factor-clock";
1230                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1231                         #clock-cells = <0>;
1232                         clock-div = <48>;
1233                         clock-mult = <1>;
1234                 };
1235                 m2_clk: m2 {
1236                         compatible = "fixed-factor-clock";
1237                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1238                         #clock-cells = <0>;
1239                         clock-div = <8>;
1240                         clock-mult = <1>;
1241                 };
1242                 imp_clk: imp {
1243                         compatible = "fixed-factor-clock";
1244                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1245                         #clock-cells = <0>;
1246                         clock-div = <4>;
1247                         clock-mult = <1>;
1248                 };
1249                 rclk_clk: rclk {
1250                         compatible = "fixed-factor-clock";
1251                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1252                         #clock-cells = <0>;
1253                         clock-div = <(48 * 1024)>;
1254                         clock-mult = <1>;
1255                 };
1256                 oscclk_clk: oscclk {
1257                         compatible = "fixed-factor-clock";
1258                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1259                         #clock-cells = <0>;
1260                         clock-div = <(12 * 1024)>;
1261                         clock-mult = <1>;
1262                 };
1263                 zb3_clk: zb3 {
1264                         compatible = "fixed-factor-clock";
1265                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1266                         #clock-cells = <0>;
1267                         clock-div = <4>;
1268                         clock-mult = <1>;
1269                 };
1270                 zb3d2_clk: zb3d2 {
1271                         compatible = "fixed-factor-clock";
1272                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1273                         #clock-cells = <0>;
1274                         clock-div = <8>;
1275                         clock-mult = <1>;
1276                 };
1277                 ddr_clk: ddr {
1278                         compatible = "fixed-factor-clock";
1279                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1280                         #clock-cells = <0>;
1281                         clock-div = <8>;
1282                         clock-mult = <1>;
1283                 };
1284                 mp_clk: mp {
1285                         compatible = "fixed-factor-clock";
1286                         clocks = <&pll1_div2_clk>;
1287                         #clock-cells = <0>;
1288                         clock-div = <15>;
1289                         clock-mult = <1>;
1290                 };
1291                 cp_clk: cp {
1292                         compatible = "fixed-factor-clock";
1293                         clocks = <&extal_clk>;
1294                         #clock-cells = <0>;
1295                         clock-div = <2>;
1296                         clock-mult = <1>;
1297                 };
1298
1299                 /* Gate clocks */
1300                 mstp0_clks: mstp0_clks@e6150130 {
1301                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1302                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1303                         clocks = <&mp_clk>;
1304                         #clock-cells = <1>;
1305                         clock-indices = <R8A7790_CLK_MSIOF0>;
1306                         clock-output-names = "msiof0";
1307                 };
1308                 mstp1_clks: mstp1_clks@e6150134 {
1309                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1310                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1311                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1312                                  <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1313                                  <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1314                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1315                         #clock-cells = <1>;
1316                         clock-indices = <
1317                                 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1318                                 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1319                                 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1320                                 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1321                                 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1322                                 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1323                                 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1324                         >;
1325                         clock-output-names =
1326                                 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1327                                 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1328                                 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1329                                 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1330                 };
1331                 mstp2_clks: mstp2_clks@e6150138 {
1332                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1333                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1334                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1335                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1336                                  <&zs_clk>;
1337                         #clock-cells = <1>;
1338                         clock-indices = <
1339                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1340                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1341                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1342                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1343                         >;
1344                         clock-output-names =
1345                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1346                                 "scifb1", "msiof1", "msiof3", "scifb2",
1347                                 "sys-dmac1", "sys-dmac0";
1348                 };
1349                 mstp3_clks: mstp3_clks@e615013c {
1350                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1351                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1352                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
1353                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1354                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1355                                  <&hp_clk>, <&hp_clk>;
1356                         #clock-cells = <1>;
1357                         clock-indices = <
1358                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
1359                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1360                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1361                                 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1362                         >;
1363                         clock-output-names =
1364                                 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
1365                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1366                                 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1367                                 "usbdmac0", "usbdmac1";
1368                 };
1369                 mstp4_clks: mstp4_clks@e6150140 {
1370                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1371                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1372                         clocks = <&cp_clk>;
1373                         #clock-cells = <1>;
1374                         clock-indices = <R8A7790_CLK_IRQC>;
1375                         clock-output-names = "irqc";
1376                 };
1377                 mstp5_clks: mstp5_clks@e6150144 {
1378                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1379                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1380                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1381                                  <&extal_clk>, <&p_clk>;
1382                         #clock-cells = <1>;
1383                         clock-indices = <
1384                                 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1385                                 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1386                                 R8A7790_CLK_PWM
1387                         >;
1388                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1389                                              "thermal", "pwm";
1390                 };
1391                 mstp7_clks: mstp7_clks@e615014c {
1392                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1393                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1394                         clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1395                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1396                                  <&zx_clk>;
1397                         #clock-cells = <1>;
1398                         clock-indices = <
1399                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1400                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1401                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1402                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1403                         >;
1404                         clock-output-names =
1405                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1406                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1407                 };
1408                 mstp8_clks: mstp8_clks@e6150990 {
1409                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1410                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1411                         clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1412                                  <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1413                                  <&zs_clk>;
1414                         #clock-cells = <1>;
1415                         clock-indices = <
1416                                 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1417                                 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1418                                 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1419                                 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1420                         >;
1421                         clock-output-names =
1422                                 "mlb", "vin3", "vin2", "vin1", "vin0",
1423                                 "etheravb", "ether", "sata1", "sata0";
1424                 };
1425                 mstp9_clks: mstp9_clks@e6150994 {
1426                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1427                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1428                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1429                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
1430                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1431                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1432                         #clock-cells = <1>;
1433                         clock-indices = <
1434                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1435                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1436                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1437                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1438                         >;
1439                         clock-output-names =
1440                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1441                                 "rcan1", "rcan0", "qspi_mod", "iic3",
1442                                 "i2c3", "i2c2", "i2c1", "i2c0";
1443                 };
1444                 mstp10_clks: mstp10_clks@e6150998 {
1445                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1446                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1447                         clocks = <&p_clk>,
1448                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1449                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1450                                 <&p_clk>,
1451                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1452                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1453                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1454                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1455                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1456                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1457                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1458
1459                         #clock-cells = <1>;
1460                         clock-indices = <
1461                                 R8A7790_CLK_SSI_ALL
1462                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1463                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1464                                 R8A7790_CLK_SCU_ALL
1465                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1466                                 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1467                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1468                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1469                         >;
1470                         clock-output-names =
1471                                 "ssi-all",
1472                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1473                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1474                                 "scu-all",
1475                                 "scu-dvc1", "scu-dvc0",
1476                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1477                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1478                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1479                 };
1480         };
1481
1482         sysc: system-controller@e6180000 {
1483                 compatible = "renesas,r8a7790-sysc";
1484                 reg = <0 0xe6180000 0 0x0200>;
1485                 #power-domain-cells = <1>;
1486         };
1487
1488         qspi: spi@e6b10000 {
1489                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1490                 reg = <0 0xe6b10000 0 0x2c>;
1491                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1492                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1493                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1494                        <&dmac1 0x17>, <&dmac1 0x18>;
1495                 dma-names = "tx", "rx", "tx", "rx";
1496                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1497                 num-cs = <1>;
1498                 #address-cells = <1>;
1499                 #size-cells = <0>;
1500                 status = "disabled";
1501         };
1502
1503         msiof0: spi@e6e20000 {
1504                 compatible = "renesas,msiof-r8a7790";
1505                 reg = <0 0xe6e20000 0 0x0064>;
1506                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1507                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1508                 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1509                        <&dmac1 0x51>, <&dmac1 0x52>;
1510                 dma-names = "tx", "rx", "tx", "rx";
1511                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1512                 #address-cells = <1>;
1513                 #size-cells = <0>;
1514                 status = "disabled";
1515         };
1516
1517         msiof1: spi@e6e10000 {
1518                 compatible = "renesas,msiof-r8a7790";
1519                 reg = <0 0xe6e10000 0 0x0064>;
1520                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1521                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1522                 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1523                        <&dmac1 0x55>, <&dmac1 0x56>;
1524                 dma-names = "tx", "rx", "tx", "rx";
1525                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1526                 #address-cells = <1>;
1527                 #size-cells = <0>;
1528                 status = "disabled";
1529         };
1530
1531         msiof2: spi@e6e00000 {
1532                 compatible = "renesas,msiof-r8a7790";
1533                 reg = <0 0xe6e00000 0 0x0064>;
1534                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1535                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1536                 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1537                        <&dmac1 0x41>, <&dmac1 0x42>;
1538                 dma-names = "tx", "rx", "tx", "rx";
1539                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1540                 #address-cells = <1>;
1541                 #size-cells = <0>;
1542                 status = "disabled";
1543         };
1544
1545         msiof3: spi@e6c90000 {
1546                 compatible = "renesas,msiof-r8a7790";
1547                 reg = <0 0xe6c90000 0 0x0064>;
1548                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1549                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1550                 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1551                        <&dmac1 0x45>, <&dmac1 0x46>;
1552                 dma-names = "tx", "rx", "tx", "rx";
1553                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1554                 #address-cells = <1>;
1555                 #size-cells = <0>;
1556                 status = "disabled";
1557         };
1558
1559         xhci: usb@ee000000 {
1560                 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
1561                 reg = <0 0xee000000 0 0xc00>;
1562                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1563                 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1564                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1565                 phys = <&usb2 1>;
1566                 phy-names = "usb";
1567                 status = "disabled";
1568         };
1569
1570         pci0: pci@ee090000 {
1571                 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1572                 device_type = "pci";
1573                 reg = <0 0xee090000 0 0xc00>,
1574                       <0 0xee080000 0 0x1100>;
1575                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1576                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1577                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1578                 status = "disabled";
1579
1580                 bus-range = <0 0>;
1581                 #address-cells = <3>;
1582                 #size-cells = <2>;
1583                 #interrupt-cells = <1>;
1584                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1585                 interrupt-map-mask = <0xff00 0 0 0x7>;
1586                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1587                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1588                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1589
1590                 usb@0,1 {
1591                         reg = <0x800 0 0 0 0>;
1592                         device_type = "pci";
1593                         phys = <&usb0 0>;
1594                         phy-names = "usb";
1595                 };
1596
1597                 usb@0,2 {
1598                         reg = <0x1000 0 0 0 0>;
1599                         device_type = "pci";
1600                         phys = <&usb0 0>;
1601                         phy-names = "usb";
1602                 };
1603         };
1604
1605         pci1: pci@ee0b0000 {
1606                 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1607                 device_type = "pci";
1608                 reg = <0 0xee0b0000 0 0xc00>,
1609                       <0 0xee0a0000 0 0x1100>;
1610                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1611                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1612                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1613                 status = "disabled";
1614
1615                 bus-range = <1 1>;
1616                 #address-cells = <3>;
1617                 #size-cells = <2>;
1618                 #interrupt-cells = <1>;
1619                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1620                 interrupt-map-mask = <0xff00 0 0 0x7>;
1621                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1622                                  0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1623                                  0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1624         };
1625
1626         pci2: pci@ee0d0000 {
1627                 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1628                 device_type = "pci";
1629                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1630                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1631                 reg = <0 0xee0d0000 0 0xc00>,
1632                       <0 0xee0c0000 0 0x1100>;
1633                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1634                 status = "disabled";
1635
1636                 bus-range = <2 2>;
1637                 #address-cells = <3>;
1638                 #size-cells = <2>;
1639                 #interrupt-cells = <1>;
1640                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1641                 interrupt-map-mask = <0xff00 0 0 0x7>;
1642                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1643                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1644                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1645
1646                 usb@0,1 {
1647                         reg = <0x800 0 0 0 0>;
1648                         device_type = "pci";
1649                         phys = <&usb2 0>;
1650                         phy-names = "usb";
1651                 };
1652
1653                 usb@0,2 {
1654                         reg = <0x1000 0 0 0 0>;
1655                         device_type = "pci";
1656                         phys = <&usb2 0>;
1657                         phy-names = "usb";
1658                 };
1659         };
1660
1661         pciec: pcie@fe000000 {
1662                 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1663                 reg = <0 0xfe000000 0 0x80000>;
1664                 #address-cells = <3>;
1665                 #size-cells = <2>;
1666                 bus-range = <0x00 0xff>;
1667                 device_type = "pci";
1668                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1669                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1670                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1671                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1672                 /* Map all possible DDR as inbound ranges */
1673                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1674                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1675                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1676                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1677                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1678                 #interrupt-cells = <1>;
1679                 interrupt-map-mask = <0 0 0 0>;
1680                 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1681                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1682                 clock-names = "pcie", "pcie_bus";
1683                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1684                 status = "disabled";
1685         };
1686
1687         rcar_sound: sound@ec500000 {
1688                 /*
1689                  * #sound-dai-cells is required
1690                  *
1691                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1692                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1693                  */
1694                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1695                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1696                         <0 0xec5a0000 0 0x100>,  /* ADG */
1697                         <0 0xec540000 0 0x1000>, /* SSIU */
1698                         <0 0xec541000 0 0x280>,  /* SSI */
1699                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1700                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1701
1702                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1703                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1704                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1705                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1706                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1707                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1708                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1709                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1710                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1711                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1712                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1713                         <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1714                         <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1715                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1716                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1717                 clock-names = "ssi-all",
1718                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1719                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1720                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1721                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1722                                 "ctu.0", "ctu.1",
1723                                 "mix.0", "mix.1",
1724                                 "dvc.0", "dvc.1",
1725                                 "clk_a", "clk_b", "clk_c", "clk_i";
1726                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1727
1728                 status = "disabled";
1729
1730                 rcar_sound,dvc {
1731                         dvc0: dvc@0 {
1732                                 dmas = <&audma0 0xbc>;
1733                                 dma-names = "tx";
1734                         };
1735                         dvc1: dvc@1 {
1736                                 dmas = <&audma0 0xbe>;
1737                                 dma-names = "tx";
1738                         };
1739                 };
1740
1741                 rcar_sound,mix {
1742                         mix0: mix@0 { };
1743                         mix1: mix@1 { };
1744                 };
1745
1746                 rcar_sound,ctu {
1747                         ctu00: ctu@0 { };
1748                         ctu01: ctu@1 { };
1749                         ctu02: ctu@2 { };
1750                         ctu03: ctu@3 { };
1751                         ctu10: ctu@4 { };
1752                         ctu11: ctu@5 { };
1753                         ctu12: ctu@6 { };
1754                         ctu13: ctu@7 { };
1755                 };
1756
1757                 rcar_sound,src {
1758                         src0: src@0 {
1759                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1760                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1761                                 dma-names = "rx", "tx";
1762                         };
1763                         src1: src@1 {
1764                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1765                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1766                                 dma-names = "rx", "tx";
1767                         };
1768                         src2: src@2 {
1769                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1770                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1771                                 dma-names = "rx", "tx";
1772                         };
1773                         src3: src@3 {
1774                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1775                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1776                                 dma-names = "rx", "tx";
1777                         };
1778                         src4: src@4 {
1779                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1780                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1781                                 dma-names = "rx", "tx";
1782                         };
1783                         src5: src@5 {
1784                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1785                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1786                                 dma-names = "rx", "tx";
1787                         };
1788                         src6: src@6 {
1789                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1790                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1791                                 dma-names = "rx", "tx";
1792                         };
1793                         src7: src@7 {
1794                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1795                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1796                                 dma-names = "rx", "tx";
1797                         };
1798                         src8: src@8 {
1799                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1800                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1801                                 dma-names = "rx", "tx";
1802                         };
1803                         src9: src@9 {
1804                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1805                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1806                                 dma-names = "rx", "tx";
1807                         };
1808                 };
1809
1810                 rcar_sound,ssi {
1811                         ssi0: ssi@0 {
1812                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1813                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1814                                 dma-names = "rx", "tx", "rxu", "txu";
1815                         };
1816                         ssi1: ssi@1 {
1817                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1818                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1819                                 dma-names = "rx", "tx", "rxu", "txu";
1820                         };
1821                         ssi2: ssi@2 {
1822                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1823                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1824                                 dma-names = "rx", "tx", "rxu", "txu";
1825                         };
1826                         ssi3: ssi@3 {
1827                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1828                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1829                                 dma-names = "rx", "tx", "rxu", "txu";
1830                         };
1831                         ssi4: ssi@4 {
1832                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1833                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1834                                 dma-names = "rx", "tx", "rxu", "txu";
1835                         };
1836                         ssi5: ssi@5 {
1837                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1838                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1839                                 dma-names = "rx", "tx", "rxu", "txu";
1840                         };
1841                         ssi6: ssi@6 {
1842                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1843                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1844                                 dma-names = "rx", "tx", "rxu", "txu";
1845                         };
1846                         ssi7: ssi@7 {
1847                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1848                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1849                                 dma-names = "rx", "tx", "rxu", "txu";
1850                         };
1851                         ssi8: ssi@8 {
1852                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1853                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1854                                 dma-names = "rx", "tx", "rxu", "txu";
1855                         };
1856                         ssi9: ssi@9 {
1857                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1858                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1859                                 dma-names = "rx", "tx", "rxu", "txu";
1860                         };
1861                 };
1862         };
1863
1864         ipmmu_sy0: mmu@e6280000 {
1865                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1866                 reg = <0 0xe6280000 0 0x1000>;
1867                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1868                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1869                 #iommu-cells = <1>;
1870                 status = "disabled";
1871         };
1872
1873         ipmmu_sy1: mmu@e6290000 {
1874                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1875                 reg = <0 0xe6290000 0 0x1000>;
1876                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1877                 #iommu-cells = <1>;
1878                 status = "disabled";
1879         };
1880
1881         ipmmu_ds: mmu@e6740000 {
1882                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1883                 reg = <0 0xe6740000 0 0x1000>;
1884                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1885                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1886                 #iommu-cells = <1>;
1887                 status = "disabled";
1888         };
1889
1890         ipmmu_mp: mmu@ec680000 {
1891                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1892                 reg = <0 0xec680000 0 0x1000>;
1893                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1894                 #iommu-cells = <1>;
1895                 status = "disabled";
1896         };
1897
1898         ipmmu_mx: mmu@fe951000 {
1899                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1900                 reg = <0 0xfe951000 0 0x1000>;
1901                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1902                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1903                 #iommu-cells = <1>;
1904                 status = "disabled";
1905         };
1906
1907         ipmmu_rt: mmu@ffc80000 {
1908                 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1909                 reg = <0 0xffc80000 0 0x1000>;
1910                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1911                 #iommu-cells = <1>;
1912                 status = "disabled";
1913         };
1914 };