2 * Device Tree Source for the r8a7791 SoC
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a15";
50 clock-frequency = <1500000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
66 compatible = "arm,cortex-a15";
68 clock-frequency = <1500000000>;
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,gic-400";
74 #interrupt-cells = <3>;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
84 gpio0: gpio@e6050000 {
85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
86 reg = <0 0xe6050000 0 0x50>;
87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
94 power-domains = <&cpg_clocks>;
97 gpio1: gpio@e6051000 {
98 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
99 reg = <0 0xe6051000 0 0x50>;
100 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
103 gpio-ranges = <&pfc 0 32 26>;
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
107 power-domains = <&cpg_clocks>;
110 gpio2: gpio@e6052000 {
111 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
112 reg = <0 0xe6052000 0 0x50>;
113 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
116 gpio-ranges = <&pfc 0 64 32>;
117 #interrupt-cells = <2>;
118 interrupt-controller;
119 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
120 power-domains = <&cpg_clocks>;
123 gpio3: gpio@e6053000 {
124 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
125 reg = <0 0xe6053000 0 0x50>;
126 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
129 gpio-ranges = <&pfc 0 96 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
133 power-domains = <&cpg_clocks>;
136 gpio4: gpio@e6054000 {
137 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
138 reg = <0 0xe6054000 0 0x50>;
139 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
142 gpio-ranges = <&pfc 0 128 32>;
143 #interrupt-cells = <2>;
144 interrupt-controller;
145 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
146 power-domains = <&cpg_clocks>;
149 gpio5: gpio@e6055000 {
150 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
151 reg = <0 0xe6055000 0 0x50>;
152 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
155 gpio-ranges = <&pfc 0 160 32>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
158 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
159 power-domains = <&cpg_clocks>;
162 gpio6: gpio@e6055400 {
163 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
164 reg = <0 0xe6055400 0 0x50>;
165 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
168 gpio-ranges = <&pfc 0 192 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
172 power-domains = <&cpg_clocks>;
175 gpio7: gpio@e6055800 {
176 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
177 reg = <0 0xe6055800 0 0x50>;
178 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
181 gpio-ranges = <&pfc 0 224 26>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
184 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
185 power-domains = <&cpg_clocks>;
189 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
190 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
191 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
193 power-domains = <&cpg_clocks>;
197 compatible = "arm,armv7-timer";
198 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
199 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
200 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
201 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
204 cmt0: timer@ffca0000 {
205 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
206 reg = <0 0xffca0000 0 0x1004>;
207 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
208 <0 143 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
211 power-domains = <&cpg_clocks>;
213 renesas,channels-mask = <0x60>;
218 cmt1: timer@e6130000 {
219 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
220 reg = <0 0xe6130000 0 0x1004>;
221 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
222 <0 121 IRQ_TYPE_LEVEL_HIGH>,
223 <0 122 IRQ_TYPE_LEVEL_HIGH>,
224 <0 123 IRQ_TYPE_LEVEL_HIGH>,
225 <0 124 IRQ_TYPE_LEVEL_HIGH>,
226 <0 125 IRQ_TYPE_LEVEL_HIGH>,
227 <0 126 IRQ_TYPE_LEVEL_HIGH>,
228 <0 127 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
231 power-domains = <&cpg_clocks>;
233 renesas,channels-mask = <0xff>;
238 irqc0: interrupt-controller@e61c0000 {
239 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
240 #interrupt-cells = <2>;
241 interrupt-controller;
242 reg = <0 0xe61c0000 0 0x200>;
243 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
244 <0 1 IRQ_TYPE_LEVEL_HIGH>,
245 <0 2 IRQ_TYPE_LEVEL_HIGH>,
246 <0 3 IRQ_TYPE_LEVEL_HIGH>,
247 <0 12 IRQ_TYPE_LEVEL_HIGH>,
248 <0 13 IRQ_TYPE_LEVEL_HIGH>,
249 <0 14 IRQ_TYPE_LEVEL_HIGH>,
250 <0 15 IRQ_TYPE_LEVEL_HIGH>,
251 <0 16 IRQ_TYPE_LEVEL_HIGH>,
252 <0 17 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
254 power-domains = <&cpg_clocks>;
257 dmac0: dma-controller@e6700000 {
258 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
259 reg = <0 0xe6700000 0 0x20000>;
260 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
261 0 200 IRQ_TYPE_LEVEL_HIGH
262 0 201 IRQ_TYPE_LEVEL_HIGH
263 0 202 IRQ_TYPE_LEVEL_HIGH
264 0 203 IRQ_TYPE_LEVEL_HIGH
265 0 204 IRQ_TYPE_LEVEL_HIGH
266 0 205 IRQ_TYPE_LEVEL_HIGH
267 0 206 IRQ_TYPE_LEVEL_HIGH
268 0 207 IRQ_TYPE_LEVEL_HIGH
269 0 208 IRQ_TYPE_LEVEL_HIGH
270 0 209 IRQ_TYPE_LEVEL_HIGH
271 0 210 IRQ_TYPE_LEVEL_HIGH
272 0 211 IRQ_TYPE_LEVEL_HIGH
273 0 212 IRQ_TYPE_LEVEL_HIGH
274 0 213 IRQ_TYPE_LEVEL_HIGH
275 0 214 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "error",
277 "ch0", "ch1", "ch2", "ch3",
278 "ch4", "ch5", "ch6", "ch7",
279 "ch8", "ch9", "ch10", "ch11",
280 "ch12", "ch13", "ch14";
281 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
283 power-domains = <&cpg_clocks>;
288 dmac1: dma-controller@e6720000 {
289 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
290 reg = <0 0xe6720000 0 0x20000>;
291 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
292 0 216 IRQ_TYPE_LEVEL_HIGH
293 0 217 IRQ_TYPE_LEVEL_HIGH
294 0 218 IRQ_TYPE_LEVEL_HIGH
295 0 219 IRQ_TYPE_LEVEL_HIGH
296 0 308 IRQ_TYPE_LEVEL_HIGH
297 0 309 IRQ_TYPE_LEVEL_HIGH
298 0 310 IRQ_TYPE_LEVEL_HIGH
299 0 311 IRQ_TYPE_LEVEL_HIGH
300 0 312 IRQ_TYPE_LEVEL_HIGH
301 0 313 IRQ_TYPE_LEVEL_HIGH
302 0 314 IRQ_TYPE_LEVEL_HIGH
303 0 315 IRQ_TYPE_LEVEL_HIGH
304 0 316 IRQ_TYPE_LEVEL_HIGH
305 0 317 IRQ_TYPE_LEVEL_HIGH
306 0 318 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-names = "error",
308 "ch0", "ch1", "ch2", "ch3",
309 "ch4", "ch5", "ch6", "ch7",
310 "ch8", "ch9", "ch10", "ch11",
311 "ch12", "ch13", "ch14";
312 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
314 power-domains = <&cpg_clocks>;
319 audma0: dma-controller@ec700000 {
320 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
321 reg = <0 0xec700000 0 0x10000>;
322 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
323 0 320 IRQ_TYPE_LEVEL_HIGH
324 0 321 IRQ_TYPE_LEVEL_HIGH
325 0 322 IRQ_TYPE_LEVEL_HIGH
326 0 323 IRQ_TYPE_LEVEL_HIGH
327 0 324 IRQ_TYPE_LEVEL_HIGH
328 0 325 IRQ_TYPE_LEVEL_HIGH
329 0 326 IRQ_TYPE_LEVEL_HIGH
330 0 327 IRQ_TYPE_LEVEL_HIGH
331 0 328 IRQ_TYPE_LEVEL_HIGH
332 0 329 IRQ_TYPE_LEVEL_HIGH
333 0 330 IRQ_TYPE_LEVEL_HIGH
334 0 331 IRQ_TYPE_LEVEL_HIGH
335 0 332 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "error",
337 "ch0", "ch1", "ch2", "ch3",
338 "ch4", "ch5", "ch6", "ch7",
339 "ch8", "ch9", "ch10", "ch11",
341 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
343 power-domains = <&cpg_clocks>;
348 audma1: dma-controller@ec720000 {
349 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
350 reg = <0 0xec720000 0 0x10000>;
351 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
352 0 333 IRQ_TYPE_LEVEL_HIGH
353 0 334 IRQ_TYPE_LEVEL_HIGH
354 0 335 IRQ_TYPE_LEVEL_HIGH
355 0 336 IRQ_TYPE_LEVEL_HIGH
356 0 337 IRQ_TYPE_LEVEL_HIGH
357 0 338 IRQ_TYPE_LEVEL_HIGH
358 0 339 IRQ_TYPE_LEVEL_HIGH
359 0 340 IRQ_TYPE_LEVEL_HIGH
360 0 341 IRQ_TYPE_LEVEL_HIGH
361 0 342 IRQ_TYPE_LEVEL_HIGH
362 0 343 IRQ_TYPE_LEVEL_HIGH
363 0 344 IRQ_TYPE_LEVEL_HIGH
364 0 345 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "error",
366 "ch0", "ch1", "ch2", "ch3",
367 "ch4", "ch5", "ch6", "ch7",
368 "ch8", "ch9", "ch10", "ch11",
370 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
372 power-domains = <&cpg_clocks>;
377 usb_dmac0: dma-controller@e65a0000 {
378 compatible = "renesas,usb-dmac";
379 reg = <0 0xe65a0000 0 0x100>;
380 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
381 0 109 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "ch0", "ch1";
383 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
384 power-domains = <&cpg_clocks>;
389 usb_dmac1: dma-controller@e65b0000 {
390 compatible = "renesas,usb-dmac";
391 reg = <0 0xe65b0000 0 0x100>;
392 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
393 0 110 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-names = "ch0", "ch1";
395 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
396 power-domains = <&cpg_clocks>;
401 /* The memory map in the User's Manual maps the cores to bus numbers */
403 #address-cells = <1>;
405 compatible = "renesas,i2c-r8a7791";
406 reg = <0 0xe6508000 0 0x40>;
407 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
409 power-domains = <&cpg_clocks>;
414 #address-cells = <1>;
416 compatible = "renesas,i2c-r8a7791";
417 reg = <0 0xe6518000 0 0x40>;
418 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
420 power-domains = <&cpg_clocks>;
425 #address-cells = <1>;
427 compatible = "renesas,i2c-r8a7791";
428 reg = <0 0xe6530000 0 0x40>;
429 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
431 power-domains = <&cpg_clocks>;
436 #address-cells = <1>;
438 compatible = "renesas,i2c-r8a7791";
439 reg = <0 0xe6540000 0 0x40>;
440 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
442 power-domains = <&cpg_clocks>;
447 #address-cells = <1>;
449 compatible = "renesas,i2c-r8a7791";
450 reg = <0 0xe6520000 0 0x40>;
451 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
453 power-domains = <&cpg_clocks>;
458 /* doesn't need pinmux */
459 #address-cells = <1>;
461 compatible = "renesas,i2c-r8a7791";
462 reg = <0 0xe6528000 0 0x40>;
463 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
465 power-domains = <&cpg_clocks>;
470 /* doesn't need pinmux */
471 #address-cells = <1>;
473 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
474 reg = <0 0xe60b0000 0 0x425>;
475 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
477 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
478 dma-names = "tx", "rx";
479 power-domains = <&cpg_clocks>;
484 #address-cells = <1>;
486 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
487 reg = <0 0xe6500000 0 0x425>;
488 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
490 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
491 dma-names = "tx", "rx";
492 power-domains = <&cpg_clocks>;
497 #address-cells = <1>;
499 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
500 reg = <0 0xe6510000 0 0x425>;
501 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
503 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
504 dma-names = "tx", "rx";
505 power-domains = <&cpg_clocks>;
510 compatible = "renesas,pfc-r8a7791";
511 reg = <0 0xe6060000 0 0x250>;
512 #gpio-range-cells = <3>;
515 mmcif0: mmc@ee200000 {
516 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
517 reg = <0 0xee200000 0 0x80>;
518 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
520 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
521 dma-names = "tx", "rx";
522 power-domains = <&cpg_clocks>;
525 max-frequency = <97500000>;
529 compatible = "renesas,sdhi-r8a7791";
530 reg = <0 0xee100000 0 0x328>;
531 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
533 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
534 dma-names = "tx", "rx";
535 power-domains = <&cpg_clocks>;
540 compatible = "renesas,sdhi-r8a7791";
541 reg = <0 0xee140000 0 0x100>;
542 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
544 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
545 dma-names = "tx", "rx";
546 power-domains = <&cpg_clocks>;
551 compatible = "renesas,sdhi-r8a7791";
552 reg = <0 0xee160000 0 0x100>;
553 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
555 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
556 dma-names = "tx", "rx";
557 power-domains = <&cpg_clocks>;
561 scifa0: serial@e6c40000 {
562 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
563 reg = <0 0xe6c40000 0 64>;
564 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
566 clock-names = "sci_ick";
567 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
568 dma-names = "tx", "rx";
569 power-domains = <&cpg_clocks>;
573 scifa1: serial@e6c50000 {
574 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
575 reg = <0 0xe6c50000 0 64>;
576 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
578 clock-names = "sci_ick";
579 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
580 dma-names = "tx", "rx";
581 power-domains = <&cpg_clocks>;
585 scifa2: serial@e6c60000 {
586 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
587 reg = <0 0xe6c60000 0 64>;
588 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
590 clock-names = "sci_ick";
591 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
592 dma-names = "tx", "rx";
593 power-domains = <&cpg_clocks>;
597 scifa3: serial@e6c70000 {
598 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
599 reg = <0 0xe6c70000 0 64>;
600 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
602 clock-names = "sci_ick";
603 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
604 dma-names = "tx", "rx";
605 power-domains = <&cpg_clocks>;
609 scifa4: serial@e6c78000 {
610 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
611 reg = <0 0xe6c78000 0 64>;
612 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
614 clock-names = "sci_ick";
615 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
616 dma-names = "tx", "rx";
617 power-domains = <&cpg_clocks>;
621 scifa5: serial@e6c80000 {
622 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
623 reg = <0 0xe6c80000 0 64>;
624 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
626 clock-names = "sci_ick";
627 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
628 dma-names = "tx", "rx";
629 power-domains = <&cpg_clocks>;
633 scifb0: serial@e6c20000 {
634 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
635 reg = <0 0xe6c20000 0 64>;
636 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
638 clock-names = "sci_ick";
639 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
640 dma-names = "tx", "rx";
641 power-domains = <&cpg_clocks>;
645 scifb1: serial@e6c30000 {
646 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
647 reg = <0 0xe6c30000 0 64>;
648 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
650 clock-names = "sci_ick";
651 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
652 dma-names = "tx", "rx";
653 power-domains = <&cpg_clocks>;
657 scifb2: serial@e6ce0000 {
658 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
659 reg = <0 0xe6ce0000 0 64>;
660 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
662 clock-names = "sci_ick";
663 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
664 dma-names = "tx", "rx";
665 power-domains = <&cpg_clocks>;
669 scif0: serial@e6e60000 {
670 compatible = "renesas,scif-r8a7791", "renesas,scif";
671 reg = <0 0xe6e60000 0 64>;
672 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
674 clock-names = "sci_ick";
675 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
676 dma-names = "tx", "rx";
677 power-domains = <&cpg_clocks>;
681 scif1: serial@e6e68000 {
682 compatible = "renesas,scif-r8a7791", "renesas,scif";
683 reg = <0 0xe6e68000 0 64>;
684 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
686 clock-names = "sci_ick";
687 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
688 dma-names = "tx", "rx";
689 power-domains = <&cpg_clocks>;
693 scif2: serial@e6e58000 {
694 compatible = "renesas,scif-r8a7791", "renesas,scif";
695 reg = <0 0xe6e58000 0 64>;
696 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
698 clock-names = "sci_ick";
699 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
700 dma-names = "tx", "rx";
701 power-domains = <&cpg_clocks>;
705 scif3: serial@e6ea8000 {
706 compatible = "renesas,scif-r8a7791", "renesas,scif";
707 reg = <0 0xe6ea8000 0 64>;
708 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
710 clock-names = "sci_ick";
711 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
712 dma-names = "tx", "rx";
713 power-domains = <&cpg_clocks>;
717 scif4: serial@e6ee0000 {
718 compatible = "renesas,scif-r8a7791", "renesas,scif";
719 reg = <0 0xe6ee0000 0 64>;
720 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
722 clock-names = "sci_ick";
723 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
724 dma-names = "tx", "rx";
725 power-domains = <&cpg_clocks>;
729 scif5: serial@e6ee8000 {
730 compatible = "renesas,scif-r8a7791", "renesas,scif";
731 reg = <0 0xe6ee8000 0 64>;
732 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
734 clock-names = "sci_ick";
735 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
736 dma-names = "tx", "rx";
737 power-domains = <&cpg_clocks>;
741 hscif0: serial@e62c0000 {
742 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
743 reg = <0 0xe62c0000 0 96>;
744 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
746 clock-names = "sci_ick";
747 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
748 dma-names = "tx", "rx";
749 power-domains = <&cpg_clocks>;
753 hscif1: serial@e62c8000 {
754 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
755 reg = <0 0xe62c8000 0 96>;
756 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
758 clock-names = "sci_ick";
759 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
760 dma-names = "tx", "rx";
761 power-domains = <&cpg_clocks>;
765 hscif2: serial@e62d0000 {
766 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
767 reg = <0 0xe62d0000 0 96>;
768 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
770 clock-names = "sci_ick";
771 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
772 dma-names = "tx", "rx";
773 power-domains = <&cpg_clocks>;
777 ether: ethernet@ee700000 {
778 compatible = "renesas,ether-r8a7791";
779 reg = <0 0xee700000 0 0x400>;
780 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
782 power-domains = <&cpg_clocks>;
784 #address-cells = <1>;
789 sata0: sata@ee300000 {
790 compatible = "renesas,sata-r8a7791";
791 reg = <0 0xee300000 0 0x2000>;
792 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
794 power-domains = <&cpg_clocks>;
798 sata1: sata@ee500000 {
799 compatible = "renesas,sata-r8a7791";
800 reg = <0 0xee500000 0 0x2000>;
801 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
803 power-domains = <&cpg_clocks>;
807 hsusb: usb@e6590000 {
808 compatible = "renesas,usbhs-r8a7791";
809 reg = <0 0xe6590000 0 0x100>;
810 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
812 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
813 <&usb_dmac1 0>, <&usb_dmac1 1>;
814 dma-names = "ch0", "ch1", "ch2", "ch3";
815 power-domains = <&cpg_clocks>;
816 renesas,buswait = <4>;
822 usbphy: usb-phy@e6590100 {
823 compatible = "renesas,usb-phy-r8a7791";
824 reg = <0 0xe6590100 0 0x100>;
825 #address-cells = <1>;
827 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
828 clock-names = "usbhs";
829 power-domains = <&cpg_clocks>;
832 usb0: usb-channel@0 {
836 usb2: usb-channel@2 {
842 vin0: video@e6ef0000 {
843 compatible = "renesas,vin-r8a7791";
844 reg = <0 0xe6ef0000 0 0x1000>;
845 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
847 power-domains = <&cpg_clocks>;
851 vin1: video@e6ef1000 {
852 compatible = "renesas,vin-r8a7791";
853 reg = <0 0xe6ef1000 0 0x1000>;
854 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
856 power-domains = <&cpg_clocks>;
860 vin2: video@e6ef2000 {
861 compatible = "renesas,vin-r8a7791";
862 reg = <0 0xe6ef2000 0 0x1000>;
863 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
865 power-domains = <&cpg_clocks>;
870 compatible = "renesas,vsp1";
871 reg = <0 0xfe928000 0 0x8000>;
872 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
874 power-domains = <&cpg_clocks>;
884 compatible = "renesas,vsp1";
885 reg = <0 0xfe930000 0 0x8000>;
886 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
888 power-domains = <&cpg_clocks>;
898 compatible = "renesas,vsp1";
899 reg = <0 0xfe938000 0 0x8000>;
900 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
902 power-domains = <&cpg_clocks>;
911 du: display@feb00000 {
912 compatible = "renesas,du-r8a7791";
913 reg = <0 0xfeb00000 0 0x40000>,
914 <0 0xfeb90000 0 0x1c>;
915 reg-names = "du", "lvds.0";
916 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
917 <0 268 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
919 <&mstp7_clks R8A7791_CLK_DU1>,
920 <&mstp7_clks R8A7791_CLK_LVDS0>;
921 clock-names = "du.0", "du.1", "lvds.0";
925 #address-cells = <1>;
930 du_out_rgb: endpoint {
935 du_out_lvds0: endpoint {
942 compatible = "renesas,can-r8a7791";
943 reg = <0 0xe6e80000 0 0x1000>;
944 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
946 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
947 clock-names = "clkp1", "clkp2", "can_clk";
948 power-domains = <&cpg_clocks>;
953 compatible = "renesas,can-r8a7791";
954 reg = <0 0xe6e88000 0 0x1000>;
955 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
957 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
958 clock-names = "clkp1", "clkp2", "can_clk";
959 power-domains = <&cpg_clocks>;
963 jpu: jpeg-codec@fe980000 {
964 compatible = "renesas,jpu-r8a7791";
965 reg = <0 0xfe980000 0 0x10300>;
966 interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
968 power-domains = <&cpg_clocks>;
972 #address-cells = <2>;
976 /* External root clock */
977 extal_clk: extal_clk {
978 compatible = "fixed-clock";
980 /* This value must be overriden by the board. */
981 clock-frequency = <0>;
982 clock-output-names = "extal";
986 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
987 * default. Boards that provide audio clocks should override them.
989 audio_clk_a: audio_clk_a {
990 compatible = "fixed-clock";
992 clock-frequency = <0>;
993 clock-output-names = "audio_clk_a";
995 audio_clk_b: audio_clk_b {
996 compatible = "fixed-clock";
998 clock-frequency = <0>;
999 clock-output-names = "audio_clk_b";
1001 audio_clk_c: audio_clk_c {
1002 compatible = "fixed-clock";
1004 clock-frequency = <0>;
1005 clock-output-names = "audio_clk_c";
1008 /* External PCIe clock - can be overridden by the board */
1009 pcie_bus_clk: pcie_bus_clk {
1010 compatible = "fixed-clock";
1012 clock-frequency = <100000000>;
1013 clock-output-names = "pcie_bus";
1014 status = "disabled";
1017 /* External USB clock - can be overridden by the board */
1018 usb_extal_clk: usb_extal_clk {
1019 compatible = "fixed-clock";
1021 clock-frequency = <48000000>;
1022 clock-output-names = "usb_extal";
1025 /* External CAN clock */
1027 compatible = "fixed-clock";
1029 /* This value must be overridden by the board. */
1030 clock-frequency = <0>;
1031 clock-output-names = "can_clk";
1032 status = "disabled";
1035 /* Special CPG clocks */
1036 cpg_clocks: cpg_clocks@e6150000 {
1037 compatible = "renesas,r8a7791-cpg-clocks",
1038 "renesas,rcar-gen2-cpg-clocks";
1039 reg = <0 0xe6150000 0 0x1000>;
1040 clocks = <&extal_clk &usb_extal_clk>;
1042 clock-output-names = "main", "pll0", "pll1", "pll3",
1043 "lb", "qspi", "sdh", "sd0", "z",
1045 #power-domain-cells = <0>;
1048 /* Variable factor clocks */
1049 sd2_clk: sd2_clk@e6150078 {
1050 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1051 reg = <0 0xe6150078 0 4>;
1052 clocks = <&pll1_div2_clk>;
1054 clock-output-names = "sd2";
1056 sd3_clk: sd3_clk@e615026c {
1057 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1058 reg = <0 0xe615026c 0 4>;
1059 clocks = <&pll1_div2_clk>;
1061 clock-output-names = "sd3";
1063 mmc0_clk: mmc0_clk@e6150240 {
1064 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1065 reg = <0 0xe6150240 0 4>;
1066 clocks = <&pll1_div2_clk>;
1068 clock-output-names = "mmc0";
1070 ssp_clk: ssp_clk@e6150248 {
1071 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1072 reg = <0 0xe6150248 0 4>;
1073 clocks = <&pll1_div2_clk>;
1075 clock-output-names = "ssp";
1077 ssprs_clk: ssprs_clk@e615024c {
1078 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1079 reg = <0 0xe615024c 0 4>;
1080 clocks = <&pll1_div2_clk>;
1082 clock-output-names = "ssprs";
1085 /* Fixed factor clocks */
1086 pll1_div2_clk: pll1_div2_clk {
1087 compatible = "fixed-factor-clock";
1088 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1092 clock-output-names = "pll1_div2";
1095 compatible = "fixed-factor-clock";
1096 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1100 clock-output-names = "zg";
1103 compatible = "fixed-factor-clock";
1104 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1108 clock-output-names = "zx";
1111 compatible = "fixed-factor-clock";
1112 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1116 clock-output-names = "zs";
1119 compatible = "fixed-factor-clock";
1120 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1124 clock-output-names = "hp";
1127 compatible = "fixed-factor-clock";
1128 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1132 clock-output-names = "i";
1135 compatible = "fixed-factor-clock";
1136 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1140 clock-output-names = "b";
1143 compatible = "fixed-factor-clock";
1144 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1148 clock-output-names = "p";
1151 compatible = "fixed-factor-clock";
1152 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1156 clock-output-names = "cl";
1159 compatible = "fixed-factor-clock";
1160 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1164 clock-output-names = "m2";
1166 rclk_clk: rclk_clk {
1167 compatible = "fixed-factor-clock";
1168 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1170 clock-div = <(48 * 1024)>;
1172 clock-output-names = "rclk";
1174 oscclk_clk: oscclk_clk {
1175 compatible = "fixed-factor-clock";
1176 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1178 clock-div = <(12 * 1024)>;
1180 clock-output-names = "oscclk";
1183 compatible = "fixed-factor-clock";
1184 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1188 clock-output-names = "zb3";
1190 zb3d2_clk: zb3d2_clk {
1191 compatible = "fixed-factor-clock";
1192 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1196 clock-output-names = "zb3d2";
1199 compatible = "fixed-factor-clock";
1200 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1204 clock-output-names = "ddr";
1207 compatible = "fixed-factor-clock";
1208 clocks = <&pll1_div2_clk>;
1212 clock-output-names = "mp";
1215 compatible = "fixed-factor-clock";
1216 clocks = <&extal_clk>;
1220 clock-output-names = "cp";
1224 mstp0_clks: mstp0_clks@e6150130 {
1225 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1226 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1229 clock-indices = <R8A7791_CLK_MSIOF0>;
1230 clock-output-names = "msiof0";
1232 mstp1_clks: mstp1_clks@e6150134 {
1233 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1234 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1235 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1236 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1237 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1241 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1242 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1243 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1244 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1245 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1248 clock-output-names =
1249 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1250 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1251 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1253 mstp2_clks: mstp2_clks@e6150138 {
1254 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1255 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1256 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1257 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1258 <&zs_clk>, <&zs_clk>;
1261 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1262 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1263 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1264 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1266 clock-output-names =
1267 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1268 "scifb1", "msiof1", "scifb2",
1269 "sys-dmac1", "sys-dmac0";
1271 mstp3_clks: mstp3_clks@e615013c {
1272 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1273 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1274 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1275 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1276 <&hp_clk>, <&hp_clk>;
1279 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1280 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1281 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1282 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1284 clock-output-names =
1285 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1286 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1287 "usbdmac0", "usbdmac1";
1289 mstp4_clks: mstp4_clks@e6150140 {
1290 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1291 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1294 clock-indices = <R8A7791_CLK_IRQC>;
1295 clock-output-names = "irqc";
1297 mstp5_clks: mstp5_clks@e6150144 {
1298 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1299 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1300 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1301 <&extal_clk>, <&p_clk>;
1304 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1305 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1308 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1311 mstp7_clks: mstp7_clks@e615014c {
1312 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1313 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1314 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1315 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1316 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1319 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1320 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1321 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1322 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1325 clock-output-names =
1326 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1327 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1329 mstp8_clks: mstp8_clks@e6150990 {
1330 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1331 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1332 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1333 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1336 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1337 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1338 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1340 clock-output-names =
1341 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1344 mstp9_clks: mstp9_clks@e6150994 {
1345 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1346 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1347 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1348 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1349 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1350 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1351 <&hp_clk>, <&hp_clk>;
1354 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1355 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1356 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1357 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1358 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1360 clock-output-names =
1361 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1362 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1365 mstp10_clks: mstp10_clks@e6150998 {
1366 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1367 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1369 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1370 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1372 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1373 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1374 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1375 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1376 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1377 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1378 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1383 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1384 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1386 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1387 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1388 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1389 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1391 clock-output-names =
1393 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1394 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1396 "scu-dvc1", "scu-dvc0",
1397 "scu-ctu1-mix1", "scu-ctu0-mix0",
1398 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1399 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1401 mstp11_clks: mstp11_clks@e615099c {
1402 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1403 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1404 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1407 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1409 clock-output-names = "scifa3", "scifa4", "scifa5";
1413 qspi: spi@e6b10000 {
1414 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1415 reg = <0 0xe6b10000 0 0x2c>;
1416 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1417 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1418 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1419 dma-names = "tx", "rx";
1420 power-domains = <&cpg_clocks>;
1422 #address-cells = <1>;
1424 status = "disabled";
1427 msiof0: spi@e6e20000 {
1428 compatible = "renesas,msiof-r8a7791";
1429 reg = <0 0xe6e20000 0 0x0064>;
1430 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1432 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1433 dma-names = "tx", "rx";
1434 power-domains = <&cpg_clocks>;
1435 #address-cells = <1>;
1437 status = "disabled";
1440 msiof1: spi@e6e10000 {
1441 compatible = "renesas,msiof-r8a7791";
1442 reg = <0 0xe6e10000 0 0x0064>;
1443 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1445 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1446 dma-names = "tx", "rx";
1447 power-domains = <&cpg_clocks>;
1448 #address-cells = <1>;
1450 status = "disabled";
1453 msiof2: spi@e6e00000 {
1454 compatible = "renesas,msiof-r8a7791";
1455 reg = <0 0xe6e00000 0 0x0064>;
1456 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1458 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1459 dma-names = "tx", "rx";
1460 power-domains = <&cpg_clocks>;
1461 #address-cells = <1>;
1463 status = "disabled";
1466 xhci: usb@ee000000 {
1467 compatible = "renesas,xhci-r8a7791";
1468 reg = <0 0xee000000 0 0xc00>;
1469 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1471 power-domains = <&cpg_clocks>;
1474 status = "disabled";
1477 pci0: pci@ee090000 {
1478 compatible = "renesas,pci-r8a7791";
1479 device_type = "pci";
1480 reg = <0 0xee090000 0 0xc00>,
1481 <0 0xee080000 0 0x1100>;
1482 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1483 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1484 power-domains = <&cpg_clocks>;
1485 status = "disabled";
1488 #address-cells = <3>;
1490 #interrupt-cells = <1>;
1491 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1492 interrupt-map-mask = <0xff00 0 0 0x7>;
1493 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1494 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1495 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1498 reg = <0x800 0 0 0 0>;
1499 device_type = "pci";
1505 reg = <0x1000 0 0 0 0>;
1506 device_type = "pci";
1512 pci1: pci@ee0d0000 {
1513 compatible = "renesas,pci-r8a7791";
1514 device_type = "pci";
1515 reg = <0 0xee0d0000 0 0xc00>,
1516 <0 0xee0c0000 0 0x1100>;
1517 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1518 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1519 power-domains = <&cpg_clocks>;
1520 status = "disabled";
1523 #address-cells = <3>;
1525 #interrupt-cells = <1>;
1526 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1527 interrupt-map-mask = <0xff00 0 0 0x7>;
1528 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1529 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1530 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1533 reg = <0x800 0 0 0 0>;
1534 device_type = "pci";
1540 reg = <0x1000 0 0 0 0>;
1541 device_type = "pci";
1547 pciec: pcie@fe000000 {
1548 compatible = "renesas,pcie-r8a7791";
1549 reg = <0 0xfe000000 0 0x80000>;
1550 #address-cells = <3>;
1552 bus-range = <0x00 0xff>;
1553 device_type = "pci";
1554 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1555 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1556 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1557 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1558 /* Map all possible DDR as inbound ranges */
1559 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1560 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1561 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1562 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1563 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1564 #interrupt-cells = <1>;
1565 interrupt-map-mask = <0 0 0 0>;
1566 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1567 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1568 clock-names = "pcie", "pcie_bus";
1569 power-domains = <&cpg_clocks>;
1570 status = "disabled";
1573 ipmmu_sy0: mmu@e6280000 {
1574 compatible = "renesas,ipmmu-vmsa";
1575 reg = <0 0xe6280000 0 0x1000>;
1576 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1577 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1579 status = "disabled";
1582 ipmmu_sy1: mmu@e6290000 {
1583 compatible = "renesas,ipmmu-vmsa";
1584 reg = <0 0xe6290000 0 0x1000>;
1585 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1587 status = "disabled";
1590 ipmmu_ds: mmu@e6740000 {
1591 compatible = "renesas,ipmmu-vmsa";
1592 reg = <0 0xe6740000 0 0x1000>;
1593 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1594 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1596 status = "disabled";
1599 ipmmu_mp: mmu@ec680000 {
1600 compatible = "renesas,ipmmu-vmsa";
1601 reg = <0 0xec680000 0 0x1000>;
1602 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1604 status = "disabled";
1607 ipmmu_mx: mmu@fe951000 {
1608 compatible = "renesas,ipmmu-vmsa";
1609 reg = <0 0xfe951000 0 0x1000>;
1610 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1611 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1613 status = "disabled";
1616 ipmmu_rt: mmu@ffc80000 {
1617 compatible = "renesas,ipmmu-vmsa";
1618 reg = <0 0xffc80000 0 0x1000>;
1619 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1621 status = "disabled";
1624 ipmmu_gp: mmu@e62a0000 {
1625 compatible = "renesas,ipmmu-vmsa";
1626 reg = <0 0xe62a0000 0 0x1000>;
1627 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1628 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1630 status = "disabled";
1633 rcar_sound: sound@ec500000 {
1635 * #sound-dai-cells is required
1637 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1638 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1640 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1641 reg = <0 0xec500000 0 0x1000>, /* SCU */
1642 <0 0xec5a0000 0 0x100>, /* ADG */
1643 <0 0xec540000 0 0x1000>, /* SSIU */
1644 <0 0xec541000 0 0x280>, /* SSI */
1645 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1646 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1648 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1649 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1650 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1651 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1652 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1653 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1654 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1655 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1656 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1657 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1658 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1659 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1660 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1661 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1662 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1663 clock-names = "ssi-all",
1664 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1665 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1666 "src.9", "src.8", "src.7", "src.6", "src.5",
1667 "src.4", "src.3", "src.2", "src.1", "src.0",
1671 "clk_a", "clk_b", "clk_c", "clk_i";
1673 status = "disabled";
1677 dmas = <&audma0 0xbc>;
1681 dmas = <&audma0 0xbe>;
1704 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1705 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1706 dma-names = "rx", "tx";
1709 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1710 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1711 dma-names = "rx", "tx";
1714 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1715 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1716 dma-names = "rx", "tx";
1719 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1720 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1721 dma-names = "rx", "tx";
1724 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1725 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1726 dma-names = "rx", "tx";
1729 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1730 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1731 dma-names = "rx", "tx";
1734 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1735 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1736 dma-names = "rx", "tx";
1739 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1740 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1741 dma-names = "rx", "tx";
1744 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1745 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1746 dma-names = "rx", "tx";
1749 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1750 dmas = <&audma0 0x97>, <&audma1 0xba>;
1751 dma-names = "rx", "tx";
1757 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1758 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1759 dma-names = "rx", "tx", "rxu", "txu";
1762 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1763 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1764 dma-names = "rx", "tx", "rxu", "txu";
1767 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1768 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1769 dma-names = "rx", "tx", "rxu", "txu";
1772 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1773 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1774 dma-names = "rx", "tx", "rxu", "txu";
1777 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1778 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1779 dma-names = "rx", "tx", "rxu", "txu";
1782 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1783 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1784 dma-names = "rx", "tx", "rxu", "txu";
1787 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1788 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1789 dma-names = "rx", "tx", "rxu", "txu";
1792 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1793 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1794 dma-names = "rx", "tx", "rxu", "txu";
1797 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1798 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1799 dma-names = "rx", "tx", "rxu", "txu";
1802 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1803 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1804 dma-names = "rx", "tx", "rxu", "txu";