arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37                 vin0 = &vin0;
  38                 vin1 = &vin1;
  39                 vin2 = &vin2;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0>;
  50                         clock-frequency = <1500000000>;
  51                         voltage-tolerance = <1>; /* 1% */
  52                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  53                         clock-latency = <300000>; /* 300 us */
  54
  55                         /* kHz - uV - OPPs unknown yet */
  56                         operating-points = <1500000 1000000>,
  57                                            <1312500 1000000>,
  58                                            <1125000 1000000>,
  59                                            < 937500 1000000>,
  60                                            < 750000 1000000>,
  61                                            < 375000 1000000>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <1>;
  68                         clock-frequency = <1500000000>;
  69                 };
  70         };
  71
  72         gic: interrupt-controller@f1001000 {
  73                 compatible = "arm,gic-400";
  74                 #interrupt-cells = <3>;
  75                 #address-cells = <0>;
  76                 interrupt-controller;
  77                 reg = <0 0xf1001000 0 0x1000>,
  78                         <0 0xf1002000 0 0x1000>,
  79                         <0 0xf1004000 0 0x2000>,
  80                         <0 0xf1006000 0 0x2000>;
  81                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  82         };
  83
  84         gpio0: gpio@e6050000 {
  85                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  86                 reg = <0 0xe6050000 0 0x50>;
  87                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  88                 #gpio-cells = <2>;
  89                 gpio-controller;
  90                 gpio-ranges = <&pfc 0 0 32>;
  91                 #interrupt-cells = <2>;
  92                 interrupt-controller;
  93                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
  94         };
  95
  96         gpio1: gpio@e6051000 {
  97                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  98                 reg = <0 0xe6051000 0 0x50>;
  99                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 32 32>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 106         };
 107
 108         gpio2: gpio@e6052000 {
 109                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 110                 reg = <0 0xe6052000 0 0x50>;
 111                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 64 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 118         };
 119
 120         gpio3: gpio@e6053000 {
 121                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 122                 reg = <0 0xe6053000 0 0x50>;
 123                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 124                 #gpio-cells = <2>;
 125                 gpio-controller;
 126                 gpio-ranges = <&pfc 0 96 32>;
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 142         };
 143
 144         gpio5: gpio@e6055000 {
 145                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 146                 reg = <0 0xe6055000 0 0x50>;
 147                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 160 32>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 154         };
 155
 156         gpio6: gpio@e6055400 {
 157                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 158                 reg = <0 0xe6055400 0 0x50>;
 159                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 160                 #gpio-cells = <2>;
 161                 gpio-controller;
 162                 gpio-ranges = <&pfc 0 192 32>;
 163                 #interrupt-cells = <2>;
 164                 interrupt-controller;
 165                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 166         };
 167
 168         gpio7: gpio@e6055800 {
 169                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 170                 reg = <0 0xe6055800 0 0x50>;
 171                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 172                 #gpio-cells = <2>;
 173                 gpio-controller;
 174                 gpio-ranges = <&pfc 0 224 26>;
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 178         };
 179
 180         thermal@e61f0000 {
 181                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 182                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 183                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 185         };
 186
 187         timer {
 188                 compatible = "arm,armv7-timer";
 189                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 190                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 191                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 193         };
 194
 195         cmt0: timer@ffca0000 {
 196                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 197                 reg = <0 0xffca0000 0 0x1004>;
 198                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 199                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 201                 clock-names = "fck";
 202
 203                 renesas,channels-mask = <0x60>;
 204
 205                 status = "disabled";
 206         };
 207
 208         cmt1: timer@e6130000 {
 209                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 210                 reg = <0 0xe6130000 0 0x1004>;
 211                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 212                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 213                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 214                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 215                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 216                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 217                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 218                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 220                 clock-names = "fck";
 221
 222                 renesas,channels-mask = <0xff>;
 223
 224                 status = "disabled";
 225         };
 226
 227         irqc0: interrupt-controller@e61c0000 {
 228                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 229                 #interrupt-cells = <2>;
 230                 interrupt-controller;
 231                 reg = <0 0xe61c0000 0 0x200>;
 232                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 237                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 238                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 239                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 240                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 241                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 242                 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
 243         };
 244
 245         dmac0: dma-controller@e6700000 {
 246                 compatible = "renesas,rcar-dmac";
 247                 reg = <0 0xe6700000 0 0x20000>;
 248                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 249                               0 200 IRQ_TYPE_LEVEL_HIGH
 250                               0 201 IRQ_TYPE_LEVEL_HIGH
 251                               0 202 IRQ_TYPE_LEVEL_HIGH
 252                               0 203 IRQ_TYPE_LEVEL_HIGH
 253                               0 204 IRQ_TYPE_LEVEL_HIGH
 254                               0 205 IRQ_TYPE_LEVEL_HIGH
 255                               0 206 IRQ_TYPE_LEVEL_HIGH
 256                               0 207 IRQ_TYPE_LEVEL_HIGH
 257                               0 208 IRQ_TYPE_LEVEL_HIGH
 258                               0 209 IRQ_TYPE_LEVEL_HIGH
 259                               0 210 IRQ_TYPE_LEVEL_HIGH
 260                               0 211 IRQ_TYPE_LEVEL_HIGH
 261                               0 212 IRQ_TYPE_LEVEL_HIGH
 262                               0 213 IRQ_TYPE_LEVEL_HIGH
 263                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 264                 interrupt-names = "error",
 265                                 "ch0", "ch1", "ch2", "ch3",
 266                                 "ch4", "ch5", "ch6", "ch7",
 267                                 "ch8", "ch9", "ch10", "ch11",
 268                                 "ch12", "ch13", "ch14";
 269                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 270                 clock-names = "fck";
 271                 #dma-cells = <1>;
 272                 dma-channels = <15>;
 273         };
 274
 275         dmac1: dma-controller@e6720000 {
 276                 compatible = "renesas,rcar-dmac";
 277                 reg = <0 0xe6720000 0 0x20000>;
 278                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 279                               0 216 IRQ_TYPE_LEVEL_HIGH
 280                               0 217 IRQ_TYPE_LEVEL_HIGH
 281                               0 218 IRQ_TYPE_LEVEL_HIGH
 282                               0 219 IRQ_TYPE_LEVEL_HIGH
 283                               0 308 IRQ_TYPE_LEVEL_HIGH
 284                               0 309 IRQ_TYPE_LEVEL_HIGH
 285                               0 310 IRQ_TYPE_LEVEL_HIGH
 286                               0 311 IRQ_TYPE_LEVEL_HIGH
 287                               0 312 IRQ_TYPE_LEVEL_HIGH
 288                               0 313 IRQ_TYPE_LEVEL_HIGH
 289                               0 314 IRQ_TYPE_LEVEL_HIGH
 290                               0 315 IRQ_TYPE_LEVEL_HIGH
 291                               0 316 IRQ_TYPE_LEVEL_HIGH
 292                               0 317 IRQ_TYPE_LEVEL_HIGH
 293                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 294                 interrupt-names = "error",
 295                                 "ch0", "ch1", "ch2", "ch3",
 296                                 "ch4", "ch5", "ch6", "ch7",
 297                                 "ch8", "ch9", "ch10", "ch11",
 298                                 "ch12", "ch13", "ch14";
 299                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 300                 clock-names = "fck";
 301                 #dma-cells = <1>;
 302                 dma-channels = <15>;
 303         };
 304
 305         audma0: dma-controller@ec700000 {
 306                 compatible = "renesas,rcar-dmac";
 307                 reg = <0 0xec700000 0 0x10000>;
 308                 interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
 309                                  0 320 IRQ_TYPE_LEVEL_HIGH
 310                                  0 321 IRQ_TYPE_LEVEL_HIGH
 311                                  0 322 IRQ_TYPE_LEVEL_HIGH
 312                                  0 323 IRQ_TYPE_LEVEL_HIGH
 313                                  0 324 IRQ_TYPE_LEVEL_HIGH
 314                                  0 325 IRQ_TYPE_LEVEL_HIGH
 315                                  0 326 IRQ_TYPE_LEVEL_HIGH
 316                                  0 327 IRQ_TYPE_LEVEL_HIGH
 317                                  0 328 IRQ_TYPE_LEVEL_HIGH
 318                                  0 329 IRQ_TYPE_LEVEL_HIGH
 319                                  0 330 IRQ_TYPE_LEVEL_HIGH
 320                                  0 331 IRQ_TYPE_LEVEL_HIGH
 321                                  0 332 IRQ_TYPE_LEVEL_HIGH>;
 322                 interrupt-names = "error",
 323                                 "ch0", "ch1", "ch2", "ch3",
 324                                 "ch4", "ch5", "ch6", "ch7",
 325                                 "ch8", "ch9", "ch10", "ch11",
 326                                 "ch12";
 327                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 328                 clock-names = "fck";
 329                 #dma-cells = <1>;
 330                 dma-channels = <13>;
 331         };
 332
 333         audma1: dma-controller@ec720000 {
 334                 compatible = "renesas,rcar-dmac";
 335                 reg = <0 0xec720000 0 0x10000>;
 336                 interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
 337                                  0 333 IRQ_TYPE_LEVEL_HIGH
 338                                  0 334 IRQ_TYPE_LEVEL_HIGH
 339                                  0 335 IRQ_TYPE_LEVEL_HIGH
 340                                  0 336 IRQ_TYPE_LEVEL_HIGH
 341                                  0 337 IRQ_TYPE_LEVEL_HIGH
 342                                  0 338 IRQ_TYPE_LEVEL_HIGH
 343                                  0 339 IRQ_TYPE_LEVEL_HIGH
 344                                  0 340 IRQ_TYPE_LEVEL_HIGH
 345                                  0 341 IRQ_TYPE_LEVEL_HIGH
 346                                  0 342 IRQ_TYPE_LEVEL_HIGH
 347                                  0 343 IRQ_TYPE_LEVEL_HIGH
 348                                  0 344 IRQ_TYPE_LEVEL_HIGH
 349                                  0 345 IRQ_TYPE_LEVEL_HIGH>;
 350                 interrupt-names = "error",
 351                                 "ch0", "ch1", "ch2", "ch3",
 352                                 "ch4", "ch5", "ch6", "ch7",
 353                                 "ch8", "ch9", "ch10", "ch11",
 354                                 "ch12";
 355                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 356                 clock-names = "fck";
 357                 #dma-cells = <1>;
 358                 dma-channels = <13>;
 359         };
 360
 361         usb_dmac0: dma-controller@e65a0000 {
 362                 compatible = "renesas,usb-dmac";
 363                 reg = <0 0xe65a0000 0 0x100>;
 364                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
 365                               0 109 IRQ_TYPE_LEVEL_HIGH>;
 366                 interrupt-names = "ch0", "ch1";
 367                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
 368                 #dma-cells = <1>;
 369                 dma-channels = <2>;
 370         };
 371
 372         usb_dmac1: dma-controller@e65b0000 {
 373                 compatible = "renesas,usb-dmac";
 374                 reg = <0 0xe65b0000 0 0x100>;
 375                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
 376                               0 110 IRQ_TYPE_LEVEL_HIGH>;
 377                 interrupt-names = "ch0", "ch1";
 378                 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
 379                 #dma-cells = <1>;
 380                 dma-channels = <2>;
 381         };
 382
 383         /* The memory map in the User's Manual maps the cores to bus numbers */
 384         i2c0: i2c@e6508000 {
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 compatible = "renesas,i2c-r8a7791";
 388                 reg = <0 0xe6508000 0 0x40>;
 389                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 391                 status = "disabled";
 392         };
 393
 394         i2c1: i2c@e6518000 {
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 compatible = "renesas,i2c-r8a7791";
 398                 reg = <0 0xe6518000 0 0x40>;
 399                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 401                 status = "disabled";
 402         };
 403
 404         i2c2: i2c@e6530000 {
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 compatible = "renesas,i2c-r8a7791";
 408                 reg = <0 0xe6530000 0 0x40>;
 409                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 410                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 411                 status = "disabled";
 412         };
 413
 414         i2c3: i2c@e6540000 {
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 compatible = "renesas,i2c-r8a7791";
 418                 reg = <0 0xe6540000 0 0x40>;
 419                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 421                 status = "disabled";
 422         };
 423
 424         i2c4: i2c@e6520000 {
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 compatible = "renesas,i2c-r8a7791";
 428                 reg = <0 0xe6520000 0 0x40>;
 429                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 431                 status = "disabled";
 432         };
 433
 434         i2c5: i2c@e6528000 {
 435                 /* doesn't need pinmux */
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 compatible = "renesas,i2c-r8a7791";
 439                 reg = <0 0xe6528000 0 0x40>;
 440                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 442                 status = "disabled";
 443         };
 444
 445         i2c6: i2c@e60b0000 {
 446                 /* doesn't need pinmux */
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 450                 reg = <0 0xe60b0000 0 0x425>;
 451                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 453                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 454                 dma-names = "tx", "rx";
 455                 status = "disabled";
 456         };
 457
 458         i2c7: i2c@e6500000 {
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 462                 reg = <0 0xe6500000 0 0x425>;
 463                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 465                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 466                 dma-names = "tx", "rx";
 467                 status = "disabled";
 468         };
 469
 470         i2c8: i2c@e6510000 {
 471                 #address-cells = <1>;
 472                 #size-cells = <0>;
 473                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 474                 reg = <0 0xe6510000 0 0x425>;
 475                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 477                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 478                 dma-names = "tx", "rx";
 479                 status = "disabled";
 480         };
 481
 482         pfc: pfc@e6060000 {
 483                 compatible = "renesas,pfc-r8a7791";
 484                 reg = <0 0xe6060000 0 0x250>;
 485                 #gpio-range-cells = <3>;
 486         };
 487
 488         mmcif0: mmc@ee200000 {
 489                 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 490                 reg = <0 0xee200000 0 0x80>;
 491                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 492                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 493                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 494                 dma-names = "tx", "rx";
 495                 reg-io-width = <4>;
 496                 status = "disabled";
 497                 max-frequency = <97500000>;
 498         };
 499
 500         sdhi0: sd@ee100000 {
 501                 compatible = "renesas,sdhi-r8a7791";
 502                 reg = <0 0xee100000 0 0x328>;
 503                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 505                 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 506                 dma-names = "tx", "rx";
 507                 status = "disabled";
 508         };
 509
 510         sdhi1: sd@ee140000 {
 511                 compatible = "renesas,sdhi-r8a7791";
 512                 reg = <0 0xee140000 0 0x100>;
 513                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 514                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 515                 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 516                 dma-names = "tx", "rx";
 517                 status = "disabled";
 518         };
 519
 520         sdhi2: sd@ee160000 {
 521                 compatible = "renesas,sdhi-r8a7791";
 522                 reg = <0 0xee160000 0 0x100>;
 523                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 525                 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 526                 dma-names = "tx", "rx";
 527                 status = "disabled";
 528         };
 529
 530         scifa0: serial@e6c40000 {
 531                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 532                 reg = <0 0xe6c40000 0 64>;
 533                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 534                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 535                 clock-names = "sci_ick";
 536                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 537                 dma-names = "tx", "rx";
 538                 status = "disabled";
 539         };
 540
 541         scifa1: serial@e6c50000 {
 542                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 543                 reg = <0 0xe6c50000 0 64>;
 544                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 546                 clock-names = "sci_ick";
 547                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 548                 dma-names = "tx", "rx";
 549                 status = "disabled";
 550         };
 551
 552         scifa2: serial@e6c60000 {
 553                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 554                 reg = <0 0xe6c60000 0 64>;
 555                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 556                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 557                 clock-names = "sci_ick";
 558                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 559                 dma-names = "tx", "rx";
 560                 status = "disabled";
 561         };
 562
 563         scifa3: serial@e6c70000 {
 564                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 565                 reg = <0 0xe6c70000 0 64>;
 566                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 568                 clock-names = "sci_ick";
 569                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 570                 dma-names = "tx", "rx";
 571                 status = "disabled";
 572         };
 573
 574         scifa4: serial@e6c78000 {
 575                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 576                 reg = <0 0xe6c78000 0 64>;
 577                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 579                 clock-names = "sci_ick";
 580                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 581                 dma-names = "tx", "rx";
 582                 status = "disabled";
 583         };
 584
 585         scifa5: serial@e6c80000 {
 586                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 587                 reg = <0 0xe6c80000 0 64>;
 588                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 589                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 590                 clock-names = "sci_ick";
 591                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 592                 dma-names = "tx", "rx";
 593                 status = "disabled";
 594         };
 595
 596         scifb0: serial@e6c20000 {
 597                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 598                 reg = <0 0xe6c20000 0 64>;
 599                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 601                 clock-names = "sci_ick";
 602                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 603                 dma-names = "tx", "rx";
 604                 status = "disabled";
 605         };
 606
 607         scifb1: serial@e6c30000 {
 608                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 609                 reg = <0 0xe6c30000 0 64>;
 610                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 612                 clock-names = "sci_ick";
 613                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 614                 dma-names = "tx", "rx";
 615                 status = "disabled";
 616         };
 617
 618         scifb2: serial@e6ce0000 {
 619                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 620                 reg = <0 0xe6ce0000 0 64>;
 621                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 622                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 623                 clock-names = "sci_ick";
 624                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 625                 dma-names = "tx", "rx";
 626                 status = "disabled";
 627         };
 628
 629         scif0: serial@e6e60000 {
 630                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 631                 reg = <0 0xe6e60000 0 64>;
 632                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 633                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 634                 clock-names = "sci_ick";
 635                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 636                 dma-names = "tx", "rx";
 637                 status = "disabled";
 638         };
 639
 640         scif1: serial@e6e68000 {
 641                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 642                 reg = <0 0xe6e68000 0 64>;
 643                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 644                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 645                 clock-names = "sci_ick";
 646                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 647                 dma-names = "tx", "rx";
 648                 status = "disabled";
 649         };
 650
 651         scif2: serial@e6e58000 {
 652                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 653                 reg = <0 0xe6e58000 0 64>;
 654                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 656                 clock-names = "sci_ick";
 657                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 658                 dma-names = "tx", "rx";
 659                 status = "disabled";
 660         };
 661
 662         scif3: serial@e6ea8000 {
 663                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 664                 reg = <0 0xe6ea8000 0 64>;
 665                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 667                 clock-names = "sci_ick";
 668                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 669                 dma-names = "tx", "rx";
 670                 status = "disabled";
 671         };
 672
 673         scif4: serial@e6ee0000 {
 674                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 675                 reg = <0 0xe6ee0000 0 64>;
 676                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 677                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 678                 clock-names = "sci_ick";
 679                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 680                 dma-names = "tx", "rx";
 681                 status = "disabled";
 682         };
 683
 684         scif5: serial@e6ee8000 {
 685                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 686                 reg = <0 0xe6ee8000 0 64>;
 687                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 689                 clock-names = "sci_ick";
 690                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 691                 dma-names = "tx", "rx";
 692                 status = "disabled";
 693         };
 694
 695         hscif0: serial@e62c0000 {
 696                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 697                 reg = <0 0xe62c0000 0 96>;
 698                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 699                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 700                 clock-names = "sci_ick";
 701                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 702                 dma-names = "tx", "rx";
 703                 status = "disabled";
 704         };
 705
 706         hscif1: serial@e62c8000 {
 707                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 708                 reg = <0 0xe62c8000 0 96>;
 709                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 710                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 711                 clock-names = "sci_ick";
 712                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 713                 dma-names = "tx", "rx";
 714                 status = "disabled";
 715         };
 716
 717         hscif2: serial@e62d0000 {
 718                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 719                 reg = <0 0xe62d0000 0 96>;
 720                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 722                 clock-names = "sci_ick";
 723                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 724                 dma-names = "tx", "rx";
 725                 status = "disabled";
 726         };
 727
 728         ether: ethernet@ee700000 {
 729                 compatible = "renesas,ether-r8a7791";
 730                 reg = <0 0xee700000 0 0x400>;
 731                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 733                 phy-mode = "rmii";
 734                 #address-cells = <1>;
 735                 #size-cells = <0>;
 736                 status = "disabled";
 737         };
 738
 739         sata0: sata@ee300000 {
 740                 compatible = "renesas,sata-r8a7791";
 741                 reg = <0 0xee300000 0 0x2000>;
 742                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 743                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 744                 status = "disabled";
 745         };
 746
 747         sata1: sata@ee500000 {
 748                 compatible = "renesas,sata-r8a7791";
 749                 reg = <0 0xee500000 0 0x2000>;
 750                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 751                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 752                 status = "disabled";
 753         };
 754
 755         hsusb: usb@e6590000 {
 756                 compatible = "renesas,usbhs-r8a7791";
 757                 reg = <0 0xe6590000 0 0x100>;
 758                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 759                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 760                 renesas,buswait = <4>;
 761                 phys = <&usb0 1>;
 762                 phy-names = "usb";
 763                 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 764                        <&usb_dmac1 0>, <&usb_dmac1 1>;
 765                 dma-names = "ch0", "ch1", "ch2", "ch3";
 766                 status = "disabled";
 767         };
 768
 769         usbphy: usb-phy@e6590100 {
 770                 compatible = "renesas,usb-phy-r8a7791";
 771                 reg = <0 0xe6590100 0 0x100>;
 772                 #address-cells = <1>;
 773                 #size-cells = <0>;
 774                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 775                 clock-names = "usbhs";
 776                 status = "disabled";
 777
 778                 usb0: usb-channel@0 {
 779                         reg = <0>;
 780                         #phy-cells = <1>;
 781                 };
 782                 usb2: usb-channel@2 {
 783                         reg = <2>;
 784                         #phy-cells = <1>;
 785                 };
 786         };
 787
 788         vin0: video@e6ef0000 {
 789                 compatible = "renesas,vin-r8a7791";
 790                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 791                 reg = <0 0xe6ef0000 0 0x1000>;
 792                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 793                 status = "disabled";
 794         };
 795
 796         vin1: video@e6ef1000 {
 797                 compatible = "renesas,vin-r8a7791";
 798                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 799                 reg = <0 0xe6ef1000 0 0x1000>;
 800                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 801                 status = "disabled";
 802         };
 803
 804         vin2: video@e6ef2000 {
 805                 compatible = "renesas,vin-r8a7791";
 806                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 807                 reg = <0 0xe6ef2000 0 0x1000>;
 808                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 809                 status = "disabled";
 810         };
 811
 812         vsp1@fe928000 {
 813                 compatible = "renesas,vsp1";
 814                 reg = <0 0xfe928000 0 0x8000>;
 815                 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 816                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
 817
 818                 renesas,has-lut;
 819                 renesas,has-sru;
 820                 renesas,#rpf = <5>;
 821                 renesas,#uds = <3>;
 822                 renesas,#wpf = <4>;
 823         };
 824
 825         vsp1@fe930000 {
 826                 compatible = "renesas,vsp1";
 827                 reg = <0 0xfe930000 0 0x8000>;
 828                 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 829                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
 830
 831                 renesas,has-lif;
 832                 renesas,has-lut;
 833                 renesas,#rpf = <4>;
 834                 renesas,#uds = <1>;
 835                 renesas,#wpf = <4>;
 836         };
 837
 838         vsp1@fe938000 {
 839                 compatible = "renesas,vsp1";
 840                 reg = <0 0xfe938000 0 0x8000>;
 841                 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 842                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
 843
 844                 renesas,has-lif;
 845                 renesas,has-lut;
 846                 renesas,#rpf = <4>;
 847                 renesas,#uds = <1>;
 848                 renesas,#wpf = <4>;
 849         };
 850
 851         du: display@feb00000 {
 852                 compatible = "renesas,du-r8a7791";
 853                 reg = <0 0xfeb00000 0 0x40000>,
 854                       <0 0xfeb90000 0 0x1c>;
 855                 reg-names = "du", "lvds.0";
 856                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 857                              <0 268 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
 859                          <&mstp7_clks R8A7791_CLK_DU1>,
 860                          <&mstp7_clks R8A7791_CLK_LVDS0>;
 861                 clock-names = "du.0", "du.1", "lvds.0";
 862                 status = "disabled";
 863
 864                 ports {
 865                         #address-cells = <1>;
 866                         #size-cells = <0>;
 867
 868                         port@0 {
 869                                 reg = <0>;
 870                                 du_out_rgb: endpoint {
 871                                 };
 872                         };
 873                         port@1 {
 874                                 reg = <1>;
 875                                 du_out_lvds0: endpoint {
 876                                 };
 877                         };
 878                 };
 879         };
 880
 881         can0: can@e6e80000 {
 882                 compatible = "renesas,can-r8a7791";
 883                 reg = <0 0xe6e80000 0 0x1000>;
 884                 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
 885                 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
 886                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 887                 clock-names = "clkp1", "clkp2", "can_clk";
 888                 status = "disabled";
 889         };
 890
 891         can1: can@e6e88000 {
 892                 compatible = "renesas,can-r8a7791";
 893                 reg = <0 0xe6e88000 0 0x1000>;
 894                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
 895                 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
 896                          <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 897                 clock-names = "clkp1", "clkp2", "can_clk";
 898                 status = "disabled";
 899         };
 900
 901         jpu: jpeg-codec@fe980000 {
 902                 compatible = "renesas,jpu-r8a7791";
 903                 reg = <0 0xfe980000 0 0x10300>;
 904                 interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
 905                 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
 906         };
 907
 908         clocks {
 909                 #address-cells = <2>;
 910                 #size-cells = <2>;
 911                 ranges;
 912
 913                 /* External root clock */
 914                 extal_clk: extal_clk {
 915                         compatible = "fixed-clock";
 916                         #clock-cells = <0>;
 917                         /* This value must be overriden by the board. */
 918                         clock-frequency = <0>;
 919                         clock-output-names = "extal";
 920                 };
 921
 922                 /*
 923                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 924                  * default. Boards that provide audio clocks should override them.
 925                  */
 926                 audio_clk_a: audio_clk_a {
 927                         compatible = "fixed-clock";
 928                         #clock-cells = <0>;
 929                         clock-frequency = <0>;
 930                         clock-output-names = "audio_clk_a";
 931                 };
 932                 audio_clk_b: audio_clk_b {
 933                         compatible = "fixed-clock";
 934                         #clock-cells = <0>;
 935                         clock-frequency = <0>;
 936                         clock-output-names = "audio_clk_b";
 937                 };
 938                 audio_clk_c: audio_clk_c {
 939                         compatible = "fixed-clock";
 940                         #clock-cells = <0>;
 941                         clock-frequency = <0>;
 942                         clock-output-names = "audio_clk_c";
 943                 };
 944
 945                 /* External PCIe clock - can be overridden by the board */
 946                 pcie_bus_clk: pcie_bus_clk {
 947                         compatible = "fixed-clock";
 948                         #clock-cells = <0>;
 949                         clock-frequency = <100000000>;
 950                         clock-output-names = "pcie_bus";
 951                         status = "disabled";
 952                 };
 953
 954                 /* External USB clock - can be overridden by the board */
 955                 usb_extal_clk: usb_extal_clk {
 956                         compatible = "fixed-clock";
 957                         #clock-cells = <0>;
 958                         clock-frequency = <48000000>;
 959                         clock-output-names = "usb_extal";
 960                 };
 961
 962                 /* External CAN clock */
 963                 can_clk: can_clk {
 964                         compatible = "fixed-clock";
 965                         #clock-cells = <0>;
 966                         /* This value must be overridden by the board. */
 967                         clock-frequency = <0>;
 968                         clock-output-names = "can_clk";
 969                         status = "disabled";
 970                 };
 971
 972                 /* Special CPG clocks */
 973                 cpg_clocks: cpg_clocks@e6150000 {
 974                         compatible = "renesas,r8a7791-cpg-clocks",
 975                                      "renesas,rcar-gen2-cpg-clocks";
 976                         reg = <0 0xe6150000 0 0x1000>;
 977                         clocks = <&extal_clk &usb_extal_clk>;
 978                         #clock-cells = <1>;
 979                         clock-output-names = "main", "pll0", "pll1", "pll3",
 980                                              "lb", "qspi", "sdh", "sd0", "z",
 981                                              "rcan", "adsp";
 982                 };
 983
 984                 /* Variable factor clocks */
 985                 sd2_clk: sd2_clk@e6150078 {
 986                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 987                         reg = <0 0xe6150078 0 4>;
 988                         clocks = <&pll1_div2_clk>;
 989                         #clock-cells = <0>;
 990                         clock-output-names = "sd2";
 991                 };
 992                 sd3_clk: sd3_clk@e615026c {
 993                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 994                         reg = <0 0xe615026c 0 4>;
 995                         clocks = <&pll1_div2_clk>;
 996                         #clock-cells = <0>;
 997                         clock-output-names = "sd3";
 998                 };
 999                 mmc0_clk: mmc0_clk@e6150240 {
1000                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1001                         reg = <0 0xe6150240 0 4>;
1002                         clocks = <&pll1_div2_clk>;
1003                         #clock-cells = <0>;
1004                         clock-output-names = "mmc0";
1005                 };
1006                 ssp_clk: ssp_clk@e6150248 {
1007                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1008                         reg = <0 0xe6150248 0 4>;
1009                         clocks = <&pll1_div2_clk>;
1010                         #clock-cells = <0>;
1011                         clock-output-names = "ssp";
1012                 };
1013                 ssprs_clk: ssprs_clk@e615024c {
1014                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1015                         reg = <0 0xe615024c 0 4>;
1016                         clocks = <&pll1_div2_clk>;
1017                         #clock-cells = <0>;
1018                         clock-output-names = "ssprs";
1019                 };
1020
1021                 /* Fixed factor clocks */
1022                 pll1_div2_clk: pll1_div2_clk {
1023                         compatible = "fixed-factor-clock";
1024                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1025                         #clock-cells = <0>;
1026                         clock-div = <2>;
1027                         clock-mult = <1>;
1028                         clock-output-names = "pll1_div2";
1029                 };
1030                 zg_clk: zg_clk {
1031                         compatible = "fixed-factor-clock";
1032                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1033                         #clock-cells = <0>;
1034                         clock-div = <3>;
1035                         clock-mult = <1>;
1036                         clock-output-names = "zg";
1037                 };
1038                 zx_clk: zx_clk {
1039                         compatible = "fixed-factor-clock";
1040                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1041                         #clock-cells = <0>;
1042                         clock-div = <3>;
1043                         clock-mult = <1>;
1044                         clock-output-names = "zx";
1045                 };
1046                 zs_clk: zs_clk {
1047                         compatible = "fixed-factor-clock";
1048                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1049                         #clock-cells = <0>;
1050                         clock-div = <6>;
1051                         clock-mult = <1>;
1052                         clock-output-names = "zs";
1053                 };
1054                 hp_clk: hp_clk {
1055                         compatible = "fixed-factor-clock";
1056                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1057                         #clock-cells = <0>;
1058                         clock-div = <12>;
1059                         clock-mult = <1>;
1060                         clock-output-names = "hp";
1061                 };
1062                 i_clk: i_clk {
1063                         compatible = "fixed-factor-clock";
1064                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1065                         #clock-cells = <0>;
1066                         clock-div = <2>;
1067                         clock-mult = <1>;
1068                         clock-output-names = "i";
1069                 };
1070                 b_clk: b_clk {
1071                         compatible = "fixed-factor-clock";
1072                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1073                         #clock-cells = <0>;
1074                         clock-div = <12>;
1075                         clock-mult = <1>;
1076                         clock-output-names = "b";
1077                 };
1078                 p_clk: p_clk {
1079                         compatible = "fixed-factor-clock";
1080                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1081                         #clock-cells = <0>;
1082                         clock-div = <24>;
1083                         clock-mult = <1>;
1084                         clock-output-names = "p";
1085                 };
1086                 cl_clk: cl_clk {
1087                         compatible = "fixed-factor-clock";
1088                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1089                         #clock-cells = <0>;
1090                         clock-div = <48>;
1091                         clock-mult = <1>;
1092                         clock-output-names = "cl";
1093                 };
1094                 m2_clk: m2_clk {
1095                         compatible = "fixed-factor-clock";
1096                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1097                         #clock-cells = <0>;
1098                         clock-div = <8>;
1099                         clock-mult = <1>;
1100                         clock-output-names = "m2";
1101                 };
1102                 imp_clk: imp_clk {
1103                         compatible = "fixed-factor-clock";
1104                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1105                         #clock-cells = <0>;
1106                         clock-div = <4>;
1107                         clock-mult = <1>;
1108                         clock-output-names = "imp";
1109                 };
1110                 rclk_clk: rclk_clk {
1111                         compatible = "fixed-factor-clock";
1112                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1113                         #clock-cells = <0>;
1114                         clock-div = <(48 * 1024)>;
1115                         clock-mult = <1>;
1116                         clock-output-names = "rclk";
1117                 };
1118                 oscclk_clk: oscclk_clk {
1119                         compatible = "fixed-factor-clock";
1120                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1121                         #clock-cells = <0>;
1122                         clock-div = <(12 * 1024)>;
1123                         clock-mult = <1>;
1124                         clock-output-names = "oscclk";
1125                 };
1126                 zb3_clk: zb3_clk {
1127                         compatible = "fixed-factor-clock";
1128                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1129                         #clock-cells = <0>;
1130                         clock-div = <4>;
1131                         clock-mult = <1>;
1132                         clock-output-names = "zb3";
1133                 };
1134                 zb3d2_clk: zb3d2_clk {
1135                         compatible = "fixed-factor-clock";
1136                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1137                         #clock-cells = <0>;
1138                         clock-div = <8>;
1139                         clock-mult = <1>;
1140                         clock-output-names = "zb3d2";
1141                 };
1142                 ddr_clk: ddr_clk {
1143                         compatible = "fixed-factor-clock";
1144                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1145                         #clock-cells = <0>;
1146                         clock-div = <8>;
1147                         clock-mult = <1>;
1148                         clock-output-names = "ddr";
1149                 };
1150                 mp_clk: mp_clk {
1151                         compatible = "fixed-factor-clock";
1152                         clocks = <&pll1_div2_clk>;
1153                         #clock-cells = <0>;
1154                         clock-div = <15>;
1155                         clock-mult = <1>;
1156                         clock-output-names = "mp";
1157                 };
1158                 cp_clk: cp_clk {
1159                         compatible = "fixed-factor-clock";
1160                         clocks = <&extal_clk>;
1161                         #clock-cells = <0>;
1162                         clock-div = <2>;
1163                         clock-mult = <1>;
1164                         clock-output-names = "cp";
1165                 };
1166
1167                 /* Gate clocks */
1168                 mstp0_clks: mstp0_clks@e6150130 {
1169                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1170                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1171                         clocks = <&mp_clk>;
1172                         #clock-cells = <1>;
1173                         clock-indices = <R8A7791_CLK_MSIOF0>;
1174                         clock-output-names = "msiof0";
1175                 };
1176                 mstp1_clks: mstp1_clks@e6150134 {
1177                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1178                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1179                         clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1180                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1181                                  <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1182                                  <&zs_clk>;
1183                         #clock-cells = <1>;
1184                         clock-indices = <
1185                                 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1186                                 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1187                                 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1188                                 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1189                                 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1190                                 R8A7791_CLK_VSP1_S
1191                         >;
1192                         clock-output-names =
1193                                 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1194                                 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1195                                 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1196                 };
1197                 mstp2_clks: mstp2_clks@e6150138 {
1198                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1199                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1200                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1201                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1202                                  <&zs_clk>, <&zs_clk>;
1203                         #clock-cells = <1>;
1204                         clock-indices = <
1205                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1206                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1207                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1208                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1209                         >;
1210                         clock-output-names =
1211                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1212                                 "scifb1", "msiof1", "scifb2",
1213                                 "sys-dmac1", "sys-dmac0";
1214                 };
1215                 mstp3_clks: mstp3_clks@e615013c {
1216                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1217                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1218                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1219                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1220                                  <&hp_clk>, <&hp_clk>;
1221                         #clock-cells = <1>;
1222                         clock-indices = <
1223                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1224                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1225                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1226                                 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1227                         >;
1228                         clock-output-names =
1229                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1230                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1231                                 "usbdmac0", "usbdmac1";
1232                 };
1233                 mstp4_clks: mstp4_clks@e6150140 {
1234                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1235                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1236                         clocks = <&cp_clk>;
1237                         #clock-cells = <1>;
1238                         clock-indices = <R8A7791_CLK_IRQC>;
1239                         clock-output-names = "irqc";
1240                 };
1241                 mstp5_clks: mstp5_clks@e6150144 {
1242                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1243                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1244                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1245                                  <&extal_clk>, <&p_clk>;
1246                         #clock-cells = <1>;
1247                         clock-indices = <
1248                                 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1249                                 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1250                                 R8A7791_CLK_PWM
1251                         >;
1252                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1253                                              "thermal", "pwm";
1254                 };
1255                 mstp7_clks: mstp7_clks@e615014c {
1256                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1257                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1258                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1259                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1260                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
1261                         #clock-cells = <1>;
1262                         clock-indices = <
1263                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1264                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1265                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1266                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1267                                 R8A7791_CLK_LVDS0
1268                         >;
1269                         clock-output-names =
1270                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1271                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1272                 };
1273                 mstp8_clks: mstp8_clks@e6150990 {
1274                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1275                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1276                         clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1277                                  <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1278                         #clock-cells = <1>;
1279                         clock-indices = <
1280                                 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1281                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1282                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1283                         >;
1284                         clock-output-names =
1285                                 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1286                                 "sata1", "sata0";
1287                 };
1288                 mstp9_clks: mstp9_clks@e6150994 {
1289                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1290                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1291                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1292                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1293                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1294                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1295                                  <&hp_clk>, <&hp_clk>;
1296                         #clock-cells = <1>;
1297                         clock-indices = <
1298                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1299                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1300                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1301                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1302                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1303                         >;
1304                         clock-output-names =
1305                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1306                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1307                                 "i2c1", "i2c0";
1308                 };
1309                 mstp10_clks: mstp10_clks@e6150998 {
1310                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1311                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1312                         clocks = <&p_clk>,
1313                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1314                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1315                                 <&p_clk>,
1316                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1317                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1318                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1319                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1320                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1321                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1322                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1323
1324                         #clock-cells = <1>;
1325                         clock-indices = <
1326                                 R8A7791_CLK_SSI_ALL
1327                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1328                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1329                                 R8A7791_CLK_SCU_ALL
1330                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1331                                 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1332                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1333                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1334                         >;
1335                         clock-output-names =
1336                                 "ssi-all",
1337                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1338                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1339                                 "scu-all",
1340                                 "scu-dvc1", "scu-dvc0",
1341                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1342                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1343                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1344                 };
1345                 mstp11_clks: mstp11_clks@e615099c {
1346                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1347                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1348                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1349                         #clock-cells = <1>;
1350                         clock-indices = <
1351                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1352                         >;
1353                         clock-output-names = "scifa3", "scifa4", "scifa5";
1354                 };
1355         };
1356
1357         qspi: spi@e6b10000 {
1358                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1359                 reg = <0 0xe6b10000 0 0x2c>;
1360                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1361                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1362                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1363                 dma-names = "tx", "rx";
1364                 num-cs = <1>;
1365                 #address-cells = <1>;
1366                 #size-cells = <0>;
1367                 status = "disabled";
1368         };
1369
1370         msiof0: spi@e6e20000 {
1371                 compatible = "renesas,msiof-r8a7791";
1372                 reg = <0 0xe6e20000 0 0x0064>;
1373                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1374                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1375                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1376                 dma-names = "tx", "rx";
1377                 #address-cells = <1>;
1378                 #size-cells = <0>;
1379                 status = "disabled";
1380         };
1381
1382         msiof1: spi@e6e10000 {
1383                 compatible = "renesas,msiof-r8a7791";
1384                 reg = <0 0xe6e10000 0 0x0064>;
1385                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1386                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1387                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1388                 dma-names = "tx", "rx";
1389                 #address-cells = <1>;
1390                 #size-cells = <0>;
1391                 status = "disabled";
1392         };
1393
1394         msiof2: spi@e6e00000 {
1395                 compatible = "renesas,msiof-r8a7791";
1396                 reg = <0 0xe6e00000 0 0x0064>;
1397                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1398                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1399                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1400                 dma-names = "tx", "rx";
1401                 #address-cells = <1>;
1402                 #size-cells = <0>;
1403                 status = "disabled";
1404         };
1405
1406         xhci: usb@ee000000 {
1407                 compatible = "renesas,xhci-r8a7791";
1408                 reg = <0 0xee000000 0 0xc00>;
1409                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1410                 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1411                 phys = <&usb2 1>;
1412                 phy-names = "usb";
1413                 status = "disabled";
1414         };
1415
1416         pci0: pci@ee090000 {
1417                 compatible = "renesas,pci-r8a7791";
1418                 device_type = "pci";
1419                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1420                 reg = <0 0xee090000 0 0xc00>,
1421                       <0 0xee080000 0 0x1100>;
1422                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1423                 status = "disabled";
1424
1425                 bus-range = <0 0>;
1426                 #address-cells = <3>;
1427                 #size-cells = <2>;
1428                 #interrupt-cells = <1>;
1429                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1430                 interrupt-map-mask = <0xff00 0 0 0x7>;
1431                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1432                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1433                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1434
1435                 usb@0,1 {
1436                         reg = <0x800 0 0 0 0>;
1437                         device_type = "pci";
1438                         phys = <&usb0 0>;
1439                         phy-names = "usb";
1440                 };
1441
1442                 usb@0,2 {
1443                         reg = <0x1000 0 0 0 0>;
1444                         device_type = "pci";
1445                         phys = <&usb0 0>;
1446                         phy-names = "usb";
1447                 };
1448         };
1449
1450         pci1: pci@ee0d0000 {
1451                 compatible = "renesas,pci-r8a7791";
1452                 device_type = "pci";
1453                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1454                 reg = <0 0xee0d0000 0 0xc00>,
1455                       <0 0xee0c0000 0 0x1100>;
1456                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1457                 status = "disabled";
1458
1459                 bus-range = <1 1>;
1460                 #address-cells = <3>;
1461                 #size-cells = <2>;
1462                 #interrupt-cells = <1>;
1463                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1464                 interrupt-map-mask = <0xff00 0 0 0x7>;
1465                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1466                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1467                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1468
1469                 usb@0,1 {
1470                         reg = <0x800 0 0 0 0>;
1471                         device_type = "pci";
1472                         phys = <&usb2 0>;
1473                         phy-names = "usb";
1474                 };
1475
1476                 usb@0,2 {
1477                         reg = <0x1000 0 0 0 0>;
1478                         device_type = "pci";
1479                         phys = <&usb2 0>;
1480                         phy-names = "usb";
1481                 };
1482         };
1483
1484         pciec: pcie@fe000000 {
1485                 compatible = "renesas,pcie-r8a7791";
1486                 reg = <0 0xfe000000 0 0x80000>;
1487                 #address-cells = <3>;
1488                 #size-cells = <2>;
1489                 bus-range = <0x00 0xff>;
1490                 device_type = "pci";
1491                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1492                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1493                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1494                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1495                 /* Map all possible DDR as inbound ranges */
1496                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1497                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1498                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1499                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1500                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1501                 #interrupt-cells = <1>;
1502                 interrupt-map-mask = <0 0 0 0>;
1503                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1504                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1505                 clock-names = "pcie", "pcie_bus";
1506                 status = "disabled";
1507         };
1508
1509         ipmmu_sy0: mmu@e6280000 {
1510                 compatible = "renesas,ipmmu-vmsa";
1511                 reg = <0 0xe6280000 0 0x1000>;
1512                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1513                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
1514                 #iommu-cells = <1>;
1515                 status = "disabled";
1516         };
1517
1518         ipmmu_sy1: mmu@e6290000 {
1519                 compatible = "renesas,ipmmu-vmsa";
1520                 reg = <0 0xe6290000 0 0x1000>;
1521                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1522                 #iommu-cells = <1>;
1523                 status = "disabled";
1524         };
1525
1526         ipmmu_ds: mmu@e6740000 {
1527                 compatible = "renesas,ipmmu-vmsa";
1528                 reg = <0 0xe6740000 0 0x1000>;
1529                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1530                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
1531                 #iommu-cells = <1>;
1532                 status = "disabled";
1533         };
1534
1535         ipmmu_mp: mmu@ec680000 {
1536                 compatible = "renesas,ipmmu-vmsa";
1537                 reg = <0 0xec680000 0 0x1000>;
1538                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1539                 #iommu-cells = <1>;
1540                 status = "disabled";
1541         };
1542
1543         ipmmu_mx: mmu@fe951000 {
1544                 compatible = "renesas,ipmmu-vmsa";
1545                 reg = <0 0xfe951000 0 0x1000>;
1546                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1547                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
1548                 #iommu-cells = <1>;
1549                 status = "disabled";
1550         };
1551
1552         ipmmu_rt: mmu@ffc80000 {
1553                 compatible = "renesas,ipmmu-vmsa";
1554                 reg = <0 0xffc80000 0 0x1000>;
1555                 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1556                 #iommu-cells = <1>;
1557                 status = "disabled";
1558         };
1559
1560         ipmmu_gp: mmu@e62a0000 {
1561                 compatible = "renesas,ipmmu-vmsa";
1562                 reg = <0 0xe62a0000 0 0x1000>;
1563                 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1564                              <0 261 IRQ_TYPE_LEVEL_HIGH>;
1565                 #iommu-cells = <1>;
1566                 status = "disabled";
1567         };
1568
1569         rcar_sound: sound@ec500000 {
1570                 /*
1571                  * #sound-dai-cells is required
1572                  *
1573                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1574                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1575                  */
1576                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1577                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1578                         <0 0xec5a0000 0 0x100>,  /* ADG */
1579                         <0 0xec540000 0 0x1000>, /* SSIU */
1580                         <0 0xec541000 0 0x1280>, /* SSI */
1581                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1582                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1583
1584                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1585                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1586                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1587                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1588                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1589                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1590                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1591                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1592                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1593                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1594                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1595                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1596                         <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1597                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1598                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1599                 clock-names = "ssi-all",
1600                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1601                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1602                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1603                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1604                                 "ctu.0", "ctu.1",
1605                                 "mix.0", "mix.1",
1606                                 "dvc.0", "dvc.1",
1607                                 "clk_a", "clk_b", "clk_c", "clk_i";
1608
1609                 status = "disabled";
1610
1611                 rcar_sound,dvc {
1612                         dvc0: dvc@0 {
1613                                 dmas = <&audma0 0xbc>;
1614                                 dma-names = "tx";
1615                         };
1616                         dvc1: dvc@1 {
1617                                 dmas = <&audma0 0xbe>;
1618                                 dma-names = "tx";
1619                         };
1620                 };
1621
1622                 rcar_sound,mix {
1623                         mix0: mix@0 { };
1624                         mix1: mix@1 { };
1625                 };
1626
1627                 rcar_sound,ctu {
1628                         ctu00: ctu@0 { };
1629                         ctu01: ctu@1 { };
1630                         ctu02: ctu@2 { };
1631                         ctu03: ctu@3 { };
1632                         ctu10: ctu@4 { };
1633                         ctu11: ctu@5 { };
1634                         ctu12: ctu@6 { };
1635                         ctu13: ctu@7 { };
1636                 };
1637
1638                 rcar_sound,src {
1639                         src0: src@0 {
1640                                 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1641                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1642                                 dma-names = "rx", "tx";
1643                         };
1644                         src1: src@1 {
1645                                 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1646                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1647                                 dma-names = "rx", "tx";
1648                         };
1649                         src2: src@2 {
1650                                 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1651                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1652                                 dma-names = "rx", "tx";
1653                         };
1654                         src3: src@3 {
1655                                 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1656                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1657                                 dma-names = "rx", "tx";
1658                         };
1659                         src4: src@4 {
1660                                 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1661                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1662                                 dma-names = "rx", "tx";
1663                         };
1664                         src5: src@5 {
1665                                 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1666                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1667                                 dma-names = "rx", "tx";
1668                         };
1669                         src6: src@6 {
1670                                 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1671                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1672                                 dma-names = "rx", "tx";
1673                         };
1674                         src7: src@7 {
1675                                 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1676                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1677                                 dma-names = "rx", "tx";
1678                         };
1679                         src8: src@8 {
1680                                 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1681                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1682                                 dma-names = "rx", "tx";
1683                         };
1684                         src9: src@9 {
1685                                 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1686                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1687                                 dma-names = "rx", "tx";
1688                         };
1689                 };
1690
1691                 rcar_sound,ssi {
1692                         ssi0: ssi@0 {
1693                                 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1694                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1695                                 dma-names = "rx", "tx", "rxu", "txu";
1696                         };
1697                         ssi1: ssi@1 {
1698                                  interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1699                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1700                                 dma-names = "rx", "tx", "rxu", "txu";
1701                         };
1702                         ssi2: ssi@2 {
1703                                 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1704                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1705                                 dma-names = "rx", "tx", "rxu", "txu";
1706                         };
1707                         ssi3: ssi@3 {
1708                                 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1709                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1710                                 dma-names = "rx", "tx", "rxu", "txu";
1711                         };
1712                         ssi4: ssi@4 {
1713                                 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1714                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1715                                 dma-names = "rx", "tx", "rxu", "txu";
1716                         };
1717                         ssi5: ssi@5 {
1718                                 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1719                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1720                                 dma-names = "rx", "tx", "rxu", "txu";
1721                         };
1722                         ssi6: ssi@6 {
1723                                 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1724                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1725                                 dma-names = "rx", "tx", "rxu", "txu";
1726                         };
1727                         ssi7: ssi@7 {
1728                                 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1729                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1730                                 dma-names = "rx", "tx", "rxu", "txu";
1731                         };
1732                         ssi8: ssi@8 {
1733                                 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1734                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1735                                 dma-names = "rx", "tx", "rxu", "txu";
1736                         };
1737                         ssi9: ssi@9 {
1738                                 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1739                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1740                                 dma-names = "rx", "tx", "rxu", "txu";
1741                         };
1742                 };
1743         };
1744 };