2 * Device Tree Source for the r8a7792 SoC
4 * Copyright (C) 2016 Cogent Embedded Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7792-clock.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/r8a7792-sysc.h>
17 compatible = "renesas,r8a7792";
42 enable-method = "renesas,apmu";
46 compatible = "arm,cortex-a15";
48 clock-frequency = <1000000000>;
49 clocks = <&cpg_clocks R8A7792_CLK_Z>;
50 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
51 next-level-cache = <&L2_CA15>;
56 compatible = "arm,cortex-a15";
58 clock-frequency = <1000000000>;
59 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
60 next-level-cache = <&L2_CA15>;
63 L2_CA15: cache-controller@0 {
68 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
73 compatible = "simple-bus";
74 interrupt-parent = <&gic>;
81 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
82 reg = <0 0xe6152000 0 0x188>;
86 gic: interrupt-controller@f1001000 {
87 compatible = "arm,gic-400";
88 #interrupt-cells = <3>;
90 reg = <0 0xf1001000 0 0x1000>,
91 <0 0xf1002000 0 0x2000>,
92 <0 0xf1004000 0 0x2000>,
93 <0 0xf1006000 0 0x2000>;
94 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
95 IRQ_TYPE_LEVEL_HIGH)>;
98 irqc: interrupt-controller@e61c0000 {
99 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
100 #interrupt-cells = <2>;
101 interrupt-controller;
102 reg = <0 0xe61c0000 0 0x200>;
103 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
108 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
112 compatible = "arm,armv7-timer";
113 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
114 IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
116 IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
118 IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
120 IRQ_TYPE_LEVEL_LOW)>;
123 rst: reset-controller@e6160000 {
124 compatible = "renesas,r8a7792-rst";
125 reg = <0 0xe6160000 0 0x0100>;
128 prr: chipid@ff000044 {
129 compatible = "renesas,prr";
130 reg = <0 0xff000044 0 4>;
133 sysc: system-controller@e6180000 {
134 compatible = "renesas,r8a7792-sysc";
135 reg = <0 0xe6180000 0 0x0200>;
136 #power-domain-cells = <1>;
139 pfc: pin-controller@e6060000 {
140 compatible = "renesas,pfc-r8a7792";
141 reg = <0 0xe6060000 0 0x144>;
144 gpio0: gpio@e6050000 {
145 compatible = "renesas,gpio-r8a7792",
147 reg = <0 0xe6050000 0 0x50>;
148 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
151 gpio-ranges = <&pfc 0 0 29>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
155 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
158 gpio1: gpio@e6051000 {
159 compatible = "renesas,gpio-r8a7792",
161 reg = <0 0xe6051000 0 0x50>;
162 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
165 gpio-ranges = <&pfc 0 32 23>;
166 #interrupt-cells = <2>;
167 interrupt-controller;
168 clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
169 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
172 gpio2: gpio@e6052000 {
173 compatible = "renesas,gpio-r8a7792",
175 reg = <0 0xe6052000 0 0x50>;
176 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
179 gpio-ranges = <&pfc 0 64 32>;
180 #interrupt-cells = <2>;
181 interrupt-controller;
182 clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
183 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
186 gpio3: gpio@e6053000 {
187 compatible = "renesas,gpio-r8a7792",
189 reg = <0 0xe6053000 0 0x50>;
190 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
193 gpio-ranges = <&pfc 0 96 28>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
197 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
200 gpio4: gpio@e6054000 {
201 compatible = "renesas,gpio-r8a7792",
203 reg = <0 0xe6054000 0 0x50>;
204 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
207 gpio-ranges = <&pfc 0 128 17>;
208 #interrupt-cells = <2>;
209 interrupt-controller;
210 clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
211 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
214 gpio5: gpio@e6055000 {
215 compatible = "renesas,gpio-r8a7792",
217 reg = <0 0xe6055000 0 0x50>;
218 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
221 gpio-ranges = <&pfc 0 160 17>;
222 #interrupt-cells = <2>;
223 interrupt-controller;
224 clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
225 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
228 gpio6: gpio@e6055100 {
229 compatible = "renesas,gpio-r8a7792",
231 reg = <0 0xe6055100 0 0x50>;
232 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
235 gpio-ranges = <&pfc 0 192 17>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
238 clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
239 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
242 gpio7: gpio@e6055200 {
243 compatible = "renesas,gpio-r8a7792",
245 reg = <0 0xe6055200 0 0x50>;
246 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
249 gpio-ranges = <&pfc 0 224 17>;
250 #interrupt-cells = <2>;
251 interrupt-controller;
252 clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
253 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
256 gpio8: gpio@e6055300 {
257 compatible = "renesas,gpio-r8a7792",
259 reg = <0 0xe6055300 0 0x50>;
260 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
263 gpio-ranges = <&pfc 0 256 17>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
266 clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
267 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
270 gpio9: gpio@e6055400 {
271 compatible = "renesas,gpio-r8a7792",
273 reg = <0 0xe6055400 0 0x50>;
274 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
277 gpio-ranges = <&pfc 0 288 17>;
278 #interrupt-cells = <2>;
279 interrupt-controller;
280 clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
281 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
284 gpio10: gpio@e6055500 {
285 compatible = "renesas,gpio-r8a7792",
287 reg = <0 0xe6055500 0 0x50>;
288 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
291 gpio-ranges = <&pfc 0 320 32>;
292 #interrupt-cells = <2>;
293 interrupt-controller;
294 clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
295 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
298 gpio11: gpio@e6055600 {
299 compatible = "renesas,gpio-r8a7792",
301 reg = <0 0xe6055600 0 0x50>;
302 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
305 gpio-ranges = <&pfc 0 352 30>;
306 #interrupt-cells = <2>;
307 interrupt-controller;
308 clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
309 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
312 dmac0: dma-controller@e6700000 {
313 compatible = "renesas,dmac-r8a7792",
315 reg = <0 0xe6700000 0 0x20000>;
316 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "error",
333 "ch0", "ch1", "ch2", "ch3",
334 "ch4", "ch5", "ch6", "ch7",
335 "ch8", "ch9", "ch10", "ch11",
336 "ch12", "ch13", "ch14";
337 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
339 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
344 dmac1: dma-controller@e6720000 {
345 compatible = "renesas,dmac-r8a7792",
347 reg = <0 0xe6720000 0 0x20000>;
348 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-names = "error",
365 "ch0", "ch1", "ch2", "ch3",
366 "ch4", "ch5", "ch6", "ch7",
367 "ch8", "ch9", "ch10", "ch11",
368 "ch12", "ch13", "ch14";
369 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
371 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
376 scif0: serial@e6e60000 {
377 compatible = "renesas,scif-r8a7792",
378 "renesas,rcar-gen2-scif", "renesas,scif";
379 reg = <0 0xe6e60000 0 64>;
380 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
383 clock-names = "fck", "brg_int", "scif_clk";
384 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
385 <&dmac1 0x29>, <&dmac1 0x2a>;
386 dma-names = "tx", "rx", "tx", "rx";
387 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
391 scif1: serial@e6e68000 {
392 compatible = "renesas,scif-r8a7792",
393 "renesas,rcar-gen2-scif", "renesas,scif";
394 reg = <0 0xe6e68000 0 64>;
395 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
398 clock-names = "fck", "brg_int", "scif_clk";
399 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
400 <&dmac1 0x2d>, <&dmac1 0x2e>;
401 dma-names = "tx", "rx", "tx", "rx";
402 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
406 scif2: serial@e6e58000 {
407 compatible = "renesas,scif-r8a7792",
408 "renesas,rcar-gen2-scif", "renesas,scif";
409 reg = <0 0xe6e58000 0 64>;
410 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
413 clock-names = "fck", "brg_int", "scif_clk";
414 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
415 <&dmac1 0x2b>, <&dmac1 0x2c>;
416 dma-names = "tx", "rx", "tx", "rx";
417 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
421 scif3: serial@e6ea8000 {
422 compatible = "renesas,scif-r8a7792",
423 "renesas,rcar-gen2-scif", "renesas,scif";
424 reg = <0 0xe6ea8000 0 64>;
425 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
428 clock-names = "fck", "brg_int", "scif_clk";
429 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
430 <&dmac1 0x2f>, <&dmac1 0x30>;
431 dma-names = "tx", "rx", "tx", "rx";
432 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
436 hscif0: serial@e62c0000 {
437 compatible = "renesas,hscif-r8a7792",
438 "renesas,rcar-gen2-hscif", "renesas,hscif";
439 reg = <0 0xe62c0000 0 96>;
440 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
443 clock-names = "fck", "brg_int", "scif_clk";
444 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
445 <&dmac1 0x39>, <&dmac1 0x3a>;
446 dma-names = "tx", "rx", "tx", "rx";
447 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
451 hscif1: serial@e62c8000 {
452 compatible = "renesas,hscif-r8a7792",
453 "renesas,rcar-gen2-hscif", "renesas,hscif";
454 reg = <0 0xe62c8000 0 96>;
455 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
458 clock-names = "fck", "brg_int", "scif_clk";
459 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
460 <&dmac1 0x4d>, <&dmac1 0x4e>;
461 dma-names = "tx", "rx", "tx", "rx";
462 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
467 compatible = "renesas,sdhi-r8a7792";
468 reg = <0 0xee100000 0 0x328>;
469 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
470 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
471 <&dmac1 0xcd>, <&dmac1 0xce>;
472 dma-names = "tx", "rx", "tx", "rx";
473 clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
474 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
478 jpu: jpeg-codec@fe980000 {
479 compatible = "renesas,jpu-r8a7792",
480 "renesas,rcar-gen2-jpu";
481 reg = <0 0xfe980000 0 0x10300>;
482 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
484 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
487 avb: ethernet@e6800000 {
488 compatible = "renesas,etheravb-r8a7792",
489 "renesas,etheravb-rcar-gen2";
490 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
491 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
493 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
494 #address-cells = <1>;
499 /* I2C doesn't need pinmux */
501 compatible = "renesas,i2c-r8a7792",
502 "renesas,rcar-gen2-i2c";
503 reg = <0 0xe6508000 0 0x40>;
504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
506 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
507 i2c-scl-internal-delay-ns = <6>;
508 #address-cells = <1>;
514 compatible = "renesas,i2c-r8a7792",
515 "renesas,rcar-gen2-i2c";
516 reg = <0 0xe6518000 0 0x40>;
517 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
519 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
520 i2c-scl-internal-delay-ns = <6>;
521 #address-cells = <1>;
527 compatible = "renesas,i2c-r8a7792",
528 "renesas,rcar-gen2-i2c";
529 reg = <0 0xe6530000 0 0x40>;
530 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
532 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
533 i2c-scl-internal-delay-ns = <6>;
534 #address-cells = <1>;
540 compatible = "renesas,i2c-r8a7792",
541 "renesas,rcar-gen2-i2c";
542 reg = <0 0xe6540000 0 0x40>;
543 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
545 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
546 i2c-scl-internal-delay-ns = <6>;
547 #address-cells = <1>;
553 compatible = "renesas,i2c-r8a7792",
554 "renesas,rcar-gen2-i2c";
555 reg = <0 0xe6520000 0 0x40>;
556 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
558 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
559 i2c-scl-internal-delay-ns = <6>;
560 #address-cells = <1>;
566 compatible = "renesas,i2c-r8a7792",
567 "renesas,rcar-gen2-i2c";
568 reg = <0 0xe6528000 0 0x40>;
569 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
571 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
572 i2c-scl-internal-delay-ns = <110>;
573 #address-cells = <1>;
579 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
580 reg = <0 0xe6b10000 0 0x2c>;
581 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
583 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
584 <&dmac1 0x17>, <&dmac1 0x18>;
585 dma-names = "tx", "rx", "tx", "rx";
586 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
588 #address-cells = <1>;
593 msiof0: spi@e6e20000 {
594 compatible = "renesas,msiof-r8a7792",
595 "renesas,rcar-gen2-msiof";
596 reg = <0 0xe6e20000 0 0x0064>;
597 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
599 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
600 <&dmac1 0x51>, <&dmac1 0x52>;
601 dma-names = "tx", "rx", "tx", "rx";
602 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
603 #address-cells = <1>;
608 msiof1: spi@e6e10000 {
609 compatible = "renesas,msiof-r8a7792",
610 "renesas,rcar-gen2-msiof";
611 reg = <0 0xe6e10000 0 0x0064>;
612 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
614 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
615 <&dmac1 0x55>, <&dmac1 0x56>;
616 dma-names = "tx", "rx", "tx", "rx";
617 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
618 #address-cells = <1>;
623 du: display@feb00000 {
624 compatible = "renesas,du-r8a7792";
625 reg = <0 0xfeb00000 0 0x40000>;
627 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&mstp7_clks R8A7792_CLK_DU0>,
630 <&mstp7_clks R8A7792_CLK_DU1>;
631 clock-names = "du.0", "du.1";
635 #address-cells = <1>;
640 du_out_rgb0: endpoint {
645 du_out_rgb1: endpoint {
652 compatible = "renesas,can-r8a7792",
653 "renesas,rcar-gen2-can";
654 reg = <0 0xe6e80000 0 0x1000>;
655 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
657 <&rcan_clk>, <&can_clk>;
658 clock-names = "clkp1", "clkp2", "can_clk";
659 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
664 compatible = "renesas,can-r8a7792",
665 "renesas,rcar-gen2-can";
666 reg = <0 0xe6e88000 0 0x1000>;
667 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
669 <&rcan_clk>, <&can_clk>;
670 clock-names = "clkp1", "clkp2", "can_clk";
671 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
675 vin0: video@e6ef0000 {
676 compatible = "renesas,vin-r8a7792",
677 "renesas,rcar-gen2-vin";
678 reg = <0 0xe6ef0000 0 0x1000>;
679 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
681 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
685 vin1: video@e6ef1000 {
686 compatible = "renesas,vin-r8a7792",
687 "renesas,rcar-gen2-vin";
688 reg = <0 0xe6ef1000 0 0x1000>;
689 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
691 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
695 vin2: video@e6ef2000 {
696 compatible = "renesas,vin-r8a7792",
697 "renesas,rcar-gen2-vin";
698 reg = <0 0xe6ef2000 0 0x1000>;
699 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
701 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
705 vin3: video@e6ef3000 {
706 compatible = "renesas,vin-r8a7792",
707 "renesas,rcar-gen2-vin";
708 reg = <0 0xe6ef3000 0 0x1000>;
709 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
711 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
715 vin4: video@e6ef4000 {
716 compatible = "renesas,vin-r8a7792",
717 "renesas,rcar-gen2-vin";
718 reg = <0 0xe6ef4000 0 0x1000>;
719 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
721 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
725 vin5: video@e6ef5000 {
726 compatible = "renesas,vin-r8a7792",
727 "renesas,rcar-gen2-vin";
728 reg = <0 0xe6ef5000 0 0x1000>;
729 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
731 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
736 compatible = "renesas,vsp1";
737 reg = <0 0xfe928000 0 0x8000>;
738 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
740 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
744 compatible = "renesas,vsp1";
745 reg = <0 0xfe930000 0 0x8000>;
746 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
748 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
752 compatible = "renesas,vsp1";
753 reg = <0 0xfe938000 0 0x8000>;
754 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
756 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
759 /* Special CPG clocks */
760 cpg_clocks: cpg_clocks@e6150000 {
761 compatible = "renesas,r8a7792-cpg-clocks",
762 "renesas,rcar-gen2-cpg-clocks";
763 reg = <0 0xe6150000 0 0x1000>;
764 clocks = <&extal_clk>;
766 clock-output-names = "main", "pll0", "pll1", "pll3",
768 #power-domain-cells = <0>;
771 /* Fixed factor clocks */
772 pll1_div2_clk: pll1_div2 {
773 compatible = "fixed-factor-clock";
774 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
780 compatible = "fixed-factor-clock";
781 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
787 compatible = "fixed-factor-clock";
788 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
794 compatible = "fixed-factor-clock";
795 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
801 compatible = "fixed-factor-clock";
802 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
808 compatible = "fixed-factor-clock";
809 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
815 compatible = "fixed-factor-clock";
816 clocks = <&pll1_div2_clk>;
822 compatible = "fixed-factor-clock";
823 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
829 compatible = "fixed-factor-clock";
830 clocks = <&pll1_div2_clk>;
836 compatible = "fixed-factor-clock";
837 clocks = <&pll1_div2_clk>;
843 compatible = "fixed-factor-clock";
844 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
851 mstp0_clks: mstp0_clks@e6150130 {
852 compatible = "renesas,r8a7792-mstp-clocks",
853 "renesas,cpg-mstp-clocks";
854 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
857 clock-indices = <R8A7792_CLK_MSIOF0>;
858 clock-output-names = "msiof0";
860 mstp1_clks: mstp1_clks@e6150134 {
861 compatible = "renesas,r8a7792-mstp-clocks",
862 "renesas,cpg-mstp-clocks";
863 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
864 clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
868 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
871 clock-output-names = "jpu", "vsp1du1", "vsp1du0",
874 mstp2_clks: mstp2_clks@e6150138 {
875 compatible = "renesas,r8a7792-mstp-clocks",
876 "renesas,cpg-mstp-clocks";
877 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
878 clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
882 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
884 clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
886 mstp3_clks: mstp3_clks@e615013c {
887 compatible = "renesas,r8a7792-mstp-clocks",
888 "renesas,cpg-mstp-clocks";
889 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
892 renesas,clock-indices = <R8A7792_CLK_SDHI0>;
893 clock-output-names = "sdhi0";
895 mstp4_clks: mstp4_clks@e6150140 {
896 compatible = "renesas,r8a7792-mstp-clocks",
897 "renesas,cpg-mstp-clocks";
898 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
901 clock-indices = <R8A7792_CLK_IRQC>;
902 clock-output-names = "irqc";
904 mstp7_clks: mstp7_clks@e615014c {
905 compatible = "renesas,r8a7792-mstp-clocks",
906 "renesas,cpg-mstp-clocks";
907 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
908 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
909 <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
912 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
913 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
914 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
915 R8A7792_CLK_DU1 R8A7792_CLK_DU0
917 clock-output-names = "hscif1", "hscif0", "scif3",
918 "scif2", "scif1", "scif0",
921 mstp8_clks: mstp8_clks@e6150990 {
922 compatible = "renesas,r8a7792-mstp-clocks",
923 "renesas,cpg-mstp-clocks";
924 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
925 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
926 <&zg_clk>, <&zg_clk>, <&hp_clk>;
929 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
930 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
931 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
934 clock-output-names = "vin5", "vin4", "vin3", "vin2",
935 "vin1", "vin0", "etheravb";
937 mstp9_clks: mstp9_clks@e6150994 {
938 compatible = "renesas,r8a7792-mstp-clocks",
939 "renesas,cpg-mstp-clocks";
940 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
941 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
942 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
943 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
944 <&cpg_clocks R8A7792_CLK_QSPI>,
945 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
946 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
949 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
950 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
951 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
952 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
953 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
954 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
956 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
957 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
958 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
959 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
962 "gpio7", "gpio6", "gpio5", "gpio4",
963 "gpio3", "gpio2", "gpio1", "gpio0",
964 "gpio11", "gpio10", "can1", "can0",
965 "qspi_mod", "gpio9", "gpio8",
966 "i2c5", "i2c4", "i2c3", "i2c2",
971 /* External root clock */
973 compatible = "fixed-clock";
975 /* This value must be overridden by the board. */
976 clock-frequency = <0>;
979 /* External SCIF clock */
981 compatible = "fixed-clock";
983 /* This value must be overridden by the board. */
984 clock-frequency = <0>;
987 /* External CAN clock */
989 compatible = "fixed-clock";
991 /* This value must be overridden by the board. */
992 clock-frequency = <0>;