arch/arm/boot/dts/r8a7793.dtsi

   1 /*
   2  * Device Tree Source for the r8a7793 SoC
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7793-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r8a7793";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 i2c6 = &i2c6;
  29                 i2c7 = &i2c7;
  30                 i2c8 = &i2c8;
  31                 spi0 = &qspi;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a15";
  41                         reg = <0>;
  42                         clock-frequency = <1500000000>;
  43                         voltage-tolerance = <1>; /* 1% */
  44                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
  45                         clock-latency = <300000>; /* 300 us */
  46
  47                         /* kHz - uV - OPPs unknown yet */
  48                         operating-points = <1500000 1000000>,
  49                                            <1312500 1000000>,
  50                                            <1125000 1000000>,
  51                                            < 937500 1000000>,
  52                                            < 750000 1000000>,
  53                                            < 375000 1000000>;
  54                 };
  55         };
  56
  57         gic: interrupt-controller@f1001000 {
  58                 compatible = "arm,gic-400";
  59                 #interrupt-cells = <3>;
  60                 #address-cells = <0>;
  61                 interrupt-controller;
  62                 reg = <0 0xf1001000 0 0x1000>,
  63                         <0 0xf1002000 0 0x1000>,
  64                         <0 0xf1004000 0 0x2000>,
  65                         <0 0xf1006000 0 0x2000>;
  66                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  67         };
  68
  69         gpio0: gpio@e6050000 {
  70                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  71                 reg = <0 0xe6050000 0 0x50>;
  72                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  73                 #gpio-cells = <2>;
  74                 gpio-controller;
  75                 gpio-ranges = <&pfc 0 0 32>;
  76                 #interrupt-cells = <2>;
  77                 interrupt-controller;
  78                 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
  79                 power-domains = <&cpg_clocks>;
  80         };
  81
  82         gpio1: gpio@e6051000 {
  83                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  84                 reg = <0 0xe6051000 0 0x50>;
  85                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  86                 #gpio-cells = <2>;
  87                 gpio-controller;
  88                 gpio-ranges = <&pfc 0 32 26>;
  89                 #interrupt-cells = <2>;
  90                 interrupt-controller;
  91                 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
  92                 power-domains = <&cpg_clocks>;
  93         };
  94
  95         gpio2: gpio@e6052000 {
  96                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  97                 reg = <0 0xe6052000 0 0x50>;
  98                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  99                 #gpio-cells = <2>;
 100                 gpio-controller;
 101                 gpio-ranges = <&pfc 0 64 32>;
 102                 #interrupt-cells = <2>;
 103                 interrupt-controller;
 104                 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
 105                 power-domains = <&cpg_clocks>;
 106         };
 107
 108         gpio3: gpio@e6053000 {
 109                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 110                 reg = <0 0xe6053000 0 0x50>;
 111                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 96 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117                 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
 118                 power-domains = <&cpg_clocks>;
 119         };
 120
 121         gpio4: gpio@e6054000 {
 122                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 123                 reg = <0 0xe6054000 0 0x50>;
 124                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 125                 #gpio-cells = <2>;
 126                 gpio-controller;
 127                 gpio-ranges = <&pfc 0 128 32>;
 128                 #interrupt-cells = <2>;
 129                 interrupt-controller;
 130                 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
 131                 power-domains = <&cpg_clocks>;
 132         };
 133
 134         gpio5: gpio@e6055000 {
 135                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 136                 reg = <0 0xe6055000 0 0x50>;
 137                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 160 32>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143                 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
 144                 power-domains = <&cpg_clocks>;
 145         };
 146
 147         gpio6: gpio@e6055400 {
 148                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 149                 reg = <0 0xe6055400 0 0x50>;
 150                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 151                 #gpio-cells = <2>;
 152                 gpio-controller;
 153                 gpio-ranges = <&pfc 0 192 32>;
 154                 #interrupt-cells = <2>;
 155                 interrupt-controller;
 156                 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
 157                 power-domains = <&cpg_clocks>;
 158         };
 159
 160         gpio7: gpio@e6055800 {
 161                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 162                 reg = <0 0xe6055800 0 0x50>;
 163                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 164                 #gpio-cells = <2>;
 165                 gpio-controller;
 166                 gpio-ranges = <&pfc 0 224 26>;
 167                 #interrupt-cells = <2>;
 168                 interrupt-controller;
 169                 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
 170                 power-domains = <&cpg_clocks>;
 171         };
 172
 173         thermal@e61f0000 {
 174                 compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
 175                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 176                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
 178                 power-domains = <&cpg_clocks>;
 179         };
 180
 181         timer {
 182                 compatible = "arm,armv7-timer";
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 184                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 185                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 186                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 187         };
 188
 189         cmt0: timer@ffca0000 {
 190                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 191                 reg = <0 0xffca0000 0 0x1004>;
 192                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 195                 clock-names = "fck";
 196                 power-domains = <&cpg_clocks>;
 197
 198                 renesas,channels-mask = <0x60>;
 199
 200                 status = "disabled";
 201         };
 202
 203         cmt1: timer@e6130000 {
 204                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 205                 reg = <0 0xe6130000 0 0x1004>;
 206                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 215                 clock-names = "fck";
 216                 power-domains = <&cpg_clocks>;
 217
 218                 renesas,channels-mask = <0xff>;
 219
 220                 status = "disabled";
 221         };
 222
 223         irqc0: interrupt-controller@e61c0000 {
 224                 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
 225                 #interrupt-cells = <2>;
 226                 interrupt-controller;
 227                 reg = <0 0xe61c0000 0 0x200>;
 228                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 229                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 230                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 231                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
 239                 power-domains = <&cpg_clocks>;
 240         };
 241
 242         dmac0: dma-controller@e6700000 {
 243                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 244                 reg = <0 0xe6700000 0 0x20000>;
 245                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 249                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 250                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 251                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 252                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 253                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 254                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 255                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 256                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 257                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 258                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 259                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 260                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 261                 interrupt-names = "error",
 262                                 "ch0", "ch1", "ch2", "ch3",
 263                                 "ch4", "ch5", "ch6", "ch7",
 264                                 "ch8", "ch9", "ch10", "ch11",
 265                                 "ch12", "ch13", "ch14";
 266                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
 267                 clock-names = "fck";
 268                 power-domains = <&cpg_clocks>;
 269                 #dma-cells = <1>;
 270                 dma-channels = <15>;
 271         };
 272
 273         dmac1: dma-controller@e6720000 {
 274                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 275                 reg = <0 0xe6720000 0 0x20000>;
 276                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 280                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 281                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 282                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 283                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 284                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 285                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 286                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 287                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 288                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 289                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 290                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 291                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 292                 interrupt-names = "error",
 293                                 "ch0", "ch1", "ch2", "ch3",
 294                                 "ch4", "ch5", "ch6", "ch7",
 295                                 "ch8", "ch9", "ch10", "ch11",
 296                                 "ch12", "ch13", "ch14";
 297                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
 298                 clock-names = "fck";
 299                 power-domains = <&cpg_clocks>;
 300                 #dma-cells = <1>;
 301                 dma-channels = <15>;
 302         };
 303
 304         audma0: dma-controller@ec700000 {
 305                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 306                 reg = <0 0xec700000 0 0x10000>;
 307                 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 308                               GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 309                               GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 310                               GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 311                               GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 312                               GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 313                               GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 314                               GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 315                               GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 316                               GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 317                               GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 318                               GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 319                               GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 320                               GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 321                 interrupt-names = "error",
 322                                 "ch0", "ch1", "ch2", "ch3",
 323                                 "ch4", "ch5", "ch6", "ch7",
 324                                 "ch8", "ch9", "ch10", "ch11",
 325                                 "ch12";
 326                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
 327                 clock-names = "fck";
 328                 power-domains = <&cpg_clocks>;
 329                 #dma-cells = <1>;
 330                 dma-channels = <13>;
 331         };
 332
 333         audma1: dma-controller@ec720000 {
 334                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 335                 reg = <0 0xec720000 0 0x10000>;
 336                 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 340                               GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 341                               GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 342                               GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 343                               GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 344                               GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 345                               GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 346                               GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 347                               GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 348                               GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 349                               GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 350                 interrupt-names = "error",
 351                                 "ch0", "ch1", "ch2", "ch3",
 352                                 "ch4", "ch5", "ch6", "ch7",
 353                                 "ch8", "ch9", "ch10", "ch11",
 354                                 "ch12";
 355                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
 356                 clock-names = "fck";
 357                 power-domains = <&cpg_clocks>;
 358                 #dma-cells = <1>;
 359                 dma-channels = <13>;
 360         };
 361
 362         /* The memory map in the User's Manual maps the cores to bus numbers */
 363         i2c0: i2c@e6508000 {
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 compatible = "renesas,i2c-r8a7793";
 367                 reg = <0 0xe6508000 0 0x40>;
 368                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
 370                 power-domains = <&cpg_clocks>;
 371                 i2c-scl-internal-delay-ns = <6>;
 372                 status = "disabled";
 373         };
 374
 375         i2c1: i2c@e6518000 {
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 compatible = "renesas,i2c-r8a7793";
 379                 reg = <0 0xe6518000 0 0x40>;
 380                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
 382                 power-domains = <&cpg_clocks>;
 383                 i2c-scl-internal-delay-ns = <6>;
 384                 status = "disabled";
 385         };
 386
 387         i2c2: i2c@e6530000 {
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 compatible = "renesas,i2c-r8a7793";
 391                 reg = <0 0xe6530000 0 0x40>;
 392                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
 394                 power-domains = <&cpg_clocks>;
 395                 i2c-scl-internal-delay-ns = <6>;
 396                 status = "disabled";
 397         };
 398
 399         i2c3: i2c@e6540000 {
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 compatible = "renesas,i2c-r8a7793";
 403                 reg = <0 0xe6540000 0 0x40>;
 404                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 405                 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
 406                 power-domains = <&cpg_clocks>;
 407                 i2c-scl-internal-delay-ns = <6>;
 408                 status = "disabled";
 409         };
 410
 411         i2c4: i2c@e6520000 {
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 compatible = "renesas,i2c-r8a7793";
 415                 reg = <0 0xe6520000 0 0x40>;
 416                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 417                 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
 418                 power-domains = <&cpg_clocks>;
 419                 i2c-scl-internal-delay-ns = <6>;
 420                 status = "disabled";
 421         };
 422
 423         i2c5: i2c@e6528000 {
 424                 /* doesn't need pinmux */
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 compatible = "renesas,i2c-r8a7793";
 428                 reg = <0 0xe6528000 0 0x40>;
 429                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
 431                 power-domains = <&cpg_clocks>;
 432                 i2c-scl-internal-delay-ns = <110>;
 433                 status = "disabled";
 434         };
 435
 436         i2c6: i2c@e60b0000 {
 437                 /* doesn't need pinmux */
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 441                 reg = <0 0xe60b0000 0 0x425>;
 442                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
 444                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 445                 dma-names = "tx", "rx";
 446                 power-domains = <&cpg_clocks>;
 447                 status = "disabled";
 448         };
 449
 450         i2c7: i2c@e6500000 {
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 454                 reg = <0 0xe6500000 0 0x425>;
 455                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 456                 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
 457                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 458                 dma-names = "tx", "rx";
 459                 power-domains = <&cpg_clocks>;
 460                 status = "disabled";
 461         };
 462
 463         i2c8: i2c@e6510000 {
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 467                 reg = <0 0xe6510000 0 0x425>;
 468                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 469                 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
 470                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 471                 dma-names = "tx", "rx";
 472                 power-domains = <&cpg_clocks>;
 473                 status = "disabled";
 474         };
 475
 476         pfc: pfc@e6060000 {
 477                 compatible = "renesas,pfc-r8a7793";
 478                 reg = <0 0xe6060000 0 0x250>;
 479         };
 480
 481         scifa0: serial@e6c40000 {
 482                 compatible = "renesas,scifa-r8a7793",
 483                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 484                 reg = <0 0xe6c40000 0 64>;
 485                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 486                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
 487                 clock-names = "fck";
 488                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 489                 dma-names = "tx", "rx";
 490                 power-domains = <&cpg_clocks>;
 491                 status = "disabled";
 492         };
 493
 494         scifa1: serial@e6c50000 {
 495                 compatible = "renesas,scifa-r8a7793",
 496                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 497                 reg = <0 0xe6c50000 0 64>;
 498                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
 500                 clock-names = "fck";
 501                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 502                 dma-names = "tx", "rx";
 503                 power-domains = <&cpg_clocks>;
 504                 status = "disabled";
 505         };
 506
 507         scifa2: serial@e6c60000 {
 508                 compatible = "renesas,scifa-r8a7793",
 509                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 510                 reg = <0 0xe6c60000 0 64>;
 511                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
 513                 clock-names = "fck";
 514                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 515                 dma-names = "tx", "rx";
 516                 power-domains = <&cpg_clocks>;
 517                 status = "disabled";
 518         };
 519
 520         scifa3: serial@e6c70000 {
 521                 compatible = "renesas,scifa-r8a7793",
 522                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 523                 reg = <0 0xe6c70000 0 64>;
 524                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
 526                 clock-names = "fck";
 527                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 528                 dma-names = "tx", "rx";
 529                 power-domains = <&cpg_clocks>;
 530                 status = "disabled";
 531         };
 532
 533         scifa4: serial@e6c78000 {
 534                 compatible = "renesas,scifa-r8a7793",
 535                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 536                 reg = <0 0xe6c78000 0 64>;
 537                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 538                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
 539                 clock-names = "fck";
 540                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 541                 dma-names = "tx", "rx";
 542                 power-domains = <&cpg_clocks>;
 543                 status = "disabled";
 544         };
 545
 546         scifa5: serial@e6c80000 {
 547                 compatible = "renesas,scifa-r8a7793",
 548                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 549                 reg = <0 0xe6c80000 0 64>;
 550                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
 552                 clock-names = "fck";
 553                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 554                 dma-names = "tx", "rx";
 555                 power-domains = <&cpg_clocks>;
 556                 status = "disabled";
 557         };
 558
 559         scifb0: serial@e6c20000 {
 560                 compatible = "renesas,scifb-r8a7793",
 561                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 562                 reg = <0 0xe6c20000 0 64>;
 563                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 564                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
 565                 clock-names = "fck";
 566                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 567                 dma-names = "tx", "rx";
 568                 power-domains = <&cpg_clocks>;
 569                 status = "disabled";
 570         };
 571
 572         scifb1: serial@e6c30000 {
 573                 compatible = "renesas,scifb-r8a7793",
 574                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 575                 reg = <0 0xe6c30000 0 64>;
 576                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 577                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
 578                 clock-names = "fck";
 579                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 580                 dma-names = "tx", "rx";
 581                 power-domains = <&cpg_clocks>;
 582                 status = "disabled";
 583         };
 584
 585         scifb2: serial@e6ce0000 {
 586                 compatible = "renesas,scifb-r8a7793",
 587                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 588                 reg = <0 0xe6ce0000 0 64>;
 589                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 590                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
 591                 clock-names = "fck";
 592                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 593                 dma-names = "tx", "rx";
 594                 power-domains = <&cpg_clocks>;
 595                 status = "disabled";
 596         };
 597
 598         scif0: serial@e6e60000 {
 599                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 600                              "renesas,scif";
 601                 reg = <0 0xe6e60000 0 64>;
 602                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
 604                          <&scif_clk>;
 605                 clock-names = "fck", "brg_int", "scif_clk";
 606                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 607                 dma-names = "tx", "rx";
 608                 power-domains = <&cpg_clocks>;
 609                 status = "disabled";
 610         };
 611
 612         scif1: serial@e6e68000 {
 613                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 614                              "renesas,scif";
 615                 reg = <0 0xe6e68000 0 64>;
 616                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
 618                          <&scif_clk>;
 619                 clock-names = "fck", "brg_int", "scif_clk";
 620                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 621                 dma-names = "tx", "rx";
 622                 power-domains = <&cpg_clocks>;
 623                 status = "disabled";
 624         };
 625
 626         scif2: serial@e6e58000 {
 627                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 628                              "renesas,scif";
 629                 reg = <0 0xe6e58000 0 64>;
 630                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 631                 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
 632                          <&scif_clk>;
 633                 clock-names = "fck", "brg_int", "scif_clk";
 634                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 635                 dma-names = "tx", "rx";
 636                 power-domains = <&cpg_clocks>;
 637                 status = "disabled";
 638         };
 639
 640         scif3: serial@e6ea8000 {
 641                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 642                              "renesas,scif";
 643                 reg = <0 0xe6ea8000 0 64>;
 644                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
 646                          <&scif_clk>;
 647                 clock-names = "fck", "brg_int", "scif_clk";
 648                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 649                 dma-names = "tx", "rx";
 650                 power-domains = <&cpg_clocks>;
 651                 status = "disabled";
 652         };
 653
 654         scif4: serial@e6ee0000 {
 655                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 656                              "renesas,scif";
 657                 reg = <0 0xe6ee0000 0 64>;
 658                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 659                 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
 660                          <&scif_clk>;
 661                 clock-names = "fck", "brg_int", "scif_clk";
 662                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 663                 dma-names = "tx", "rx";
 664                 power-domains = <&cpg_clocks>;
 665                 status = "disabled";
 666         };
 667
 668         scif5: serial@e6ee8000 {
 669                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 670                              "renesas,scif";
 671                 reg = <0 0xe6ee8000 0 64>;
 672                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 673                 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
 674                          <&scif_clk>;
 675                 clock-names = "fck", "brg_int", "scif_clk";
 676                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 677                 dma-names = "tx", "rx";
 678                 power-domains = <&cpg_clocks>;
 679                 status = "disabled";
 680         };
 681
 682         hscif0: serial@e62c0000 {
 683                 compatible = "renesas,hscif-r8a7793",
 684                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 685                 reg = <0 0xe62c0000 0 96>;
 686                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 687                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
 688                          <&scif_clk>;
 689                 clock-names = "fck", "brg_int", "scif_clk";
 690                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 691                 dma-names = "tx", "rx";
 692                 power-domains = <&cpg_clocks>;
 693                 status = "disabled";
 694         };
 695
 696         hscif1: serial@e62c8000 {
 697                 compatible = "renesas,hscif-r8a7793",
 698                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 699                 reg = <0 0xe62c8000 0 96>;
 700                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 701                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
 702                          <&scif_clk>;
 703                 clock-names = "fck", "brg_int", "scif_clk";
 704                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 705                 dma-names = "tx", "rx";
 706                 power-domains = <&cpg_clocks>;
 707                 status = "disabled";
 708         };
 709
 710         hscif2: serial@e62d0000 {
 711                 compatible = "renesas,hscif-r8a7793",
 712                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 713                 reg = <0 0xe62d0000 0 96>;
 714                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 715                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
 716                          <&scif_clk>;
 717                 clock-names = "fck", "brg_int", "scif_clk";
 718                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 719                 dma-names = "tx", "rx";
 720                 power-domains = <&cpg_clocks>;
 721                 status = "disabled";
 722         };
 723
 724         ether: ethernet@ee700000 {
 725                 compatible = "renesas,ether-r8a7793";
 726                 reg = <0 0xee700000 0 0x400>;
 727                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 728                 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
 729                 power-domains = <&cpg_clocks>;
 730                 phy-mode = "rmii";
 731                 #address-cells = <1>;
 732                 #size-cells = <0>;
 733                 status = "disabled";
 734         };
 735
 736         qspi: spi@e6b10000 {
 737                 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
 738                 reg = <0 0xe6b10000 0 0x2c>;
 739                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 740                 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
 741                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 742                 dma-names = "tx", "rx";
 743                 power-domains = <&cpg_clocks>;
 744                 num-cs = <1>;
 745                 #address-cells = <1>;
 746                 #size-cells = <0>;
 747                 status = "disabled";
 748         };
 749
 750         du: display@feb00000 {
 751                 compatible = "renesas,du-r8a7793";
 752                 reg = <0 0xfeb00000 0 0x40000>,
 753                       <0 0xfeb90000 0 0x1c>;
 754                 reg-names = "du", "lvds.0";
 755                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 756                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 757                 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
 758                          <&mstp7_clks R8A7793_CLK_DU1>,
 759                          <&mstp7_clks R8A7793_CLK_LVDS0>;
 760                 clock-names = "du.0", "du.1", "lvds.0";
 761                 status = "disabled";
 762
 763                 ports {
 764                         #address-cells = <1>;
 765                         #size-cells = <0>;
 766
 767                         port@0 {
 768                                 reg = <0>;
 769                                 du_out_rgb: endpoint {
 770                                 };
 771                         };
 772                         port@1 {
 773                                 reg = <1>;
 774                                 du_out_lvds0: endpoint {
 775                                 };
 776                         };
 777                 };
 778         };
 779
 780         clocks {
 781                 #address-cells = <2>;
 782                 #size-cells = <2>;
 783                 ranges;
 784
 785                 /* External root clock */
 786                 extal_clk: extal_clk {
 787                         compatible = "fixed-clock";
 788                         #clock-cells = <0>;
 789                         /* This value must be overridden by the board. */
 790                         clock-frequency = <0>;
 791                         clock-output-names = "extal";
 792                 };
 793
 794                 /*
 795                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 796                  * default. Boards that provide audio clocks should override them.
 797                  */
 798                 audio_clk_a: audio_clk_a {
 799                         compatible = "fixed-clock";
 800                         #clock-cells = <0>;
 801                         clock-frequency = <0>;
 802                         clock-output-names = "audio_clk_a";
 803                 };
 804                 audio_clk_b: audio_clk_b {
 805                         compatible = "fixed-clock";
 806                         #clock-cells = <0>;
 807                         clock-frequency = <0>;
 808                         clock-output-names = "audio_clk_b";
 809                 };
 810                 audio_clk_c: audio_clk_c {
 811                         compatible = "fixed-clock";
 812                         #clock-cells = <0>;
 813                         clock-frequency = <0>;
 814                         clock-output-names = "audio_clk_c";
 815                 };
 816
 817                 /* External SCIF clock */
 818                 scif_clk: scif {
 819                         compatible = "fixed-clock";
 820                         #clock-cells = <0>;
 821                         /* This value must be overridden by the board. */
 822                         clock-frequency = <0>;
 823                         status = "disabled";
 824                 };
 825
 826                 /* Special CPG clocks */
 827                 cpg_clocks: cpg_clocks@e6150000 {
 828                         compatible = "renesas,r8a7793-cpg-clocks",
 829                                      "renesas,rcar-gen2-cpg-clocks";
 830                         reg = <0 0xe6150000 0 0x1000>;
 831                         clocks = <&extal_clk>;
 832                         #clock-cells = <1>;
 833                         clock-output-names = "main", "pll0", "pll1", "pll3",
 834                                              "lb", "qspi", "sdh", "sd0", "z",
 835                                              "rcan", "adsp";
 836                         #power-domain-cells = <0>;
 837                 };
 838
 839                 /* Variable factor clocks */
 840                 sd2_clk: sd2_clk@e6150078 {
 841                         compatible = "renesas,r8a7793-div6-clock",
 842                                      "renesas,cpg-div6-clock";
 843                         reg = <0 0xe6150078 0 4>;
 844                         clocks = <&pll1_div2_clk>;
 845                         #clock-cells = <0>;
 846                         clock-output-names = "sd2";
 847                 };
 848                 sd3_clk: sd3_clk@e615026c {
 849                         compatible = "renesas,r8a7793-div6-clock",
 850                                      "renesas,cpg-div6-clock";
 851                         reg = <0 0xe615026c 0 4>;
 852                         clocks = <&pll1_div2_clk>;
 853                         #clock-cells = <0>;
 854                         clock-output-names = "sd3";
 855                 };
 856                 mmc0_clk: mmc0_clk@e6150240 {
 857                         compatible = "renesas,r8a7793-div6-clock",
 858                                      "renesas,cpg-div6-clock";
 859                         reg = <0 0xe6150240 0 4>;
 860                         clocks = <&pll1_div2_clk>;
 861                         #clock-cells = <0>;
 862                         clock-output-names = "mmc0";
 863                 };
 864
 865                 /* Fixed factor clocks */
 866                 pll1_div2_clk: pll1_div2_clk {
 867                         compatible = "fixed-factor-clock";
 868                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 869                         #clock-cells = <0>;
 870                         clock-div = <2>;
 871                         clock-mult = <1>;
 872                         clock-output-names = "pll1_div2";
 873                 };
 874                 zg_clk: zg_clk {
 875                         compatible = "fixed-factor-clock";
 876                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 877                         #clock-cells = <0>;
 878                         clock-div = <5>;
 879                         clock-mult = <1>;
 880                         clock-output-names = "zg";
 881                 };
 882                 zx_clk: zx_clk {
 883                         compatible = "fixed-factor-clock";
 884                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 885                         #clock-cells = <0>;
 886                         clock-div = <3>;
 887                         clock-mult = <1>;
 888                         clock-output-names = "zx";
 889                 };
 890                 zs_clk: zs_clk {
 891                         compatible = "fixed-factor-clock";
 892                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 893                         #clock-cells = <0>;
 894                         clock-div = <6>;
 895                         clock-mult = <1>;
 896                         clock-output-names = "zs";
 897                 };
 898                 hp_clk: hp_clk {
 899                         compatible = "fixed-factor-clock";
 900                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 901                         #clock-cells = <0>;
 902                         clock-div = <12>;
 903                         clock-mult = <1>;
 904                         clock-output-names = "hp";
 905                 };
 906                 p_clk: p_clk {
 907                         compatible = "fixed-factor-clock";
 908                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 909                         #clock-cells = <0>;
 910                         clock-div = <24>;
 911                         clock-mult = <1>;
 912                         clock-output-names = "p";
 913                 };
 914                 m2_clk: m2_clk {
 915                         compatible = "fixed-factor-clock";
 916                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 917                         #clock-cells = <0>;
 918                         clock-div = <8>;
 919                         clock-mult = <1>;
 920                         clock-output-names = "m2";
 921                 };
 922                 rclk_clk: rclk_clk {
 923                         compatible = "fixed-factor-clock";
 924                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 925                         #clock-cells = <0>;
 926                         clock-div = <(48 * 1024)>;
 927                         clock-mult = <1>;
 928                         clock-output-names = "rclk";
 929                 };
 930                 mp_clk: mp_clk {
 931                         compatible = "fixed-factor-clock";
 932                         clocks = <&pll1_div2_clk>;
 933                         #clock-cells = <0>;
 934                         clock-div = <15>;
 935                         clock-mult = <1>;
 936                         clock-output-names = "mp";
 937                 };
 938                 cp_clk: cp_clk {
 939                         compatible = "fixed-factor-clock";
 940                         clocks = <&extal_clk>;
 941                         #clock-cells = <0>;
 942                         clock-div = <2>;
 943                         clock-mult = <1>;
 944                         clock-output-names = "cp";
 945                 };
 946
 947                 /* Gate clocks */
 948                 mstp1_clks: mstp1_clks@e6150134 {
 949                         compatible = "renesas,r8a7793-mstp-clocks",
 950                                      "renesas,cpg-mstp-clocks";
 951                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 952                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 953                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 954                                  <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 955                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
 956                         #clock-cells = <1>;
 957                         clock-indices = <
 958                                 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
 959                                 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
 960                                 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
 961                                 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
 962                                 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
 963                                 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
 964                                 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
 965                                 R8A7793_CLK_VSP1_S
 966                         >;
 967                         clock-output-names =
 968                                 "vcp0", "vpc0", "ssp_dev", "tmu1",
 969                                 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
 970                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 971                                 "vsp1-du0", "vsps";
 972                 };
 973                 mstp2_clks: mstp2_clks@e6150138 {
 974                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 975                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 976                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 977                                  <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
 978                         #clock-cells = <1>;
 979                         clock-indices = <
 980                                 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
 981                                 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
 982                                 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
 983                         >;
 984                         clock-output-names =
 985                                 "scifa2", "scifa1", "scifa0", "scifb0",
 986                                 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
 987                 };
 988                 mstp3_clks: mstp3_clks@e615013c {
 989                         compatible = "renesas,r8a7793-mstp-clocks",
 990                                      "renesas,cpg-mstp-clocks";
 991                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 992                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
 993                                  <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
 994                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
 995                                  <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 996                         #clock-cells = <1>;
 997                         clock-indices = <
 998                                 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
 999                                 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1000                                 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1001                                 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1002                                 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1003                                 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1004                         >;
1005                         clock-output-names =
1006                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1007                                 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1008                                 "usbdmac0", "usbdmac1";
1009                 };
1010                 mstp4_clks: mstp4_clks@e6150140 {
1011                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1012                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1013                         clocks = <&cp_clk>;
1014                         #clock-cells = <1>;
1015                         clock-indices = <R8A7793_CLK_IRQC>;
1016                         clock-output-names = "irqc";
1017                 };
1018                 mstp5_clks: mstp5_clks@e6150144 {
1019                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1020                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1021                         clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1022                         #clock-cells = <1>;
1023                         clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1024                                          R8A7793_CLK_THERMAL>;
1025                         clock-output-names = "audmac0", "audmac1", "thermal";
1026                 };
1027                 mstp7_clks: mstp7_clks@e615014c {
1028                         compatible = "renesas,r8a7793-mstp-clocks",
1029                                      "renesas,cpg-mstp-clocks";
1030                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1031                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
1032                                  <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1033                                  <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1034                                  <&zx_clk>, <&zx_clk>;
1035                         #clock-cells = <1>;
1036                         clock-indices = <
1037                                 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1038                                 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1039                                 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1040                                 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1041                                 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1042                                 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1043                                 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1044                         >;
1045                         clock-output-names =
1046                                 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1047                                 "hscif1", "hscif0", "scif3", "scif2",
1048                                 "scif1", "scif0", "du1", "du0", "lvds0";
1049                 };
1050                 mstp8_clks: mstp8_clks@e6150990 {
1051                         compatible = "renesas,r8a7793-mstp-clocks",
1052                                      "renesas,cpg-mstp-clocks";
1053                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1054                         clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1055                                  <&p_clk>, <&zs_clk>, <&zs_clk>;
1056                         #clock-cells = <1>;
1057                         clock-indices = <
1058                                 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1059                                 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1060                                 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1061                                 R8A7793_CLK_SATA0
1062                         >;
1063                         clock-output-names =
1064                                 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1065                                 "sata1", "sata0";
1066                 };
1067                 mstp9_clks: mstp9_clks@e6150994 {
1068                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1069                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1070                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1071                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1072                                  <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1073                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1074                                  <&hp_clk>, <&hp_clk>;
1075                         #clock-cells = <1>;
1076                         clock-indices = <
1077                                 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1078                                 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1079                                 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1080                                 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1081                                 R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
1082                                 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1083                                 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1084                                 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1085                         >;
1086                         clock-output-names =
1087                                 "gpio7", "gpio6", "gpio5", "gpio4",
1088                                 "gpio3", "gpio2", "gpio1", "gpio0",
1089                                 "qspi_mod", "i2c5", "i2c6", "i2c4",
1090                                 "i2c3", "i2c2", "i2c1", "i2c0";
1091                 };
1092                 mstp10_clks: mstp10_clks@e6150998 {
1093                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1094                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1095                         clocks = <&p_clk>,
1096                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1097                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1098                                 <&p_clk>,
1099                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1100                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1101                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1102                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1103                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1104                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1105                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1106
1107                         #clock-cells = <1>;
1108                         clock-indices = <
1109                                 R8A7793_CLK_SSI_ALL
1110                                 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1111                                 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1112                                 R8A7793_CLK_SCU_ALL
1113                                 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1114                                 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1115                                 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1116                                 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1117                         >;
1118                         clock-output-names =
1119                                 "ssi-all",
1120                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1121                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1122                                 "scu-all",
1123                                 "scu-dvc1", "scu-dvc0",
1124                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1125                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1126                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1127                 };
1128                 mstp11_clks: mstp11_clks@e615099c {
1129                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1130                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1131                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1132                         #clock-cells = <1>;
1133                         clock-indices = <
1134                                 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1135                         >;
1136                         clock-output-names = "scifa3", "scifa4", "scifa5";
1137                 };
1138         };
1139
1140         ipmmu_sy0: mmu@e6280000 {
1141                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1142                 reg = <0 0xe6280000 0 0x1000>;
1143                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1144                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1145                 #iommu-cells = <1>;
1146                 status = "disabled";
1147         };
1148
1149         ipmmu_sy1: mmu@e6290000 {
1150                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1151                 reg = <0 0xe6290000 0 0x1000>;
1152                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1153                 #iommu-cells = <1>;
1154                 status = "disabled";
1155         };
1156
1157         ipmmu_ds: mmu@e6740000 {
1158                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1159                 reg = <0 0xe6740000 0 0x1000>;
1160                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1161                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1162                 #iommu-cells = <1>;
1163                 status = "disabled";
1164         };
1165
1166         ipmmu_mp: mmu@ec680000 {
1167                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1168                 reg = <0 0xec680000 0 0x1000>;
1169                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1170                 #iommu-cells = <1>;
1171                 status = "disabled";
1172         };
1173
1174         ipmmu_mx: mmu@fe951000 {
1175                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1176                 reg = <0 0xfe951000 0 0x1000>;
1177                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1178                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1179                 #iommu-cells = <1>;
1180                 status = "disabled";
1181         };
1182
1183         ipmmu_rt: mmu@ffc80000 {
1184                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1185                 reg = <0 0xffc80000 0 0x1000>;
1186                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1187                 #iommu-cells = <1>;
1188                 status = "disabled";
1189         };
1190
1191         ipmmu_gp: mmu@e62a0000 {
1192                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1193                 reg = <0 0xe62a0000 0 0x1000>;
1194                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1195                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1196                 #iommu-cells = <1>;
1197                 status = "disabled";
1198         };
1199
1200         rcar_sound: sound@ec500000 {
1201                 /*
1202                  * #sound-dai-cells is required
1203                  *
1204                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1205                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1206                  */
1207                 compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1208                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1209                         <0 0xec5a0000 0 0x100>,  /* ADG */
1210                         <0 0xec540000 0 0x1000>, /* SSIU */
1211                         <0 0xec541000 0 0x280>,  /* SSI */
1212                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1213                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1214
1215                 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1216                         <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1217                         <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1218                         <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1219                         <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1220                         <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1221                         <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1222                         <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1223                         <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1224                         <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1225                         <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1226                         <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1227                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1228                 clock-names = "ssi-all",
1229                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1230                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1231                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1232                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1233                                 "dvc.0", "dvc.1",
1234                                 "clk_a", "clk_b", "clk_c", "clk_i";
1235                 power-domains = <&cpg_clocks>;
1236
1237                 status = "disabled";
1238
1239                 rcar_sound,dvc {
1240                         dvc0: dvc@0 {
1241                                 dmas = <&audma0 0xbc>;
1242                                 dma-names = "tx";
1243                         };
1244                         dvc1: dvc@1 {
1245                                 dmas = <&audma0 0xbe>;
1246                                 dma-names = "tx";
1247                         };
1248                 };
1249
1250                 rcar_sound,src {
1251                         src0: src@0 {
1252                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1253                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1254                                 dma-names = "rx", "tx";
1255                         };
1256                         src1: src@1 {
1257                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1258                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1259                                 dma-names = "rx", "tx";
1260                         };
1261                         src2: src@2 {
1262                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1263                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1264                                 dma-names = "rx", "tx";
1265                         };
1266                         src3: src@3 {
1267                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1268                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1269                                 dma-names = "rx", "tx";
1270                         };
1271                         src4: src@4 {
1272                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1273                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1274                                 dma-names = "rx", "tx";
1275                         };
1276                         src5: src@5 {
1277                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1278                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1279                                 dma-names = "rx", "tx";
1280                         };
1281                         src6: src@6 {
1282                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1283                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1284                                 dma-names = "rx", "tx";
1285                         };
1286                         src7: src@7 {
1287                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1288                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1289                                 dma-names = "rx", "tx";
1290                         };
1291                         src8: src@8 {
1292                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1293                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1294                                 dma-names = "rx", "tx";
1295                         };
1296                         src9: src@9 {
1297                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1298                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1299                                 dma-names = "rx", "tx";
1300                         };
1301                 };
1302
1303                 rcar_sound,ssi {
1304                         ssi0: ssi@0 {
1305                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1306                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1307                                 dma-names = "rx", "tx", "rxu", "txu";
1308                         };
1309                         ssi1: ssi@1 {
1310                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1311                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1312                                 dma-names = "rx", "tx", "rxu", "txu";
1313                         };
1314                         ssi2: ssi@2 {
1315                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1316                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1317                                 dma-names = "rx", "tx", "rxu", "txu";
1318                         };
1319                         ssi3: ssi@3 {
1320                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1321                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1322                                 dma-names = "rx", "tx", "rxu", "txu";
1323                         };
1324                         ssi4: ssi@4 {
1325                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1326                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1327                                 dma-names = "rx", "tx", "rxu", "txu";
1328                         };
1329                         ssi5: ssi@5 {
1330                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1331                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1332                                 dma-names = "rx", "tx", "rxu", "txu";
1333                         };
1334                         ssi6: ssi@6 {
1335                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1336                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1337                                 dma-names = "rx", "tx", "rxu", "txu";
1338                         };
1339                         ssi7: ssi@7 {
1340                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1341                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1342                                 dma-names = "rx", "tx", "rxu", "txu";
1343                         };
1344                         ssi8: ssi@8 {
1345                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1346                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1347                                 dma-names = "rx", "tx", "rxu", "txu";
1348                         };
1349                         ssi9: ssi@9 {
1350                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1351                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1352                                 dma-names = "rx", "tx", "rxu", "txu";
1353                         };
1354                 };
1355         };
1356 };