2 * Device Tree Source for the r8a7793 SoC
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7793-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,r8a7793";
17 interrupt-parent = <&gic>;
40 compatible = "arm,cortex-a15";
42 clock-frequency = <1500000000>;
43 voltage-tolerance = <1>; /* 1% */
44 clocks = <&cpg_clocks R8A7793_CLK_Z>;
45 clock-latency = <300000>; /* 300 us */
47 /* kHz - uV - OPPs unknown yet */
48 operating-points = <1500000 1000000>,
54 next-level-cache = <&L2_CA15>;
59 cpu_thermal: cpu-thermal {
60 polling-delay-passive = <0>;
63 thermal-sensors = <&thermal>;
67 temperature = <115000>;
77 L2_CA15: cache-controller@0 {
83 gic: interrupt-controller@f1001000 {
84 compatible = "arm,gic-400";
85 #interrupt-cells = <3>;
88 reg = <0 0xf1001000 0 0x1000>,
89 <0 0xf1002000 0 0x1000>,
90 <0 0xf1004000 0 0x2000>,
91 <0 0xf1006000 0 0x2000>;
92 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
95 gpio0: gpio@e6050000 {
96 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
97 reg = <0 0xe6050000 0 0x50>;
98 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
101 gpio-ranges = <&pfc 0 0 32>;
102 #interrupt-cells = <2>;
103 interrupt-controller;
104 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
105 power-domains = <&cpg_clocks>;
108 gpio1: gpio@e6051000 {
109 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
110 reg = <0 0xe6051000 0 0x50>;
111 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
114 gpio-ranges = <&pfc 0 32 26>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
117 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
118 power-domains = <&cpg_clocks>;
121 gpio2: gpio@e6052000 {
122 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
123 reg = <0 0xe6052000 0 0x50>;
124 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
127 gpio-ranges = <&pfc 0 64 32>;
128 #interrupt-cells = <2>;
129 interrupt-controller;
130 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
131 power-domains = <&cpg_clocks>;
134 gpio3: gpio@e6053000 {
135 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
136 reg = <0 0xe6053000 0 0x50>;
137 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
140 gpio-ranges = <&pfc 0 96 32>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
143 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
144 power-domains = <&cpg_clocks>;
147 gpio4: gpio@e6054000 {
148 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
149 reg = <0 0xe6054000 0 0x50>;
150 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
153 gpio-ranges = <&pfc 0 128 32>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
157 power-domains = <&cpg_clocks>;
160 gpio5: gpio@e6055000 {
161 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
162 reg = <0 0xe6055000 0 0x50>;
163 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
166 gpio-ranges = <&pfc 0 160 32>;
167 #interrupt-cells = <2>;
168 interrupt-controller;
169 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
170 power-domains = <&cpg_clocks>;
173 gpio6: gpio@e6055400 {
174 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
175 reg = <0 0xe6055400 0 0x50>;
176 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
179 gpio-ranges = <&pfc 0 192 32>;
180 #interrupt-cells = <2>;
181 interrupt-controller;
182 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
183 power-domains = <&cpg_clocks>;
186 gpio7: gpio@e6055800 {
187 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
188 reg = <0 0xe6055800 0 0x50>;
189 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
192 gpio-ranges = <&pfc 0 224 26>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
195 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
196 power-domains = <&cpg_clocks>;
199 thermal: thermal@e61f0000 {
200 compatible = "renesas,thermal-r8a7793",
201 "renesas,rcar-gen2-thermal",
202 "renesas,rcar-thermal";
203 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
204 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
206 power-domains = <&cpg_clocks>;
207 #thermal-sensor-cells = <0>;
211 compatible = "arm,armv7-timer";
212 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
213 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
214 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
215 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
218 cmt0: timer@ffca0000 {
219 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
220 reg = <0 0xffca0000 0 0x1004>;
221 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
225 power-domains = <&cpg_clocks>;
227 renesas,channels-mask = <0x60>;
232 cmt1: timer@e6130000 {
233 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
234 reg = <0 0xe6130000 0 0x1004>;
235 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
245 power-domains = <&cpg_clocks>;
247 renesas,channels-mask = <0xff>;
252 irqc0: interrupt-controller@e61c0000 {
253 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 reg = <0 0xe61c0000 0 0x200>;
257 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
268 power-domains = <&cpg_clocks>;
271 dmac0: dma-controller@e6700000 {
272 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
273 reg = <0 0xe6700000 0 0x20000>;
274 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
282 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
283 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
284 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
285 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
286 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
287 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
288 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "error",
291 "ch0", "ch1", "ch2", "ch3",
292 "ch4", "ch5", "ch6", "ch7",
293 "ch8", "ch9", "ch10", "ch11",
294 "ch12", "ch13", "ch14";
295 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
297 power-domains = <&cpg_clocks>;
302 dmac1: dma-controller@e6720000 {
303 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
304 reg = <0 0xe6720000 0 0x20000>;
305 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-names = "error",
322 "ch0", "ch1", "ch2", "ch3",
323 "ch4", "ch5", "ch6", "ch7",
324 "ch8", "ch9", "ch10", "ch11",
325 "ch12", "ch13", "ch14";
326 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
328 power-domains = <&cpg_clocks>;
333 audma0: dma-controller@ec700000 {
334 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
335 reg = <0 0xec700000 0 0x10000>;
336 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "error",
351 "ch0", "ch1", "ch2", "ch3",
352 "ch4", "ch5", "ch6", "ch7",
353 "ch8", "ch9", "ch10", "ch11",
355 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
357 power-domains = <&cpg_clocks>;
362 audma1: dma-controller@ec720000 {
363 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
364 reg = <0 0xec720000 0 0x10000>;
365 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-names = "error",
380 "ch0", "ch1", "ch2", "ch3",
381 "ch4", "ch5", "ch6", "ch7",
382 "ch8", "ch9", "ch10", "ch11",
384 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
386 power-domains = <&cpg_clocks>;
391 /* The memory map in the User's Manual maps the cores to bus numbers */
393 #address-cells = <1>;
395 compatible = "renesas,i2c-r8a7793";
396 reg = <0 0xe6508000 0 0x40>;
397 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
399 power-domains = <&cpg_clocks>;
400 i2c-scl-internal-delay-ns = <6>;
405 #address-cells = <1>;
407 compatible = "renesas,i2c-r8a7793";
408 reg = <0 0xe6518000 0 0x40>;
409 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
411 power-domains = <&cpg_clocks>;
412 i2c-scl-internal-delay-ns = <6>;
417 #address-cells = <1>;
419 compatible = "renesas,i2c-r8a7793";
420 reg = <0 0xe6530000 0 0x40>;
421 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
423 power-domains = <&cpg_clocks>;
424 i2c-scl-internal-delay-ns = <6>;
429 #address-cells = <1>;
431 compatible = "renesas,i2c-r8a7793";
432 reg = <0 0xe6540000 0 0x40>;
433 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
435 power-domains = <&cpg_clocks>;
436 i2c-scl-internal-delay-ns = <6>;
441 #address-cells = <1>;
443 compatible = "renesas,i2c-r8a7793";
444 reg = <0 0xe6520000 0 0x40>;
445 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
447 power-domains = <&cpg_clocks>;
448 i2c-scl-internal-delay-ns = <6>;
453 /* doesn't need pinmux */
454 #address-cells = <1>;
456 compatible = "renesas,i2c-r8a7793";
457 reg = <0 0xe6528000 0 0x40>;
458 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
460 power-domains = <&cpg_clocks>;
461 i2c-scl-internal-delay-ns = <110>;
466 /* doesn't need pinmux */
467 #address-cells = <1>;
469 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
470 reg = <0 0xe60b0000 0 0x425>;
471 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
473 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
474 dma-names = "tx", "rx";
475 power-domains = <&cpg_clocks>;
480 #address-cells = <1>;
482 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
483 reg = <0 0xe6500000 0 0x425>;
484 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
486 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
487 dma-names = "tx", "rx";
488 power-domains = <&cpg_clocks>;
493 #address-cells = <1>;
495 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
496 reg = <0 0xe6510000 0 0x425>;
497 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
499 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
500 dma-names = "tx", "rx";
501 power-domains = <&cpg_clocks>;
506 compatible = "renesas,pfc-r8a7793";
507 reg = <0 0xe6060000 0 0x250>;
510 scifa0: serial@e6c40000 {
511 compatible = "renesas,scifa-r8a7793",
512 "renesas,rcar-gen2-scifa", "renesas,scifa";
513 reg = <0 0xe6c40000 0 64>;
514 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
517 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
518 dma-names = "tx", "rx";
519 power-domains = <&cpg_clocks>;
523 scifa1: serial@e6c50000 {
524 compatible = "renesas,scifa-r8a7793",
525 "renesas,rcar-gen2-scifa", "renesas,scifa";
526 reg = <0 0xe6c50000 0 64>;
527 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
530 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
531 dma-names = "tx", "rx";
532 power-domains = <&cpg_clocks>;
536 scifa2: serial@e6c60000 {
537 compatible = "renesas,scifa-r8a7793",
538 "renesas,rcar-gen2-scifa", "renesas,scifa";
539 reg = <0 0xe6c60000 0 64>;
540 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
543 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
544 dma-names = "tx", "rx";
545 power-domains = <&cpg_clocks>;
549 scifa3: serial@e6c70000 {
550 compatible = "renesas,scifa-r8a7793",
551 "renesas,rcar-gen2-scifa", "renesas,scifa";
552 reg = <0 0xe6c70000 0 64>;
553 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
556 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
557 dma-names = "tx", "rx";
558 power-domains = <&cpg_clocks>;
562 scifa4: serial@e6c78000 {
563 compatible = "renesas,scifa-r8a7793",
564 "renesas,rcar-gen2-scifa", "renesas,scifa";
565 reg = <0 0xe6c78000 0 64>;
566 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
569 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
570 dma-names = "tx", "rx";
571 power-domains = <&cpg_clocks>;
575 scifa5: serial@e6c80000 {
576 compatible = "renesas,scifa-r8a7793",
577 "renesas,rcar-gen2-scifa", "renesas,scifa";
578 reg = <0 0xe6c80000 0 64>;
579 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
582 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
583 dma-names = "tx", "rx";
584 power-domains = <&cpg_clocks>;
588 scifb0: serial@e6c20000 {
589 compatible = "renesas,scifb-r8a7793",
590 "renesas,rcar-gen2-scifb", "renesas,scifb";
591 reg = <0 0xe6c20000 0 64>;
592 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
595 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
596 dma-names = "tx", "rx";
597 power-domains = <&cpg_clocks>;
601 scifb1: serial@e6c30000 {
602 compatible = "renesas,scifb-r8a7793",
603 "renesas,rcar-gen2-scifb", "renesas,scifb";
604 reg = <0 0xe6c30000 0 64>;
605 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
608 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
609 dma-names = "tx", "rx";
610 power-domains = <&cpg_clocks>;
614 scifb2: serial@e6ce0000 {
615 compatible = "renesas,scifb-r8a7793",
616 "renesas,rcar-gen2-scifb", "renesas,scifb";
617 reg = <0 0xe6ce0000 0 64>;
618 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
621 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
622 dma-names = "tx", "rx";
623 power-domains = <&cpg_clocks>;
627 scif0: serial@e6e60000 {
628 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
630 reg = <0 0xe6e60000 0 64>;
631 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
634 clock-names = "fck", "brg_int", "scif_clk";
635 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
636 dma-names = "tx", "rx";
637 power-domains = <&cpg_clocks>;
641 scif1: serial@e6e68000 {
642 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
644 reg = <0 0xe6e68000 0 64>;
645 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
648 clock-names = "fck", "brg_int", "scif_clk";
649 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
650 dma-names = "tx", "rx";
651 power-domains = <&cpg_clocks>;
655 scif2: serial@e6e58000 {
656 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
658 reg = <0 0xe6e58000 0 64>;
659 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
662 clock-names = "fck", "brg_int", "scif_clk";
663 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
664 dma-names = "tx", "rx";
665 power-domains = <&cpg_clocks>;
669 scif3: serial@e6ea8000 {
670 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
672 reg = <0 0xe6ea8000 0 64>;
673 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
676 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
678 dma-names = "tx", "rx";
679 power-domains = <&cpg_clocks>;
683 scif4: serial@e6ee0000 {
684 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
686 reg = <0 0xe6ee0000 0 64>;
687 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
690 clock-names = "fck", "brg_int", "scif_clk";
691 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
692 dma-names = "tx", "rx";
693 power-domains = <&cpg_clocks>;
697 scif5: serial@e6ee8000 {
698 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
700 reg = <0 0xe6ee8000 0 64>;
701 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
704 clock-names = "fck", "brg_int", "scif_clk";
705 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
706 dma-names = "tx", "rx";
707 power-domains = <&cpg_clocks>;
711 hscif0: serial@e62c0000 {
712 compatible = "renesas,hscif-r8a7793",
713 "renesas,rcar-gen2-hscif", "renesas,hscif";
714 reg = <0 0xe62c0000 0 96>;
715 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
718 clock-names = "fck", "brg_int", "scif_clk";
719 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
720 dma-names = "tx", "rx";
721 power-domains = <&cpg_clocks>;
725 hscif1: serial@e62c8000 {
726 compatible = "renesas,hscif-r8a7793",
727 "renesas,rcar-gen2-hscif", "renesas,hscif";
728 reg = <0 0xe62c8000 0 96>;
729 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
732 clock-names = "fck", "brg_int", "scif_clk";
733 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
734 dma-names = "tx", "rx";
735 power-domains = <&cpg_clocks>;
739 hscif2: serial@e62d0000 {
740 compatible = "renesas,hscif-r8a7793",
741 "renesas,rcar-gen2-hscif", "renesas,hscif";
742 reg = <0 0xe62d0000 0 96>;
743 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
746 clock-names = "fck", "brg_int", "scif_clk";
747 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
748 dma-names = "tx", "rx";
749 power-domains = <&cpg_clocks>;
753 ether: ethernet@ee700000 {
754 compatible = "renesas,ether-r8a7793";
755 reg = <0 0xee700000 0 0x400>;
756 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
758 power-domains = <&cpg_clocks>;
760 #address-cells = <1>;
766 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
767 reg = <0 0xe6b10000 0 0x2c>;
768 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
770 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
771 dma-names = "tx", "rx";
772 power-domains = <&cpg_clocks>;
774 #address-cells = <1>;
779 du: display@feb00000 {
780 compatible = "renesas,du-r8a7793";
781 reg = <0 0xfeb00000 0 0x40000>,
782 <0 0xfeb90000 0 0x1c>;
783 reg-names = "du", "lvds.0";
784 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
787 <&mstp7_clks R8A7793_CLK_DU1>,
788 <&mstp7_clks R8A7793_CLK_LVDS0>;
789 clock-names = "du.0", "du.1", "lvds.0";
793 #address-cells = <1>;
798 du_out_rgb: endpoint {
803 du_out_lvds0: endpoint {
810 #address-cells = <2>;
814 /* External root clock */
816 compatible = "fixed-clock";
818 /* This value must be overridden by the board. */
819 clock-frequency = <0>;
823 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
824 * default. Boards that provide audio clocks should override them.
826 audio_clk_a: audio_clk_a {
827 compatible = "fixed-clock";
829 clock-frequency = <0>;
831 audio_clk_b: audio_clk_b {
832 compatible = "fixed-clock";
834 clock-frequency = <0>;
836 audio_clk_c: audio_clk_c {
837 compatible = "fixed-clock";
839 clock-frequency = <0>;
842 /* External SCIF clock */
844 compatible = "fixed-clock";
846 /* This value must be overridden by the board. */
847 clock-frequency = <0>;
851 /* Special CPG clocks */
852 cpg_clocks: cpg_clocks@e6150000 {
853 compatible = "renesas,r8a7793-cpg-clocks",
854 "renesas,rcar-gen2-cpg-clocks";
855 reg = <0 0xe6150000 0 0x1000>;
856 clocks = <&extal_clk>;
858 clock-output-names = "main", "pll0", "pll1", "pll3",
859 "lb", "qspi", "sdh", "sd0", "z",
861 #power-domain-cells = <0>;
864 /* Variable factor clocks */
865 sd2_clk: sd2@e6150078 {
866 compatible = "renesas,r8a7793-div6-clock",
867 "renesas,cpg-div6-clock";
868 reg = <0 0xe6150078 0 4>;
869 clocks = <&pll1_div2_clk>;
872 sd3_clk: sd3@e615026c {
873 compatible = "renesas,r8a7793-div6-clock",
874 "renesas,cpg-div6-clock";
875 reg = <0 0xe615026c 0 4>;
876 clocks = <&pll1_div2_clk>;
879 mmc0_clk: mmc0@e6150240 {
880 compatible = "renesas,r8a7793-div6-clock",
881 "renesas,cpg-div6-clock";
882 reg = <0 0xe6150240 0 4>;
883 clocks = <&pll1_div2_clk>;
887 /* Fixed factor clocks */
888 pll1_div2_clk: pll1_div2 {
889 compatible = "fixed-factor-clock";
890 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
896 compatible = "fixed-factor-clock";
897 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
903 compatible = "fixed-factor-clock";
904 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
910 compatible = "fixed-factor-clock";
911 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
917 compatible = "fixed-factor-clock";
918 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
924 compatible = "fixed-factor-clock";
925 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
931 compatible = "fixed-factor-clock";
932 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
938 compatible = "fixed-factor-clock";
939 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
941 clock-div = <(48 * 1024)>;
945 compatible = "fixed-factor-clock";
946 clocks = <&pll1_div2_clk>;
952 compatible = "fixed-factor-clock";
953 clocks = <&extal_clk>;
960 mstp1_clks: mstp1_clks@e6150134 {
961 compatible = "renesas,r8a7793-mstp-clocks",
962 "renesas,cpg-mstp-clocks";
963 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
964 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
965 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
966 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
967 <&zs_clk>, <&zs_clk>, <&zs_clk>;
970 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
971 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
972 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
973 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
974 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
975 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
976 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
980 "vcp0", "vpc0", "ssp_dev", "tmu1",
981 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
982 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
985 mstp2_clks: mstp2_clks@e6150138 {
986 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
987 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
988 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
989 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
992 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
993 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
994 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
997 "scifa2", "scifa1", "scifa0", "scifb0",
998 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1000 mstp3_clks: mstp3_clks@e615013c {
1001 compatible = "renesas,r8a7793-mstp-clocks",
1002 "renesas,cpg-mstp-clocks";
1003 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1004 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1005 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1006 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1007 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1010 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1011 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1012 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1013 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1014 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1015 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1017 clock-output-names =
1018 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1019 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1020 "usbdmac0", "usbdmac1";
1022 mstp4_clks: mstp4_clks@e6150140 {
1023 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1024 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1027 clock-indices = <R8A7793_CLK_IRQC>;
1028 clock-output-names = "irqc";
1030 mstp5_clks: mstp5_clks@e6150144 {
1031 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1032 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1033 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1035 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1036 R8A7793_CLK_THERMAL>;
1037 clock-output-names = "audmac0", "audmac1", "thermal";
1039 mstp7_clks: mstp7_clks@e615014c {
1040 compatible = "renesas,r8a7793-mstp-clocks",
1041 "renesas,cpg-mstp-clocks";
1042 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1043 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
1044 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1045 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1046 <&zx_clk>, <&zx_clk>;
1049 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1050 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1051 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1052 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1053 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1054 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1055 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1057 clock-output-names =
1058 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1059 "hscif1", "hscif0", "scif3", "scif2",
1060 "scif1", "scif0", "du1", "du0", "lvds0";
1062 mstp8_clks: mstp8_clks@e6150990 {
1063 compatible = "renesas,r8a7793-mstp-clocks",
1064 "renesas,cpg-mstp-clocks";
1065 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1066 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1067 <&p_clk>, <&zs_clk>, <&zs_clk>;
1070 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1071 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1072 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1075 clock-output-names =
1076 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1079 mstp9_clks: mstp9_clks@e6150994 {
1080 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1081 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1082 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1083 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1084 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1085 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1086 <&hp_clk>, <&hp_clk>;
1089 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1090 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1091 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1092 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1093 R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
1094 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1095 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1096 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1098 clock-output-names =
1099 "gpio7", "gpio6", "gpio5", "gpio4",
1100 "gpio3", "gpio2", "gpio1", "gpio0",
1101 "qspi_mod", "i2c5", "i2c6", "i2c4",
1102 "i2c3", "i2c2", "i2c1", "i2c0";
1104 mstp10_clks: mstp10_clks@e6150998 {
1105 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1106 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1108 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1109 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1111 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1112 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1113 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1114 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1115 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1116 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1117 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1122 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1123 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1125 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1126 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1127 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1128 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1130 clock-output-names =
1132 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1133 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1135 "scu-dvc1", "scu-dvc0",
1136 "scu-ctu1-mix1", "scu-ctu0-mix0",
1137 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1138 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1140 mstp11_clks: mstp11_clks@e615099c {
1141 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1142 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1143 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1146 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1148 clock-output-names = "scifa3", "scifa4", "scifa5";
1152 ipmmu_sy0: mmu@e6280000 {
1153 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1154 reg = <0 0xe6280000 0 0x1000>;
1155 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1158 status = "disabled";
1161 ipmmu_sy1: mmu@e6290000 {
1162 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1163 reg = <0 0xe6290000 0 0x1000>;
1164 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1166 status = "disabled";
1169 ipmmu_ds: mmu@e6740000 {
1170 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1171 reg = <0 0xe6740000 0 0x1000>;
1172 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1175 status = "disabled";
1178 ipmmu_mp: mmu@ec680000 {
1179 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1180 reg = <0 0xec680000 0 0x1000>;
1181 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1183 status = "disabled";
1186 ipmmu_mx: mmu@fe951000 {
1187 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1188 reg = <0 0xfe951000 0 0x1000>;
1189 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1192 status = "disabled";
1195 ipmmu_rt: mmu@ffc80000 {
1196 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1197 reg = <0 0xffc80000 0 0x1000>;
1198 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1200 status = "disabled";
1203 ipmmu_gp: mmu@e62a0000 {
1204 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1205 reg = <0 0xe62a0000 0 0x1000>;
1206 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1209 status = "disabled";
1212 rcar_sound: sound@ec500000 {
1214 * #sound-dai-cells is required
1216 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1217 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1219 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1220 reg = <0 0xec500000 0 0x1000>, /* SCU */
1221 <0 0xec5a0000 0 0x100>, /* ADG */
1222 <0 0xec540000 0 0x1000>, /* SSIU */
1223 <0 0xec541000 0 0x280>, /* SSI */
1224 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1225 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1227 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1228 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1229 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1230 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1231 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1232 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1233 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1234 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1235 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1236 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1237 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1238 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1239 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1240 clock-names = "ssi-all",
1241 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1242 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1243 "src.9", "src.8", "src.7", "src.6", "src.5",
1244 "src.4", "src.3", "src.2", "src.1", "src.0",
1246 "clk_a", "clk_b", "clk_c", "clk_i";
1247 power-domains = <&cpg_clocks>;
1249 status = "disabled";
1253 dmas = <&audma0 0xbc>;
1257 dmas = <&audma0 0xbe>;
1264 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1265 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1266 dma-names = "rx", "tx";
1269 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1270 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1271 dma-names = "rx", "tx";
1274 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1275 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1276 dma-names = "rx", "tx";
1279 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1280 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1281 dma-names = "rx", "tx";
1284 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1285 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1286 dma-names = "rx", "tx";
1289 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1290 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1291 dma-names = "rx", "tx";
1294 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1295 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1296 dma-names = "rx", "tx";
1299 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1300 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1301 dma-names = "rx", "tx";
1304 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1305 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1306 dma-names = "rx", "tx";
1309 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1310 dmas = <&audma0 0x97>, <&audma1 0xba>;
1311 dma-names = "rx", "tx";
1317 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1318 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1319 dma-names = "rx", "tx", "rxu", "txu";
1322 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1323 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1324 dma-names = "rx", "tx", "rxu", "txu";
1327 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1328 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1329 dma-names = "rx", "tx", "rxu", "txu";
1332 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1333 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1334 dma-names = "rx", "tx", "rxu", "txu";
1337 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1338 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1339 dma-names = "rx", "tx", "rxu", "txu";
1342 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1343 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1344 dma-names = "rx", "tx", "rxu", "txu";
1347 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1348 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1349 dma-names = "rx", "tx", "rxu", "txu";
1352 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1353 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1354 dma-names = "rx", "tx", "rxu", "txu";
1357 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1358 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1359 dma-names = "rx", "tx", "rxu", "txu";
1362 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1363 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1364 dma-names = "rx", "tx", "rxu", "txu";