arch/arm/boot/dts/r8a7793.dtsi

   1 /*
   2  * Device Tree Source for the r8a7793 SoC
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7793-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r8a7793";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 spi0 = &qspi;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a15";
  32                         reg = <0>;
  33                         clock-frequency = <1500000000>;
  34                         voltage-tolerance = <1>; /* 1% */
  35                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
  36                         clock-latency = <300000>; /* 300 us */
  37
  38                         /* kHz - uV - OPPs unknown yet */
  39                         operating-points = <1500000 1000000>,
  40                                            <1312500 1000000>,
  41                                            <1125000 1000000>,
  42                                            < 937500 1000000>,
  43                                            < 750000 1000000>,
  44                                            < 375000 1000000>;
  45                 };
  46         };
  47
  48         gic: interrupt-controller@f1001000 {
  49                 compatible = "arm,gic-400";
  50                 #interrupt-cells = <3>;
  51                 #address-cells = <0>;
  52                 interrupt-controller;
  53                 reg = <0 0xf1001000 0 0x1000>,
  54                         <0 0xf1002000 0 0x1000>,
  55                         <0 0xf1004000 0 0x2000>,
  56                         <0 0xf1006000 0 0x2000>;
  57                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  58         };
  59
  60         gpio0: gpio@e6050000 {
  61                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  62                 reg = <0 0xe6050000 0 0x50>;
  63                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  64                 #gpio-cells = <2>;
  65                 gpio-controller;
  66                 gpio-ranges = <&pfc 0 0 32>;
  67                 #interrupt-cells = <2>;
  68                 interrupt-controller;
  69                 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
  70                 power-domains = <&cpg_clocks>;
  71         };
  72
  73         gpio1: gpio@e6051000 {
  74                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  75                 reg = <0 0xe6051000 0 0x50>;
  76                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  77                 #gpio-cells = <2>;
  78                 gpio-controller;
  79                 gpio-ranges = <&pfc 0 32 26>;
  80                 #interrupt-cells = <2>;
  81                 interrupt-controller;
  82                 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
  83                 power-domains = <&cpg_clocks>;
  84         };
  85
  86         gpio2: gpio@e6052000 {
  87                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  88                 reg = <0 0xe6052000 0 0x50>;
  89                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  90                 #gpio-cells = <2>;
  91                 gpio-controller;
  92                 gpio-ranges = <&pfc 0 64 32>;
  93                 #interrupt-cells = <2>;
  94                 interrupt-controller;
  95                 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
  96                 power-domains = <&cpg_clocks>;
  97         };
  98
  99         gpio3: gpio@e6053000 {
 100                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 101                 reg = <0 0xe6053000 0 0x50>;
 102                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 103                 #gpio-cells = <2>;
 104                 gpio-controller;
 105                 gpio-ranges = <&pfc 0 96 32>;
 106                 #interrupt-cells = <2>;
 107                 interrupt-controller;
 108                 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
 109                 power-domains = <&cpg_clocks>;
 110         };
 111
 112         gpio4: gpio@e6054000 {
 113                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 114                 reg = <0 0xe6054000 0 0x50>;
 115                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 gpio-ranges = <&pfc 0 128 32>;
 119                 #interrupt-cells = <2>;
 120                 interrupt-controller;
 121                 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
 122                 power-domains = <&cpg_clocks>;
 123         };
 124
 125         gpio5: gpio@e6055000 {
 126                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 127                 reg = <0 0xe6055000 0 0x50>;
 128                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 160 32>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134                 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
 135                 power-domains = <&cpg_clocks>;
 136         };
 137
 138         gpio6: gpio@e6055400 {
 139                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 140                 reg = <0 0xe6055400 0 0x50>;
 141                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 142                 #gpio-cells = <2>;
 143                 gpio-controller;
 144                 gpio-ranges = <&pfc 0 192 32>;
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147                 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
 148                 power-domains = <&cpg_clocks>;
 149         };
 150
 151         gpio7: gpio@e6055800 {
 152                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 153                 reg = <0 0xe6055800 0 0x50>;
 154                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 155                 #gpio-cells = <2>;
 156                 gpio-controller;
 157                 gpio-ranges = <&pfc 0 224 26>;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
 161                 power-domains = <&cpg_clocks>;
 162         };
 163
 164         thermal@e61f0000 {
 165                 compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
 166                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 167                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 168                 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
 169                 power-domains = <&cpg_clocks>;
 170         };
 171
 172         timer {
 173                 compatible = "arm,armv7-timer";
 174                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 175                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 176                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 177                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 178         };
 179
 180         cmt0: timer@ffca0000 {
 181                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 182                 reg = <0 0xffca0000 0 0x1004>;
 183                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 184                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 186                 clock-names = "fck";
 187                 power-domains = <&cpg_clocks>;
 188
 189                 renesas,channels-mask = <0x60>;
 190
 191                 status = "disabled";
 192         };
 193
 194         cmt1: timer@e6130000 {
 195                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 196                 reg = <0 0xe6130000 0 0x1004>;
 197                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 198                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 199                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 200                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 201                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 202                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 203                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 204                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 206                 clock-names = "fck";
 207                 power-domains = <&cpg_clocks>;
 208
 209                 renesas,channels-mask = <0xff>;
 210
 211                 status = "disabled";
 212         };
 213
 214         irqc0: interrupt-controller@e61c0000 {
 215                 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
 216                 #interrupt-cells = <2>;
 217                 interrupt-controller;
 218                 reg = <0 0xe61c0000 0 0x200>;
 219                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 220                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 221                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 222                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 223                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 224                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 225                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 226                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 227                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 228                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
 230                 power-domains = <&cpg_clocks>;
 231         };
 232
 233         pfc: pfc@e6060000 {
 234                 compatible = "renesas,pfc-r8a7793";
 235                 reg = <0 0xe6060000 0 0x250>;
 236         };
 237
 238         dmac0: dma-controller@e6700000 {
 239                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 240                 reg = <0 0xe6700000 0 0x20000>;
 241                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 242                               0 200 IRQ_TYPE_LEVEL_HIGH
 243                               0 201 IRQ_TYPE_LEVEL_HIGH
 244                               0 202 IRQ_TYPE_LEVEL_HIGH
 245                               0 203 IRQ_TYPE_LEVEL_HIGH
 246                               0 204 IRQ_TYPE_LEVEL_HIGH
 247                               0 205 IRQ_TYPE_LEVEL_HIGH
 248                               0 206 IRQ_TYPE_LEVEL_HIGH
 249                               0 207 IRQ_TYPE_LEVEL_HIGH
 250                               0 208 IRQ_TYPE_LEVEL_HIGH
 251                               0 209 IRQ_TYPE_LEVEL_HIGH
 252                               0 210 IRQ_TYPE_LEVEL_HIGH
 253                               0 211 IRQ_TYPE_LEVEL_HIGH
 254                               0 212 IRQ_TYPE_LEVEL_HIGH
 255                               0 213 IRQ_TYPE_LEVEL_HIGH
 256                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 257                 interrupt-names = "error",
 258                                 "ch0", "ch1", "ch2", "ch3",
 259                                 "ch4", "ch5", "ch6", "ch7",
 260                                 "ch8", "ch9", "ch10", "ch11",
 261                                 "ch12", "ch13", "ch14";
 262                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
 263                 clock-names = "fck";
 264                 power-domains = <&cpg_clocks>;
 265                 #dma-cells = <1>;
 266                 dma-channels = <15>;
 267         };
 268
 269         dmac1: dma-controller@e6720000 {
 270                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 271                 reg = <0 0xe6720000 0 0x20000>;
 272                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 273                               0 216 IRQ_TYPE_LEVEL_HIGH
 274                               0 217 IRQ_TYPE_LEVEL_HIGH
 275                               0 218 IRQ_TYPE_LEVEL_HIGH
 276                               0 219 IRQ_TYPE_LEVEL_HIGH
 277                               0 308 IRQ_TYPE_LEVEL_HIGH
 278                               0 309 IRQ_TYPE_LEVEL_HIGH
 279                               0 310 IRQ_TYPE_LEVEL_HIGH
 280                               0 311 IRQ_TYPE_LEVEL_HIGH
 281                               0 312 IRQ_TYPE_LEVEL_HIGH
 282                               0 313 IRQ_TYPE_LEVEL_HIGH
 283                               0 314 IRQ_TYPE_LEVEL_HIGH
 284                               0 315 IRQ_TYPE_LEVEL_HIGH
 285                               0 316 IRQ_TYPE_LEVEL_HIGH
 286                               0 317 IRQ_TYPE_LEVEL_HIGH
 287                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 288                 interrupt-names = "error",
 289                                 "ch0", "ch1", "ch2", "ch3",
 290                                 "ch4", "ch5", "ch6", "ch7",
 291                                 "ch8", "ch9", "ch10", "ch11",
 292                                 "ch12", "ch13", "ch14";
 293                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
 294                 clock-names = "fck";
 295                 power-domains = <&cpg_clocks>;
 296                 #dma-cells = <1>;
 297                 dma-channels = <15>;
 298         };
 299
 300         scifa0: serial@e6c40000 {
 301                 compatible = "renesas,scifa-r8a7793", "renesas,scifa";
 302                 reg = <0 0xe6c40000 0 64>;
 303                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
 305                 clock-names = "sci_ick";
 306                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 307                 dma-names = "tx", "rx";
 308                 power-domains = <&cpg_clocks>;
 309                 status = "disabled";
 310         };
 311
 312         scifa1: serial@e6c50000 {
 313                 compatible = "renesas,scifa-r8a7793", "renesas,scifa";
 314                 reg = <0 0xe6c50000 0 64>;
 315                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
 317                 clock-names = "sci_ick";
 318                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 319                 dma-names = "tx", "rx";
 320                 power-domains = <&cpg_clocks>;
 321                 status = "disabled";
 322         };
 323
 324         scifa2: serial@e6c60000 {
 325                 compatible = "renesas,scifa-r8a7793", "renesas,scifa";
 326                 reg = <0 0xe6c60000 0 64>;
 327                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
 329                 clock-names = "sci_ick";
 330                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 331                 dma-names = "tx", "rx";
 332                 power-domains = <&cpg_clocks>;
 333                 status = "disabled";
 334         };
 335
 336         scifa3: serial@e6c70000 {
 337                 compatible = "renesas,scifa-r8a7793", "renesas,scifa";
 338                 reg = <0 0xe6c70000 0 64>;
 339                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
 341                 clock-names = "sci_ick";
 342                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 343                 dma-names = "tx", "rx";
 344                 power-domains = <&cpg_clocks>;
 345                 status = "disabled";
 346         };
 347
 348         scifa4: serial@e6c78000 {
 349                 compatible = "renesas,scifa-r8a7793", "renesas,scifa";
 350                 reg = <0 0xe6c78000 0 64>;
 351                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
 353                 clock-names = "sci_ick";
 354                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 355                 dma-names = "tx", "rx";
 356                 power-domains = <&cpg_clocks>;
 357                 status = "disabled";
 358         };
 359
 360         scifa5: serial@e6c80000 {
 361                 compatible = "renesas,scifa-r8a7793", "renesas,scifa";
 362                 reg = <0 0xe6c80000 0 64>;
 363                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 364                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
 365                 clock-names = "sci_ick";
 366                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 367                 dma-names = "tx", "rx";
 368                 power-domains = <&cpg_clocks>;
 369                 status = "disabled";
 370         };
 371
 372         scifb0: serial@e6c20000 {
 373                 compatible = "renesas,scifb-r8a7793", "renesas,scifb";
 374                 reg = <0 0xe6c20000 0 64>;
 375                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
 377                 clock-names = "sci_ick";
 378                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 379                 dma-names = "tx", "rx";
 380                 power-domains = <&cpg_clocks>;
 381                 status = "disabled";
 382         };
 383
 384         scifb1: serial@e6c30000 {
 385                 compatible = "renesas,scifb-r8a7793", "renesas,scifb";
 386                 reg = <0 0xe6c30000 0 64>;
 387                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
 389                 clock-names = "sci_ick";
 390                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 391                 dma-names = "tx", "rx";
 392                 power-domains = <&cpg_clocks>;
 393                 status = "disabled";
 394         };
 395
 396         scifb2: serial@e6ce0000 {
 397                 compatible = "renesas,scifb-r8a7793", "renesas,scifb";
 398                 reg = <0 0xe6ce0000 0 64>;
 399                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
 401                 clock-names = "sci_ick";
 402                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 403                 dma-names = "tx", "rx";
 404                 power-domains = <&cpg_clocks>;
 405                 status = "disabled";
 406         };
 407
 408         scif0: serial@e6e60000 {
 409                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 410                 reg = <0 0xe6e60000 0 64>;
 411                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
 413                 clock-names = "sci_ick";
 414                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 415                 dma-names = "tx", "rx";
 416                 power-domains = <&cpg_clocks>;
 417                 status = "disabled";
 418         };
 419
 420         scif1: serial@e6e68000 {
 421                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 422                 reg = <0 0xe6e68000 0 64>;
 423                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 424                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
 425                 clock-names = "sci_ick";
 426                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 427                 dma-names = "tx", "rx";
 428                 power-domains = <&cpg_clocks>;
 429                 status = "disabled";
 430         };
 431
 432         scif2: serial@e6e58000 {
 433                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 434                 reg = <0 0xe6e58000 0 64>;
 435                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 436                 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>;
 437                 clock-names = "sci_ick";
 438                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 439                 dma-names = "tx", "rx";
 440                 power-domains = <&cpg_clocks>;
 441                 status = "disabled";
 442         };
 443
 444         scif3: serial@e6ea8000 {
 445                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 446                 reg = <0 0xe6ea8000 0 64>;
 447                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>;
 449                 clock-names = "sci_ick";
 450                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 451                 dma-names = "tx", "rx";
 452                 power-domains = <&cpg_clocks>;
 453                 status = "disabled";
 454         };
 455
 456         scif4: serial@e6ee0000 {
 457                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 458                 reg = <0 0xe6ee0000 0 64>;
 459                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 460                 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>;
 461                 clock-names = "sci_ick";
 462                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 463                 dma-names = "tx", "rx";
 464                 power-domains = <&cpg_clocks>;
 465                 status = "disabled";
 466         };
 467
 468         scif5: serial@e6ee8000 {
 469                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 470                 reg = <0 0xe6ee8000 0 64>;
 471                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 472                 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>;
 473                 clock-names = "sci_ick";
 474                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 475                 dma-names = "tx", "rx";
 476                 power-domains = <&cpg_clocks>;
 477                 status = "disabled";
 478         };
 479
 480         hscif0: serial@e62c0000 {
 481                 compatible = "renesas,hscif-r8a7793", "renesas,hscif";
 482                 reg = <0 0xe62c0000 0 96>;
 483                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 484                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>;
 485                 clock-names = "sci_ick";
 486                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 487                 dma-names = "tx", "rx";
 488                 power-domains = <&cpg_clocks>;
 489                 status = "disabled";
 490         };
 491
 492         hscif1: serial@e62c8000 {
 493                 compatible = "renesas,hscif-r8a7793", "renesas,hscif";
 494                 reg = <0 0xe62c8000 0 96>;
 495                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 496                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>;
 497                 clock-names = "sci_ick";
 498                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 499                 dma-names = "tx", "rx";
 500                 power-domains = <&cpg_clocks>;
 501                 status = "disabled";
 502         };
 503
 504         hscif2: serial@e62d0000 {
 505                 compatible = "renesas,hscif-r8a7793", "renesas,hscif";
 506                 reg = <0 0xe62d0000 0 96>;
 507                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>;
 509                 clock-names = "sci_ick";
 510                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 511                 dma-names = "tx", "rx";
 512                 power-domains = <&cpg_clocks>;
 513                 status = "disabled";
 514         };
 515
 516         ether: ethernet@ee700000 {
 517                 compatible = "renesas,ether-r8a7793";
 518                 reg = <0 0xee700000 0 0x400>;
 519                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 520                 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
 521                 power-domains = <&cpg_clocks>;
 522                 phy-mode = "rmii";
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 status = "disabled";
 526         };
 527
 528         qspi: spi@e6b10000 {
 529                 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
 530                 reg = <0 0xe6b10000 0 0x2c>;
 531                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
 533                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 534                 dma-names = "tx", "rx";
 535                 power-domains = <&cpg_clocks>;
 536                 num-cs = <1>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         du: display@feb00000 {
 543                 compatible = "renesas,du-r8a7793";
 544                 reg = <0 0xfeb00000 0 0x40000>,
 545                       <0 0xfeb90000 0 0x1c>;
 546                 reg-names = "du", "lvds.0";
 547                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 548                              <0 268 IRQ_TYPE_LEVEL_HIGH>;
 549                 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
 550                          <&mstp7_clks R8A7793_CLK_DU1>,
 551                          <&mstp7_clks R8A7793_CLK_LVDS0>;
 552                 clock-names = "du.0", "du.1", "lvds.0";
 553                 status = "disabled";
 554
 555                 ports {
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558
 559                         port@0 {
 560                                 reg = <0>;
 561                                 du_out_rgb: endpoint {
 562                                 };
 563                         };
 564                         port@1 {
 565                                 reg = <1>;
 566                                 du_out_lvds0: endpoint {
 567                                 };
 568                         };
 569                 };
 570         };
 571
 572         clocks {
 573                 #address-cells = <2>;
 574                 #size-cells = <2>;
 575                 ranges;
 576
 577                 /* External root clock */
 578                 extal_clk: extal_clk {
 579                         compatible = "fixed-clock";
 580                         #clock-cells = <0>;
 581                         /* This value must be overridden by the board. */
 582                         clock-frequency = <0>;
 583                         clock-output-names = "extal";
 584                 };
 585
 586                 /* Special CPG clocks */
 587                 cpg_clocks: cpg_clocks@e6150000 {
 588                         compatible = "renesas,r8a7793-cpg-clocks",
 589                                      "renesas,rcar-gen2-cpg-clocks";
 590                         reg = <0 0xe6150000 0 0x1000>;
 591                         clocks = <&extal_clk>;
 592                         #clock-cells = <1>;
 593                         clock-output-names = "main", "pll0", "pll1", "pll3",
 594                                              "lb", "qspi", "sdh", "sd0", "z",
 595                                              "rcan", "adsp";
 596                         #power-domain-cells = <0>;
 597                 };
 598
 599                 /* Variable factor clocks */
 600                 sd2_clk: sd2_clk@e6150078 {
 601                         compatible = "renesas,r8a7793-div6-clock",
 602                                      "renesas,cpg-div6-clock";
 603                         reg = <0 0xe6150078 0 4>;
 604                         clocks = <&pll1_div2_clk>;
 605                         #clock-cells = <0>;
 606                         clock-output-names = "sd2";
 607                 };
 608                 sd3_clk: sd3_clk@e615026c {
 609                         compatible = "renesas,r8a7793-div6-clock",
 610                                      "renesas,cpg-div6-clock";
 611                         reg = <0 0xe615026c 0 4>;
 612                         clocks = <&pll1_div2_clk>;
 613                         #clock-cells = <0>;
 614                         clock-output-names = "sd3";
 615                 };
 616                 mmc0_clk: mmc0_clk@e6150240 {
 617                         compatible = "renesas,r8a7793-div6-clock",
 618                                      "renesas,cpg-div6-clock";
 619                         reg = <0 0xe6150240 0 4>;
 620                         clocks = <&pll1_div2_clk>;
 621                         #clock-cells = <0>;
 622                         clock-output-names = "mmc0";
 623                 };
 624
 625                 /* Fixed factor clocks */
 626                 pll1_div2_clk: pll1_div2_clk {
 627                         compatible = "fixed-factor-clock";
 628                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 629                         #clock-cells = <0>;
 630                         clock-div = <2>;
 631                         clock-mult = <1>;
 632                         clock-output-names = "pll1_div2";
 633                 };
 634                 zg_clk: zg_clk {
 635                         compatible = "fixed-factor-clock";
 636                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 637                         #clock-cells = <0>;
 638                         clock-div = <5>;
 639                         clock-mult = <1>;
 640                         clock-output-names = "zg";
 641                 };
 642                 zx_clk: zx_clk {
 643                         compatible = "fixed-factor-clock";
 644                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 645                         #clock-cells = <0>;
 646                         clock-div = <3>;
 647                         clock-mult = <1>;
 648                         clock-output-names = "zx";
 649                 };
 650                 zs_clk: zs_clk {
 651                         compatible = "fixed-factor-clock";
 652                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 653                         #clock-cells = <0>;
 654                         clock-div = <6>;
 655                         clock-mult = <1>;
 656                         clock-output-names = "zs";
 657                 };
 658                 hp_clk: hp_clk {
 659                         compatible = "fixed-factor-clock";
 660                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 661                         #clock-cells = <0>;
 662                         clock-div = <12>;
 663                         clock-mult = <1>;
 664                         clock-output-names = "hp";
 665                 };
 666                 p_clk: p_clk {
 667                         compatible = "fixed-factor-clock";
 668                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 669                         #clock-cells = <0>;
 670                         clock-div = <24>;
 671                         clock-mult = <1>;
 672                         clock-output-names = "p";
 673                 };
 674                 rclk_clk: rclk_clk {
 675                         compatible = "fixed-factor-clock";
 676                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 677                         #clock-cells = <0>;
 678                         clock-div = <(48 * 1024)>;
 679                         clock-mult = <1>;
 680                         clock-output-names = "rclk";
 681                 };
 682                 mp_clk: mp_clk {
 683                         compatible = "fixed-factor-clock";
 684                         clocks = <&pll1_div2_clk>;
 685                         #clock-cells = <0>;
 686                         clock-div = <15>;
 687                         clock-mult = <1>;
 688                         clock-output-names = "mp";
 689                 };
 690                 cp_clk: cp_clk {
 691                         compatible = "fixed-factor-clock";
 692                         clocks = <&extal_clk>;
 693                         #clock-cells = <0>;
 694                         clock-div = <2>;
 695                         clock-mult = <1>;
 696                         clock-output-names = "cp";
 697                 };
 698
 699                 /* Gate clocks */
 700                 mstp1_clks: mstp1_clks@e6150134 {
 701                         compatible = "renesas,r8a7793-mstp-clocks",
 702                                      "renesas,cpg-mstp-clocks";
 703                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 704                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 705                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 706                                  <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 707                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
 708                         #clock-cells = <1>;
 709                         clock-indices = <
 710                                 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
 711                                 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
 712                                 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
 713                                 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
 714                                 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
 715                                 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
 716                                 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
 717                                 R8A7793_CLK_VSP1_S
 718                         >;
 719                         clock-output-names =
 720                                 "vcp0", "vpc0", "ssp_dev", "tmu1",
 721                                 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
 722                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 723                                 "vsp1-du0", "vsps";
 724                 };
 725                 mstp2_clks: mstp2_clks@e6150138 {
 726                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 727                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 728                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 729                                  <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
 730                         #clock-cells = <1>;
 731                         clock-indices = <
 732                                 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
 733                                 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
 734                                 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
 735                         >;
 736                         clock-output-names =
 737                                 "scifa2", "scifa1", "scifa0", "scifb0",
 738                                 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
 739                 };
 740                 mstp3_clks: mstp3_clks@e615013c {
 741                         compatible = "renesas,r8a7793-mstp-clocks",
 742                                      "renesas,cpg-mstp-clocks";
 743                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 744                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
 745                                  <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
 746                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
 747                                  <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 748                         #clock-cells = <1>;
 749                         clock-indices = <
 750                                 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
 751                                 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
 752                                 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
 753                                 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
 754                                 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
 755                                 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
 756                         >;
 757                         clock-output-names =
 758                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 759                                 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
 760                                 "usbdmac0", "usbdmac1";
 761                 };
 762                 mstp4_clks: mstp4_clks@e6150140 {
 763                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 764                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 765                         clocks = <&cp_clk>;
 766                         #clock-cells = <1>;
 767                         clock-indices = <R8A7793_CLK_IRQC>;
 768                         clock-output-names = "irqc";
 769                 };
 770                 mstp5_clks: mstp5_clks@e6150144 {
 771                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 772                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 773                         clocks = <&extal_clk>;
 774                         #clock-cells = <1>;
 775                         clock-indices = <R8A7793_CLK_THERMAL>;
 776                         clock-output-names = "thermal";
 777                 };
 778                 mstp7_clks: mstp7_clks@e615014c {
 779                         compatible = "renesas,r8a7793-mstp-clocks",
 780                                      "renesas,cpg-mstp-clocks";
 781                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 782                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
 783                                  <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 784                                  <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
 785                                  <&zx_clk>, <&zx_clk>;
 786                         #clock-cells = <1>;
 787                         clock-indices = <
 788                                 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
 789                                 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
 790                                 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
 791                                 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
 792                                 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
 793                                 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
 794                                 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
 795                         >;
 796                         clock-output-names =
 797                                 "ehci", "hsusb", "hscif2", "scif5", "scif4",
 798                                 "hscif1", "hscif0", "scif3", "scif2",
 799                                 "scif1", "scif0", "du1", "du0", "lvds0";
 800                 };
 801                 mstp8_clks: mstp8_clks@e6150990 {
 802                         compatible = "renesas,r8a7793-mstp-clocks",
 803                                      "renesas,cpg-mstp-clocks";
 804                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 805                         clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
 806                                  <&p_clk>, <&zs_clk>, <&zs_clk>;
 807                         #clock-cells = <1>;
 808                         clock-indices = <
 809                                 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
 810                                 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
 811                                 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
 812                                 R8A7793_CLK_SATA0
 813                         >;
 814                         clock-output-names =
 815                                 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
 816                                 "sata1", "sata0";
 817                 };
 818                 mstp9_clks: mstp9_clks@e6150994 {
 819                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 820                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 821                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 822                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 823                                  <&cpg_clocks R8A7793_CLK_QSPI>;
 824                         #clock-cells = <1>;
 825                         clock-indices = <
 826                                 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
 827                                 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
 828                                 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
 829                                 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
 830                                 R8A7793_CLK_QSPI_MOD
 831                         >;
 832                         clock-output-names =
 833                                 "gpio7", "gpio6", "gpio5", "gpio4",
 834                                 "gpio3", "gpio2", "gpio1", "gpio0",
 835                                 "qspi_mod";
 836                 };
 837                 mstp11_clks: mstp11_clks@e615099c {
 838                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 839                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 840                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 841                         #clock-cells = <1>;
 842                         clock-indices = <
 843                                 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
 844                         >;
 845                         clock-output-names = "scifa3", "scifa4", "scifa5";
 846                 };
 847         };
 848
 849         ipmmu_sy0: mmu@e6280000 {
 850                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 851                 reg = <0 0xe6280000 0 0x1000>;
 852                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
 853                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
 854                 #iommu-cells = <1>;
 855                 status = "disabled";
 856         };
 857
 858         ipmmu_sy1: mmu@e6290000 {
 859                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 860                 reg = <0 0xe6290000 0 0x1000>;
 861                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
 862                 #iommu-cells = <1>;
 863                 status = "disabled";
 864         };
 865
 866         ipmmu_ds: mmu@e6740000 {
 867                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 868                 reg = <0 0xe6740000 0 0x1000>;
 869                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
 870                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
 871                 #iommu-cells = <1>;
 872                 status = "disabled";
 873         };
 874
 875         ipmmu_mp: mmu@ec680000 {
 876                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 877                 reg = <0 0xec680000 0 0x1000>;
 878                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
 879                 #iommu-cells = <1>;
 880                 status = "disabled";
 881         };
 882
 883         ipmmu_mx: mmu@fe951000 {
 884                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 885                 reg = <0 0xfe951000 0 0x1000>;
 886                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
 887                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
 888                 #iommu-cells = <1>;
 889                 status = "disabled";
 890         };
 891
 892         ipmmu_rt: mmu@ffc80000 {
 893                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 894                 reg = <0 0xffc80000 0 0x1000>;
 895                 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
 896                 #iommu-cells = <1>;
 897                 status = "disabled";
 898         };
 899
 900         ipmmu_gp: mmu@e62a0000 {
 901                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 902                 reg = <0 0xe62a0000 0 0x1000>;
 903                 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
 904                              <0 261 IRQ_TYPE_LEVEL_HIGH>;
 905                 #iommu-cells = <1>;
 906                 status = "disabled";
 907         };
 908 };