arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7794";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 spi0 = &qspi;
  30                 vin0 = &vin0;
  31                 vin1 = &vin1;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0>;
  42                         clock-frequency = <1000000000>;
  43                 };
  44
  45                 cpu1: cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a7";
  48                         reg = <1>;
  49                         clock-frequency = <1000000000>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@f1001000 {
  54                 compatible = "arm,gic-400";
  55                 #interrupt-cells = <3>;
  56                 #address-cells = <0>;
  57                 interrupt-controller;
  58                 reg = <0 0xf1001000 0 0x1000>,
  59                         <0 0xf1002000 0 0x1000>,
  60                         <0 0xf1004000 0 0x2000>,
  61                         <0 0xf1006000 0 0x2000>;
  62                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  63         };
  64
  65         gpio0: gpio@e6050000 {
  66                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  67                 reg = <0 0xe6050000 0 0x50>;
  68                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  69                 #gpio-cells = <2>;
  70                 gpio-controller;
  71                 gpio-ranges = <&pfc 0 0 32>;
  72                 #interrupt-cells = <2>;
  73                 interrupt-controller;
  74                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  75                 power-domains = <&cpg_clocks>;
  76         };
  77
  78         gpio1: gpio@e6051000 {
  79                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  80                 reg = <0 0xe6051000 0 0x50>;
  81                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  82                 #gpio-cells = <2>;
  83                 gpio-controller;
  84                 gpio-ranges = <&pfc 0 32 26>;
  85                 #interrupt-cells = <2>;
  86                 interrupt-controller;
  87                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
  88                 power-domains = <&cpg_clocks>;
  89         };
  90
  91         gpio2: gpio@e6052000 {
  92                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  93                 reg = <0 0xe6052000 0 0x50>;
  94                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  95                 #gpio-cells = <2>;
  96                 gpio-controller;
  97                 gpio-ranges = <&pfc 0 64 32>;
  98                 #interrupt-cells = <2>;
  99                 interrupt-controller;
 100                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 101                 power-domains = <&cpg_clocks>;
 102         };
 103
 104         gpio3: gpio@e6053000 {
 105                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 106                 reg = <0 0xe6053000 0 0x50>;
 107                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 108                 #gpio-cells = <2>;
 109                 gpio-controller;
 110                 gpio-ranges = <&pfc 0 96 32>;
 111                 #interrupt-cells = <2>;
 112                 interrupt-controller;
 113                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 114                 power-domains = <&cpg_clocks>;
 115         };
 116
 117         gpio4: gpio@e6054000 {
 118                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 119                 reg = <0 0xe6054000 0 0x50>;
 120                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 121                 #gpio-cells = <2>;
 122                 gpio-controller;
 123                 gpio-ranges = <&pfc 0 128 32>;
 124                 #interrupt-cells = <2>;
 125                 interrupt-controller;
 126                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 127                 power-domains = <&cpg_clocks>;
 128         };
 129
 130         gpio5: gpio@e6055000 {
 131                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 132                 reg = <0 0xe6055000 0 0x50>;
 133                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 134                 #gpio-cells = <2>;
 135                 gpio-controller;
 136                 gpio-ranges = <&pfc 0 160 28>;
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 140                 power-domains = <&cpg_clocks>;
 141         };
 142
 143         gpio6: gpio@e6055400 {
 144                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 145                 reg = <0 0xe6055400 0 0x50>;
 146                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 147                 #gpio-cells = <2>;
 148                 gpio-controller;
 149                 gpio-ranges = <&pfc 0 192 26>;
 150                 #interrupt-cells = <2>;
 151                 interrupt-controller;
 152                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 153                 power-domains = <&cpg_clocks>;
 154         };
 155
 156         cmt0: timer@ffca0000 {
 157                 compatible = "renesas,cmt-48-gen2";
 158                 reg = <0 0xffca0000 0 0x1004>;
 159                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 161                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 162                 clock-names = "fck";
 163                 power-domains = <&cpg_clocks>;
 164
 165                 renesas,channels-mask = <0x60>;
 166
 167                 status = "disabled";
 168         };
 169
 170         cmt1: timer@e6130000 {
 171                 compatible = "renesas,cmt-48-gen2";
 172                 reg = <0 0xe6130000 0 0x1004>;
 173                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 182                 clock-names = "fck";
 183                 power-domains = <&cpg_clocks>;
 184
 185                 renesas,channels-mask = <0xff>;
 186
 187                 status = "disabled";
 188         };
 189
 190         timer {
 191                 compatible = "arm,armv7-timer";
 192                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 193                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 194                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 195                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 196         };
 197
 198         irqc0: interrupt-controller@e61c0000 {
 199                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 200                 #interrupt-cells = <2>;
 201                 interrupt-controller;
 202                 reg = <0 0xe61c0000 0 0x200>;
 203                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 214                 power-domains = <&cpg_clocks>;
 215         };
 216
 217         pfc: pin-controller@e6060000 {
 218                 compatible = "renesas,pfc-r8a7794";
 219                 reg = <0 0xe6060000 0 0x11c>;
 220         };
 221
 222         dmac0: dma-controller@e6700000 {
 223                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 224                 reg = <0 0xe6700000 0 0x20000>;
 225                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 226                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 227                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 228                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 229                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 230                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 231                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 232                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 233                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 234                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 235                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 236                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 237                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 238                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 239                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 240                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 241                 interrupt-names = "error",
 242                                 "ch0", "ch1", "ch2", "ch3",
 243                                 "ch4", "ch5", "ch6", "ch7",
 244                                 "ch8", "ch9", "ch10", "ch11",
 245                                 "ch12", "ch13", "ch14";
 246                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 247                 clock-names = "fck";
 248                 power-domains = <&cpg_clocks>;
 249                 #dma-cells = <1>;
 250                 dma-channels = <15>;
 251         };
 252
 253         dmac1: dma-controller@e6720000 {
 254                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 255                 reg = <0 0xe6720000 0 0x20000>;
 256                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 257                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 258                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 259                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 260                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 261                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 262                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 263                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 264                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 265                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 266                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 267                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 268                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 269                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 270                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 271                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 272                 interrupt-names = "error",
 273                                 "ch0", "ch1", "ch2", "ch3",
 274                                 "ch4", "ch5", "ch6", "ch7",
 275                                 "ch8", "ch9", "ch10", "ch11",
 276                                 "ch12", "ch13", "ch14";
 277                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 278                 clock-names = "fck";
 279                 power-domains = <&cpg_clocks>;
 280                 #dma-cells = <1>;
 281                 dma-channels = <15>;
 282         };
 283
 284         scifa0: serial@e6c40000 {
 285                 compatible = "renesas,scifa-r8a7794",
 286                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 287                 reg = <0 0xe6c40000 0 64>;
 288                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 290                 clock-names = "fck";
 291                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 292                 dma-names = "tx", "rx";
 293                 power-domains = <&cpg_clocks>;
 294                 status = "disabled";
 295         };
 296
 297         scifa1: serial@e6c50000 {
 298                 compatible = "renesas,scifa-r8a7794",
 299                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 300                 reg = <0 0xe6c50000 0 64>;
 301                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 303                 clock-names = "fck";
 304                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 305                 dma-names = "tx", "rx";
 306                 power-domains = <&cpg_clocks>;
 307                 status = "disabled";
 308         };
 309
 310         scifa2: serial@e6c60000 {
 311                 compatible = "renesas,scifa-r8a7794",
 312                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 313                 reg = <0 0xe6c60000 0 64>;
 314                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 316                 clock-names = "fck";
 317                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 318                 dma-names = "tx", "rx";
 319                 power-domains = <&cpg_clocks>;
 320                 status = "disabled";
 321         };
 322
 323         scifa3: serial@e6c70000 {
 324                 compatible = "renesas,scifa-r8a7794",
 325                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 326                 reg = <0 0xe6c70000 0 64>;
 327                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 329                 clock-names = "fck";
 330                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 331                 dma-names = "tx", "rx";
 332                 power-domains = <&cpg_clocks>;
 333                 status = "disabled";
 334         };
 335
 336         scifa4: serial@e6c78000 {
 337                 compatible = "renesas,scifa-r8a7794",
 338                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 339                 reg = <0 0xe6c78000 0 64>;
 340                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 341                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 342                 clock-names = "fck";
 343                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 344                 dma-names = "tx", "rx";
 345                 power-domains = <&cpg_clocks>;
 346                 status = "disabled";
 347         };
 348
 349         scifa5: serial@e6c80000 {
 350                 compatible = "renesas,scifa-r8a7794",
 351                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 352                 reg = <0 0xe6c80000 0 64>;
 353                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 355                 clock-names = "fck";
 356                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 357                 dma-names = "tx", "rx";
 358                 power-domains = <&cpg_clocks>;
 359                 status = "disabled";
 360         };
 361
 362         scifb0: serial@e6c20000 {
 363                 compatible = "renesas,scifb-r8a7794",
 364                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 365                 reg = <0 0xe6c20000 0 64>;
 366                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 368                 clock-names = "fck";
 369                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 370                 dma-names = "tx", "rx";
 371                 power-domains = <&cpg_clocks>;
 372                 status = "disabled";
 373         };
 374
 375         scifb1: serial@e6c30000 {
 376                 compatible = "renesas,scifb-r8a7794",
 377                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 378                 reg = <0 0xe6c30000 0 64>;
 379                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 381                 clock-names = "fck";
 382                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 383                 dma-names = "tx", "rx";
 384                 power-domains = <&cpg_clocks>;
 385                 status = "disabled";
 386         };
 387
 388         scifb2: serial@e6ce0000 {
 389                 compatible = "renesas,scifb-r8a7794",
 390                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 391                 reg = <0 0xe6ce0000 0 64>;
 392                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 394                 clock-names = "fck";
 395                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 396                 dma-names = "tx", "rx";
 397                 power-domains = <&cpg_clocks>;
 398                 status = "disabled";
 399         };
 400
 401         scif0: serial@e6e60000 {
 402                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 403                              "renesas,scif";
 404                 reg = <0 0xe6e60000 0 64>;
 405                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 407                          <&scif_clk>;
 408                 clock-names = "fck", "brg_int", "scif_clk";
 409                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 410                 dma-names = "tx", "rx";
 411                 power-domains = <&cpg_clocks>;
 412                 status = "disabled";
 413         };
 414
 415         scif1: serial@e6e68000 {
 416                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 417                              "renesas,scif";
 418                 reg = <0 0xe6e68000 0 64>;
 419                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 421                          <&scif_clk>;
 422                 clock-names = "fck", "brg_int", "scif_clk";
 423                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 424                 dma-names = "tx", "rx";
 425                 power-domains = <&cpg_clocks>;
 426                 status = "disabled";
 427         };
 428
 429         scif2: serial@e6e58000 {
 430                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 431                              "renesas,scif";
 432                 reg = <0 0xe6e58000 0 64>;
 433                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 435                          <&scif_clk>;
 436                 clock-names = "fck", "brg_int", "scif_clk";
 437                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 438                 dma-names = "tx", "rx";
 439                 power-domains = <&cpg_clocks>;
 440                 status = "disabled";
 441         };
 442
 443         scif3: serial@e6ea8000 {
 444                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 445                              "renesas,scif";
 446                 reg = <0 0xe6ea8000 0 64>;
 447                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 449                          <&scif_clk>;
 450                 clock-names = "fck", "brg_int", "scif_clk";
 451                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 452                 dma-names = "tx", "rx";
 453                 power-domains = <&cpg_clocks>;
 454                 status = "disabled";
 455         };
 456
 457         scif4: serial@e6ee0000 {
 458                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 459                              "renesas,scif";
 460                 reg = <0 0xe6ee0000 0 64>;
 461                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 463                          <&scif_clk>;
 464                 clock-names = "fck", "brg_int", "scif_clk";
 465                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 466                 dma-names = "tx", "rx";
 467                 power-domains = <&cpg_clocks>;
 468                 status = "disabled";
 469         };
 470
 471         scif5: serial@e6ee8000 {
 472                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 473                              "renesas,scif";
 474                 reg = <0 0xe6ee8000 0 64>;
 475                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 477                          <&scif_clk>;
 478                 clock-names = "fck", "brg_int", "scif_clk";
 479                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 480                 dma-names = "tx", "rx";
 481                 power-domains = <&cpg_clocks>;
 482                 status = "disabled";
 483         };
 484
 485         hscif0: serial@e62c0000 {
 486                 compatible = "renesas,hscif-r8a7794",
 487                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 488                 reg = <0 0xe62c0000 0 96>;
 489                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 491                          <&scif_clk>;
 492                 clock-names = "fck", "brg_int", "scif_clk";
 493                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 494                 dma-names = "tx", "rx";
 495                 power-domains = <&cpg_clocks>;
 496                 status = "disabled";
 497         };
 498
 499         hscif1: serial@e62c8000 {
 500                 compatible = "renesas,hscif-r8a7794",
 501                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 502                 reg = <0 0xe62c8000 0 96>;
 503                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 505                          <&scif_clk>;
 506                 clock-names = "fck", "brg_int", "scif_clk";
 507                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 508                 dma-names = "tx", "rx";
 509                 power-domains = <&cpg_clocks>;
 510                 status = "disabled";
 511         };
 512
 513         hscif2: serial@e62d0000 {
 514                 compatible = "renesas,hscif-r8a7794",
 515                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 516                 reg = <0 0xe62d0000 0 96>;
 517                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 519                          <&scif_clk>;
 520                 clock-names = "fck", "brg_int", "scif_clk";
 521                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 522                 dma-names = "tx", "rx";
 523                 power-domains = <&cpg_clocks>;
 524                 status = "disabled";
 525         };
 526
 527         ether: ethernet@ee700000 {
 528                 compatible = "renesas,ether-r8a7794";
 529                 reg = <0 0xee700000 0 0x400>;
 530                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 531                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 532                 power-domains = <&cpg_clocks>;
 533                 phy-mode = "rmii";
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 status = "disabled";
 537         };
 538
 539         /* The memory map in the User's Manual maps the cores to bus numbers */
 540         i2c0: i2c@e6508000 {
 541                 compatible = "renesas,i2c-r8a7794";
 542                 reg = <0 0xe6508000 0 0x40>;
 543                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 544                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 545                 power-domains = <&cpg_clocks>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 i2c-scl-internal-delay-ns = <6>;
 549                 status = "disabled";
 550         };
 551
 552         i2c1: i2c@e6518000 {
 553                 compatible = "renesas,i2c-r8a7794";
 554                 reg = <0 0xe6518000 0 0x40>;
 555                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 556                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 557                 power-domains = <&cpg_clocks>;
 558                 #address-cells = <1>;
 559                 #size-cells = <0>;
 560                 i2c-scl-internal-delay-ns = <6>;
 561                 status = "disabled";
 562         };
 563
 564         i2c2: i2c@e6530000 {
 565                 compatible = "renesas,i2c-r8a7794";
 566                 reg = <0 0xe6530000 0 0x40>;
 567                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 568                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 569                 power-domains = <&cpg_clocks>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 i2c-scl-internal-delay-ns = <6>;
 573                 status = "disabled";
 574         };
 575
 576         i2c3: i2c@e6540000 {
 577                 compatible = "renesas,i2c-r8a7794";
 578                 reg = <0 0xe6540000 0 0x40>;
 579                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 580                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 581                 power-domains = <&cpg_clocks>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 i2c-scl-internal-delay-ns = <6>;
 585                 status = "disabled";
 586         };
 587
 588         i2c4: i2c@e6520000 {
 589                 compatible = "renesas,i2c-r8a7794";
 590                 reg = <0 0xe6520000 0 0x40>;
 591                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 592                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 593                 power-domains = <&cpg_clocks>;
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 i2c-scl-internal-delay-ns = <6>;
 597                 status = "disabled";
 598         };
 599
 600         i2c5: i2c@e6528000 {
 601                 compatible = "renesas,i2c-r8a7794";
 602                 reg = <0 0xe6528000 0 0x40>;
 603                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 604                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 605                 power-domains = <&cpg_clocks>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 i2c-scl-internal-delay-ns = <6>;
 609                 status = "disabled";
 610         };
 611
 612         mmcif0: mmc@ee200000 {
 613                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 614                 reg = <0 0xee200000 0 0x80>;
 615                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 616                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 617                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 618                 dma-names = "tx", "rx";
 619                 power-domains = <&cpg_clocks>;
 620                 reg-io-width = <4>;
 621                 status = "disabled";
 622         };
 623
 624         sdhi0: sd@ee100000 {
 625                 compatible = "renesas,sdhi-r8a7794";
 626                 reg = <0 0xee100000 0 0x200>;
 627                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 629                 power-domains = <&cpg_clocks>;
 630                 status = "disabled";
 631         };
 632
 633         sdhi1: sd@ee140000 {
 634                 compatible = "renesas,sdhi-r8a7794";
 635                 reg = <0 0xee140000 0 0x100>;
 636                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 638                 power-domains = <&cpg_clocks>;
 639                 status = "disabled";
 640         };
 641
 642         sdhi2: sd@ee160000 {
 643                 compatible = "renesas,sdhi-r8a7794";
 644                 reg = <0 0xee160000 0 0x100>;
 645                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 646                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 647                 power-domains = <&cpg_clocks>;
 648                 status = "disabled";
 649         };
 650
 651         qspi: spi@e6b10000 {
 652                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 653                 reg = <0 0xe6b10000 0 0x2c>;
 654                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 656                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 657                 dma-names = "tx", "rx";
 658                 power-domains = <&cpg_clocks>;
 659                 num-cs = <1>;
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 status = "disabled";
 663         };
 664
 665         vin0: video@e6ef0000 {
 666                 compatible = "renesas,vin-r8a7794";
 667                 reg = <0 0xe6ef0000 0 0x1000>;
 668                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 669                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 670                 power-domains = <&cpg_clocks>;
 671                 status = "disabled";
 672         };
 673
 674         vin1: video@e6ef1000 {
 675                 compatible = "renesas,vin-r8a7794";
 676                 reg = <0 0xe6ef1000 0 0x1000>;
 677                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 679                 power-domains = <&cpg_clocks>;
 680                 status = "disabled";
 681         };
 682
 683         pci0: pci@ee090000 {
 684                 compatible = "renesas,pci-r8a7794";
 685                 device_type = "pci";
 686                 reg = <0 0xee090000 0 0xc00>,
 687                       <0 0xee080000 0 0x1100>;
 688                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 690                 power-domains = <&cpg_clocks>;
 691                 status = "disabled";
 692
 693                 bus-range = <0 0>;
 694                 #address-cells = <3>;
 695                 #size-cells = <2>;
 696                 #interrupt-cells = <1>;
 697                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 698                 interrupt-map-mask = <0xff00 0 0 0x7>;
 699                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 700                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 701                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 702
 703                 usb@0,1 {
 704                         reg = <0x800 0 0 0 0>;
 705                         device_type = "pci";
 706                         phys = <&usb0 0>;
 707                         phy-names = "usb";
 708                 };
 709
 710                 usb@0,2 {
 711                         reg = <0x1000 0 0 0 0>;
 712                         device_type = "pci";
 713                         phys = <&usb0 0>;
 714                         phy-names = "usb";
 715                 };
 716         };
 717
 718         pci1: pci@ee0d0000 {
 719                 compatible = "renesas,pci-r8a7794";
 720                 device_type = "pci";
 721                 reg = <0 0xee0d0000 0 0xc00>,
 722                       <0 0xee0c0000 0 0x1100>;
 723                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 724                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 725                 power-domains = <&cpg_clocks>;
 726                 status = "disabled";
 727
 728                 bus-range = <1 1>;
 729                 #address-cells = <3>;
 730                 #size-cells = <2>;
 731                 #interrupt-cells = <1>;
 732                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 733                 interrupt-map-mask = <0xff00 0 0 0x7>;
 734                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 735                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 736                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 737
 738                 usb@0,1 {
 739                         reg = <0x800 0 0 0 0>;
 740                         device_type = "pci";
 741                         phys = <&usb2 0>;
 742                         phy-names = "usb";
 743                 };
 744
 745                 usb@0,2 {
 746                         reg = <0x1000 0 0 0 0>;
 747                         device_type = "pci";
 748                         phys = <&usb2 0>;
 749                         phy-names = "usb";
 750                 };
 751         };
 752
 753         hsusb: usb@e6590000 {
 754                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 755                 reg = <0 0xe6590000 0 0x100>;
 756                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 757                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 758                 power-domains = <&cpg_clocks>;
 759                 renesas,buswait = <4>;
 760                 phys = <&usb0 1>;
 761                 phy-names = "usb";
 762                 status = "disabled";
 763         };
 764
 765         usbphy: usb-phy@e6590100 {
 766                 compatible = "renesas,usb-phy-r8a7794";
 767                 reg = <0 0xe6590100 0 0x100>;
 768                 #address-cells = <1>;
 769                 #size-cells = <0>;
 770                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 771                 clock-names = "usbhs";
 772                 power-domains = <&cpg_clocks>;
 773                 status = "disabled";
 774
 775                 usb0: usb-channel@0 {
 776                         reg = <0>;
 777                         #phy-cells = <1>;
 778                 };
 779                 usb2: usb-channel@2 {
 780                         reg = <2>;
 781                         #phy-cells = <1>;
 782                 };
 783         };
 784
 785         du: display@feb00000 {
 786                 compatible = "renesas,du-r8a7794";
 787                 reg = <0 0xfeb00000 0 0x40000>;
 788                 reg-names = "du";
 789                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 790                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 791                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 792                          <&mstp7_clks R8A7794_CLK_DU0>;
 793                 clock-names = "du.0", "du.1";
 794                 status = "disabled";
 795
 796                 ports {
 797                         #address-cells = <1>;
 798                         #size-cells = <0>;
 799
 800                         port@0 {
 801                                 reg = <0>;
 802                                 du_out_rgb0: endpoint {
 803                                 };
 804                         };
 805                         port@1 {
 806                                 reg = <1>;
 807                                 du_out_rgb1: endpoint {
 808                                 };
 809                         };
 810                 };
 811         };
 812
 813         clocks {
 814                 #address-cells = <2>;
 815                 #size-cells = <2>;
 816                 ranges;
 817
 818                 /* External root clock */
 819                 extal_clk: extal_clk {
 820                         compatible = "fixed-clock";
 821                         #clock-cells = <0>;
 822                         /* This value must be overriden by the board. */
 823                         clock-frequency = <0>;
 824                         clock-output-names = "extal";
 825                 };
 826
 827                 /* External SCIF clock */
 828                 scif_clk: scif {
 829                         compatible = "fixed-clock";
 830                         #clock-cells = <0>;
 831                         /* This value must be overridden by the board. */
 832                         clock-frequency = <0>;
 833                         status = "disabled";
 834                 };
 835
 836                 /* Special CPG clocks */
 837                 cpg_clocks: cpg_clocks@e6150000 {
 838                         compatible = "renesas,r8a7794-cpg-clocks",
 839                                      "renesas,rcar-gen2-cpg-clocks";
 840                         reg = <0 0xe6150000 0 0x1000>;
 841                         clocks = <&extal_clk>;
 842                         #clock-cells = <1>;
 843                         clock-output-names = "main", "pll0", "pll1", "pll3",
 844                                              "lb", "qspi", "sdh", "sd0", "z";
 845                         #power-domain-cells = <0>;
 846                 };
 847                 /* Variable factor clocks */
 848                 sd2_clk: sd2_clk@e6150078 {
 849                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 850                         reg = <0 0xe6150078 0 4>;
 851                         clocks = <&pll1_div2_clk>;
 852                         #clock-cells = <0>;
 853                         clock-output-names = "sd2";
 854                 };
 855                 sd3_clk: sd3_clk@e615026c {
 856                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 857                         reg = <0 0xe615026c 0 4>;
 858                         clocks = <&pll1_div2_clk>;
 859                         #clock-cells = <0>;
 860                         clock-output-names = "sd3";
 861                 };
 862                 mmc0_clk: mmc0_clk@e6150240 {
 863                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 864                         reg = <0 0xe6150240 0 4>;
 865                         clocks = <&pll1_div2_clk>;
 866                         #clock-cells = <0>;
 867                         clock-output-names = "mmc0";
 868                 };
 869
 870                 /* Fixed factor clocks */
 871                 pll1_div2_clk: pll1_div2_clk {
 872                         compatible = "fixed-factor-clock";
 873                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 874                         #clock-cells = <0>;
 875                         clock-div = <2>;
 876                         clock-mult = <1>;
 877                         clock-output-names = "pll1_div2";
 878                 };
 879                 zg_clk: zg_clk {
 880                         compatible = "fixed-factor-clock";
 881                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 882                         #clock-cells = <0>;
 883                         clock-div = <6>;
 884                         clock-mult = <1>;
 885                         clock-output-names = "zg";
 886                 };
 887                 zx_clk: zx_clk {
 888                         compatible = "fixed-factor-clock";
 889                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 890                         #clock-cells = <0>;
 891                         clock-div = <3>;
 892                         clock-mult = <1>;
 893                         clock-output-names = "zx";
 894                 };
 895                 zs_clk: zs_clk {
 896                         compatible = "fixed-factor-clock";
 897                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 898                         #clock-cells = <0>;
 899                         clock-div = <6>;
 900                         clock-mult = <1>;
 901                         clock-output-names = "zs";
 902                 };
 903                 hp_clk: hp_clk {
 904                         compatible = "fixed-factor-clock";
 905                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 906                         #clock-cells = <0>;
 907                         clock-div = <12>;
 908                         clock-mult = <1>;
 909                         clock-output-names = "hp";
 910                 };
 911                 i_clk: i_clk {
 912                         compatible = "fixed-factor-clock";
 913                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 914                         #clock-cells = <0>;
 915                         clock-div = <2>;
 916                         clock-mult = <1>;
 917                         clock-output-names = "i";
 918                 };
 919                 b_clk: b_clk {
 920                         compatible = "fixed-factor-clock";
 921                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 922                         #clock-cells = <0>;
 923                         clock-div = <12>;
 924                         clock-mult = <1>;
 925                         clock-output-names = "b";
 926                 };
 927                 p_clk: p_clk {
 928                         compatible = "fixed-factor-clock";
 929                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 930                         #clock-cells = <0>;
 931                         clock-div = <24>;
 932                         clock-mult = <1>;
 933                         clock-output-names = "p";
 934                 };
 935                 cl_clk: cl_clk {
 936                         compatible = "fixed-factor-clock";
 937                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 938                         #clock-cells = <0>;
 939                         clock-div = <48>;
 940                         clock-mult = <1>;
 941                         clock-output-names = "cl";
 942                 };
 943                 m2_clk: m2_clk {
 944                         compatible = "fixed-factor-clock";
 945                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 946                         #clock-cells = <0>;
 947                         clock-div = <8>;
 948                         clock-mult = <1>;
 949                         clock-output-names = "m2";
 950                 };
 951                 rclk_clk: rclk_clk {
 952                         compatible = "fixed-factor-clock";
 953                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 954                         #clock-cells = <0>;
 955                         clock-div = <(48 * 1024)>;
 956                         clock-mult = <1>;
 957                         clock-output-names = "rclk";
 958                 };
 959                 oscclk_clk: oscclk_clk {
 960                         compatible = "fixed-factor-clock";
 961                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 962                         #clock-cells = <0>;
 963                         clock-div = <(12 * 1024)>;
 964                         clock-mult = <1>;
 965                         clock-output-names = "oscclk";
 966                 };
 967                 zb3_clk: zb3_clk {
 968                         compatible = "fixed-factor-clock";
 969                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 970                         #clock-cells = <0>;
 971                         clock-div = <4>;
 972                         clock-mult = <1>;
 973                         clock-output-names = "zb3";
 974                 };
 975                 zb3d2_clk: zb3d2_clk {
 976                         compatible = "fixed-factor-clock";
 977                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 978                         #clock-cells = <0>;
 979                         clock-div = <8>;
 980                         clock-mult = <1>;
 981                         clock-output-names = "zb3d2";
 982                 };
 983                 ddr_clk: ddr_clk {
 984                         compatible = "fixed-factor-clock";
 985                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 986                         #clock-cells = <0>;
 987                         clock-div = <8>;
 988                         clock-mult = <1>;
 989                         clock-output-names = "ddr";
 990                 };
 991                 mp_clk: mp_clk {
 992                         compatible = "fixed-factor-clock";
 993                         clocks = <&pll1_div2_clk>;
 994                         #clock-cells = <0>;
 995                         clock-div = <15>;
 996                         clock-mult = <1>;
 997                         clock-output-names = "mp";
 998                 };
 999                 cp_clk: cp_clk {
1000                         compatible = "fixed-factor-clock";
1001                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1002                         #clock-cells = <0>;
1003                         clock-div = <48>;
1004                         clock-mult = <1>;
1005                         clock-output-names = "cp";
1006                 };
1007
1008                 acp_clk: acp_clk {
1009                         compatible = "fixed-factor-clock";
1010                         clocks = <&extal_clk>;
1011                         #clock-cells = <0>;
1012                         clock-div = <2>;
1013                         clock-mult = <1>;
1014                         clock-output-names = "acp";
1015                 };
1016
1017                 /* Gate clocks */
1018                 mstp0_clks: mstp0_clks@e6150130 {
1019                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1020                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1021                         clocks = <&mp_clk>;
1022                         #clock-cells = <1>;
1023                         clock-indices = <R8A7794_CLK_MSIOF0>;
1024                         clock-output-names = "msiof0";
1025                 };
1026                 mstp1_clks: mstp1_clks@e6150134 {
1027                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1028                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1029                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1030                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1031                                  <&zs_clk>, <&zs_clk>;
1032                         #clock-cells = <1>;
1033                         clock-indices = <
1034                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1035                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1036                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1037                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1038                         >;
1039                         clock-output-names =
1040                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1041                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1042                 };
1043                 mstp2_clks: mstp2_clks@e6150138 {
1044                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1045                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1046                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1047                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1048                                  <&zs_clk>, <&zs_clk>;
1049                         #clock-cells = <1>;
1050                         clock-indices = <
1051                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1052                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1053                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1054                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1055                         >;
1056                         clock-output-names =
1057                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1058                                 "scifb1", "msiof1", "scifb2",
1059                                 "sys-dmac1", "sys-dmac0";
1060                 };
1061                 mstp3_clks: mstp3_clks@e615013c {
1062                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1063                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1064                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1065                                  <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1066                         #clock-cells = <1>;
1067                         clock-indices = <
1068                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1069                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
1070                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1071                         >;
1072                         clock-output-names =
1073                                 "sdhi2", "sdhi1", "sdhi0",
1074                                 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
1075                 };
1076                 mstp4_clks: mstp4_clks@e6150140 {
1077                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1078                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1079                         clocks = <&cp_clk>;
1080                         #clock-cells = <1>;
1081                         clock-indices = <R8A7794_CLK_IRQC>;
1082                         clock-output-names = "irqc";
1083                 };
1084                 mstp7_clks: mstp7_clks@e615014c {
1085                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1086                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1087                         clocks = <&mp_clk>, <&mp_clk>,
1088                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1089                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1090                                  <&zx_clk>;
1091                         #clock-cells = <1>;
1092                         clock-indices = <
1093                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1094                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1095                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1096                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1097                                 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1098                         >;
1099                         clock-output-names =
1100                                 "ehci", "hsusb",
1101                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1102                                 "scif3", "scif2", "scif1", "scif0", "du0";
1103                 };
1104                 mstp8_clks: mstp8_clks@e6150990 {
1105                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1106                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1107                         clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
1108                         #clock-cells = <1>;
1109                         clock-indices = <
1110                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
1111                         >;
1112                         clock-output-names =
1113                                 "vin1", "vin0", "ether";
1114                 };
1115                 mstp9_clks: mstp9_clks@e6150994 {
1116                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1117                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1118                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1119                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
1120                                  <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
1121                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1122                         #clock-cells = <1>;
1123                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1124                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1125                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1126                                          R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
1127                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1128                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1129                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1130                         clock-output-names =
1131                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1132                                 "gpio1", "gpio0", "qspi_mod",
1133                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1134                 };
1135                 mstp11_clks: mstp11_clks@e615099c {
1136                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1137                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1138                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1139                         #clock-cells = <1>;
1140                         clock-indices = <
1141                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1142                         >;
1143                         clock-output-names = "scifa3", "scifa4", "scifa5";
1144                 };
1145         };
1146
1147         ipmmu_sy0: mmu@e6280000 {
1148                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1149                 reg = <0 0xe6280000 0 0x1000>;
1150                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1151                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1152                 #iommu-cells = <1>;
1153                 status = "disabled";
1154         };
1155
1156         ipmmu_sy1: mmu@e6290000 {
1157                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1158                 reg = <0 0xe6290000 0 0x1000>;
1159                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1160                 #iommu-cells = <1>;
1161                 status = "disabled";
1162         };
1163
1164         ipmmu_ds: mmu@e6740000 {
1165                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1166                 reg = <0 0xe6740000 0 0x1000>;
1167                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1168                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1169                 #iommu-cells = <1>;
1170                 status = "disabled";
1171         };
1172
1173         ipmmu_mp: mmu@ec680000 {
1174                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1175                 reg = <0 0xec680000 0 0x1000>;
1176                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1177                 #iommu-cells = <1>;
1178                 status = "disabled";
1179         };
1180
1181         ipmmu_mx: mmu@fe951000 {
1182                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1183                 reg = <0 0xfe951000 0 0x1000>;
1184                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1185                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1186                 #iommu-cells = <1>;
1187                 status = "disabled";
1188         };
1189
1190         ipmmu_gp: mmu@e62a0000 {
1191                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1192                 reg = <0 0xe62a0000 0 0x1000>;
1193                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1194                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1195                 #iommu-cells = <1>;
1196                 status = "disabled";
1197         };
1198 };