2 * Device Tree Source for the r8a7794 SoC
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7794-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
40 compatible = "arm,cortex-a7";
42 clock-frequency = <1000000000>;
47 compatible = "arm,cortex-a7";
49 clock-frequency = <1000000000>;
53 gic: interrupt-controller@f1001000 {
54 compatible = "arm,gic-400";
55 #interrupt-cells = <3>;
58 reg = <0 0xf1001000 0 0x1000>,
59 <0 0xf1002000 0 0x1000>,
60 <0 0xf1004000 0 0x2000>,
61 <0 0xf1006000 0 0x2000>;
62 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 gpio0: gpio@e6050000 {
66 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
67 reg = <0 0xe6050000 0 0x50>;
68 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
74 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
75 power-domains = <&cpg_clocks>;
78 gpio1: gpio@e6051000 {
79 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
80 reg = <0 0xe6051000 0 0x50>;
81 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
84 gpio-ranges = <&pfc 0 32 26>;
85 #interrupt-cells = <2>;
87 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
88 power-domains = <&cpg_clocks>;
91 gpio2: gpio@e6052000 {
92 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
93 reg = <0 0xe6052000 0 0x50>;
94 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
97 gpio-ranges = <&pfc 0 64 32>;
98 #interrupt-cells = <2>;
100 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
101 power-domains = <&cpg_clocks>;
104 gpio3: gpio@e6053000 {
105 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
106 reg = <0 0xe6053000 0 0x50>;
107 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
110 gpio-ranges = <&pfc 0 96 32>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
113 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
114 power-domains = <&cpg_clocks>;
117 gpio4: gpio@e6054000 {
118 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
119 reg = <0 0xe6054000 0 0x50>;
120 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
123 gpio-ranges = <&pfc 0 128 32>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
127 power-domains = <&cpg_clocks>;
130 gpio5: gpio@e6055000 {
131 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
132 reg = <0 0xe6055000 0 0x50>;
133 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
136 gpio-ranges = <&pfc 0 160 28>;
137 #interrupt-cells = <2>;
138 interrupt-controller;
139 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
140 power-domains = <&cpg_clocks>;
143 gpio6: gpio@e6055400 {
144 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
145 reg = <0 0xe6055400 0 0x50>;
146 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
149 gpio-ranges = <&pfc 0 192 26>;
150 #interrupt-cells = <2>;
151 interrupt-controller;
152 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
153 power-domains = <&cpg_clocks>;
156 cmt0: timer@ffca0000 {
157 compatible = "renesas,cmt-48-gen2";
158 reg = <0 0xffca0000 0 0x1004>;
159 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
163 power-domains = <&cpg_clocks>;
165 renesas,channels-mask = <0x60>;
170 cmt1: timer@e6130000 {
171 compatible = "renesas,cmt-48-gen2";
172 reg = <0 0xe6130000 0 0x1004>;
173 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
183 power-domains = <&cpg_clocks>;
185 renesas,channels-mask = <0xff>;
191 compatible = "arm,armv7-timer";
192 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
193 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
194 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
195 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
198 irqc0: interrupt-controller@e61c0000 {
199 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 reg = <0 0xe61c0000 0 0x200>;
203 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
214 power-domains = <&cpg_clocks>;
217 pfc: pin-controller@e6060000 {
218 compatible = "renesas,pfc-r8a7794";
219 reg = <0 0xe6060000 0 0x11c>;
222 dmac0: dma-controller@e6700000 {
223 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
224 reg = <0 0xe6700000 0 0x20000>;
225 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
226 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
227 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
228 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
229 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
230 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
231 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
232 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
233 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
234 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
235 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
238 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
239 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-names = "error",
242 "ch0", "ch1", "ch2", "ch3",
243 "ch4", "ch5", "ch6", "ch7",
244 "ch8", "ch9", "ch10", "ch11",
245 "ch12", "ch13", "ch14";
246 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
248 power-domains = <&cpg_clocks>;
253 dmac1: dma-controller@e6720000 {
254 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
255 reg = <0 0xe6720000 0 0x20000>;
256 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
257 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
258 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
259 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
260 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
261 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
262 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
263 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
264 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
265 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
266 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
267 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "error",
273 "ch0", "ch1", "ch2", "ch3",
274 "ch4", "ch5", "ch6", "ch7",
275 "ch8", "ch9", "ch10", "ch11",
276 "ch12", "ch13", "ch14";
277 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
279 power-domains = <&cpg_clocks>;
284 scifa0: serial@e6c40000 {
285 compatible = "renesas,scifa-r8a7794",
286 "renesas,rcar-gen2-scifa", "renesas,scifa";
287 reg = <0 0xe6c40000 0 64>;
288 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
291 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
292 dma-names = "tx", "rx";
293 power-domains = <&cpg_clocks>;
297 scifa1: serial@e6c50000 {
298 compatible = "renesas,scifa-r8a7794",
299 "renesas,rcar-gen2-scifa", "renesas,scifa";
300 reg = <0 0xe6c50000 0 64>;
301 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
304 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
305 dma-names = "tx", "rx";
306 power-domains = <&cpg_clocks>;
310 scifa2: serial@e6c60000 {
311 compatible = "renesas,scifa-r8a7794",
312 "renesas,rcar-gen2-scifa", "renesas,scifa";
313 reg = <0 0xe6c60000 0 64>;
314 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
317 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
318 dma-names = "tx", "rx";
319 power-domains = <&cpg_clocks>;
323 scifa3: serial@e6c70000 {
324 compatible = "renesas,scifa-r8a7794",
325 "renesas,rcar-gen2-scifa", "renesas,scifa";
326 reg = <0 0xe6c70000 0 64>;
327 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
330 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
331 dma-names = "tx", "rx";
332 power-domains = <&cpg_clocks>;
336 scifa4: serial@e6c78000 {
337 compatible = "renesas,scifa-r8a7794",
338 "renesas,rcar-gen2-scifa", "renesas,scifa";
339 reg = <0 0xe6c78000 0 64>;
340 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
343 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
344 dma-names = "tx", "rx";
345 power-domains = <&cpg_clocks>;
349 scifa5: serial@e6c80000 {
350 compatible = "renesas,scifa-r8a7794",
351 "renesas,rcar-gen2-scifa", "renesas,scifa";
352 reg = <0 0xe6c80000 0 64>;
353 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
356 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
357 dma-names = "tx", "rx";
358 power-domains = <&cpg_clocks>;
362 scifb0: serial@e6c20000 {
363 compatible = "renesas,scifb-r8a7794",
364 "renesas,rcar-gen2-scifb", "renesas,scifb";
365 reg = <0 0xe6c20000 0 64>;
366 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
369 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
370 dma-names = "tx", "rx";
371 power-domains = <&cpg_clocks>;
375 scifb1: serial@e6c30000 {
376 compatible = "renesas,scifb-r8a7794",
377 "renesas,rcar-gen2-scifb", "renesas,scifb";
378 reg = <0 0xe6c30000 0 64>;
379 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
382 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
383 dma-names = "tx", "rx";
384 power-domains = <&cpg_clocks>;
388 scifb2: serial@e6ce0000 {
389 compatible = "renesas,scifb-r8a7794",
390 "renesas,rcar-gen2-scifb", "renesas,scifb";
391 reg = <0 0xe6ce0000 0 64>;
392 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
395 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
396 dma-names = "tx", "rx";
397 power-domains = <&cpg_clocks>;
401 scif0: serial@e6e60000 {
402 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
404 reg = <0 0xe6e60000 0 64>;
405 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
408 clock-names = "fck", "brg_int", "scif_clk";
409 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
410 dma-names = "tx", "rx";
411 power-domains = <&cpg_clocks>;
415 scif1: serial@e6e68000 {
416 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
418 reg = <0 0xe6e68000 0 64>;
419 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
422 clock-names = "fck", "brg_int", "scif_clk";
423 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
424 dma-names = "tx", "rx";
425 power-domains = <&cpg_clocks>;
429 scif2: serial@e6e58000 {
430 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
432 reg = <0 0xe6e58000 0 64>;
433 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
436 clock-names = "fck", "brg_int", "scif_clk";
437 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
438 dma-names = "tx", "rx";
439 power-domains = <&cpg_clocks>;
443 scif3: serial@e6ea8000 {
444 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
446 reg = <0 0xe6ea8000 0 64>;
447 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
450 clock-names = "fck", "brg_int", "scif_clk";
451 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
452 dma-names = "tx", "rx";
453 power-domains = <&cpg_clocks>;
457 scif4: serial@e6ee0000 {
458 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
460 reg = <0 0xe6ee0000 0 64>;
461 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
464 clock-names = "fck", "brg_int", "scif_clk";
465 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
466 dma-names = "tx", "rx";
467 power-domains = <&cpg_clocks>;
471 scif5: serial@e6ee8000 {
472 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
474 reg = <0 0xe6ee8000 0 64>;
475 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
478 clock-names = "fck", "brg_int", "scif_clk";
479 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
480 dma-names = "tx", "rx";
481 power-domains = <&cpg_clocks>;
485 hscif0: serial@e62c0000 {
486 compatible = "renesas,hscif-r8a7794",
487 "renesas,rcar-gen2-hscif", "renesas,hscif";
488 reg = <0 0xe62c0000 0 96>;
489 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
492 clock-names = "fck", "brg_int", "scif_clk";
493 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
494 dma-names = "tx", "rx";
495 power-domains = <&cpg_clocks>;
499 hscif1: serial@e62c8000 {
500 compatible = "renesas,hscif-r8a7794",
501 "renesas,rcar-gen2-hscif", "renesas,hscif";
502 reg = <0 0xe62c8000 0 96>;
503 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
506 clock-names = "fck", "brg_int", "scif_clk";
507 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
508 dma-names = "tx", "rx";
509 power-domains = <&cpg_clocks>;
513 hscif2: serial@e62d0000 {
514 compatible = "renesas,hscif-r8a7794",
515 "renesas,rcar-gen2-hscif", "renesas,hscif";
516 reg = <0 0xe62d0000 0 96>;
517 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
520 clock-names = "fck", "brg_int", "scif_clk";
521 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
522 dma-names = "tx", "rx";
523 power-domains = <&cpg_clocks>;
527 ether: ethernet@ee700000 {
528 compatible = "renesas,ether-r8a7794";
529 reg = <0 0xee700000 0 0x400>;
530 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
532 power-domains = <&cpg_clocks>;
534 #address-cells = <1>;
539 /* The memory map in the User's Manual maps the cores to bus numbers */
541 compatible = "renesas,i2c-r8a7794";
542 reg = <0 0xe6508000 0 0x40>;
543 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
545 power-domains = <&cpg_clocks>;
546 #address-cells = <1>;
548 i2c-scl-internal-delay-ns = <6>;
553 compatible = "renesas,i2c-r8a7794";
554 reg = <0 0xe6518000 0 0x40>;
555 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
557 power-domains = <&cpg_clocks>;
558 #address-cells = <1>;
560 i2c-scl-internal-delay-ns = <6>;
565 compatible = "renesas,i2c-r8a7794";
566 reg = <0 0xe6530000 0 0x40>;
567 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
569 power-domains = <&cpg_clocks>;
570 #address-cells = <1>;
572 i2c-scl-internal-delay-ns = <6>;
577 compatible = "renesas,i2c-r8a7794";
578 reg = <0 0xe6540000 0 0x40>;
579 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
581 power-domains = <&cpg_clocks>;
582 #address-cells = <1>;
584 i2c-scl-internal-delay-ns = <6>;
589 compatible = "renesas,i2c-r8a7794";
590 reg = <0 0xe6520000 0 0x40>;
591 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
593 power-domains = <&cpg_clocks>;
594 #address-cells = <1>;
596 i2c-scl-internal-delay-ns = <6>;
601 compatible = "renesas,i2c-r8a7794";
602 reg = <0 0xe6528000 0 0x40>;
603 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
605 power-domains = <&cpg_clocks>;
606 #address-cells = <1>;
608 i2c-scl-internal-delay-ns = <6>;
612 mmcif0: mmc@ee200000 {
613 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
614 reg = <0 0xee200000 0 0x80>;
615 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
617 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
618 dma-names = "tx", "rx";
619 power-domains = <&cpg_clocks>;
625 compatible = "renesas,sdhi-r8a7794";
626 reg = <0 0xee100000 0 0x200>;
627 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
629 power-domains = <&cpg_clocks>;
634 compatible = "renesas,sdhi-r8a7794";
635 reg = <0 0xee140000 0 0x100>;
636 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
638 power-domains = <&cpg_clocks>;
643 compatible = "renesas,sdhi-r8a7794";
644 reg = <0 0xee160000 0 0x100>;
645 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
647 power-domains = <&cpg_clocks>;
652 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
653 reg = <0 0xe6b10000 0 0x2c>;
654 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
656 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
657 dma-names = "tx", "rx";
658 power-domains = <&cpg_clocks>;
660 #address-cells = <1>;
665 vin0: video@e6ef0000 {
666 compatible = "renesas,vin-r8a7794";
667 reg = <0 0xe6ef0000 0 0x1000>;
668 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
670 power-domains = <&cpg_clocks>;
674 vin1: video@e6ef1000 {
675 compatible = "renesas,vin-r8a7794";
676 reg = <0 0xe6ef1000 0 0x1000>;
677 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
679 power-domains = <&cpg_clocks>;
684 compatible = "renesas,pci-r8a7794";
686 reg = <0 0xee090000 0 0xc00>,
687 <0 0xee080000 0 0x1100>;
688 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
690 power-domains = <&cpg_clocks>;
694 #address-cells = <3>;
696 #interrupt-cells = <1>;
697 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
698 interrupt-map-mask = <0xff00 0 0 0x7>;
699 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
700 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
701 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
704 reg = <0x800 0 0 0 0>;
711 reg = <0x1000 0 0 0 0>;
719 compatible = "renesas,pci-r8a7794";
721 reg = <0 0xee0d0000 0 0xc00>,
722 <0 0xee0c0000 0 0x1100>;
723 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
725 power-domains = <&cpg_clocks>;
729 #address-cells = <3>;
731 #interrupt-cells = <1>;
732 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
733 interrupt-map-mask = <0xff00 0 0 0x7>;
734 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
735 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
736 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
739 reg = <0x800 0 0 0 0>;
746 reg = <0x1000 0 0 0 0>;
753 hsusb: usb@e6590000 {
754 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
755 reg = <0 0xe6590000 0 0x100>;
756 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
758 power-domains = <&cpg_clocks>;
759 renesas,buswait = <4>;
765 usbphy: usb-phy@e6590100 {
766 compatible = "renesas,usb-phy-r8a7794";
767 reg = <0 0xe6590100 0 0x100>;
768 #address-cells = <1>;
770 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
771 clock-names = "usbhs";
772 power-domains = <&cpg_clocks>;
775 usb0: usb-channel@0 {
779 usb2: usb-channel@2 {
785 du: display@feb00000 {
786 compatible = "renesas,du-r8a7794";
787 reg = <0 0xfeb00000 0 0x40000>;
789 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
792 <&mstp7_clks R8A7794_CLK_DU0>;
793 clock-names = "du.0", "du.1";
797 #address-cells = <1>;
802 du_out_rgb0: endpoint {
807 du_out_rgb1: endpoint {
814 #address-cells = <2>;
818 /* External root clock */
819 extal_clk: extal_clk {
820 compatible = "fixed-clock";
822 /* This value must be overriden by the board. */
823 clock-frequency = <0>;
824 clock-output-names = "extal";
827 /* External SCIF clock */
829 compatible = "fixed-clock";
831 /* This value must be overridden by the board. */
832 clock-frequency = <0>;
836 /* Special CPG clocks */
837 cpg_clocks: cpg_clocks@e6150000 {
838 compatible = "renesas,r8a7794-cpg-clocks",
839 "renesas,rcar-gen2-cpg-clocks";
840 reg = <0 0xe6150000 0 0x1000>;
841 clocks = <&extal_clk>;
843 clock-output-names = "main", "pll0", "pll1", "pll3",
844 "lb", "qspi", "sdh", "sd0", "z";
845 #power-domain-cells = <0>;
847 /* Variable factor clocks */
848 sd2_clk: sd2_clk@e6150078 {
849 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
850 reg = <0 0xe6150078 0 4>;
851 clocks = <&pll1_div2_clk>;
853 clock-output-names = "sd2";
855 sd3_clk: sd3_clk@e615026c {
856 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
857 reg = <0 0xe615026c 0 4>;
858 clocks = <&pll1_div2_clk>;
860 clock-output-names = "sd3";
862 mmc0_clk: mmc0_clk@e6150240 {
863 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
864 reg = <0 0xe6150240 0 4>;
865 clocks = <&pll1_div2_clk>;
867 clock-output-names = "mmc0";
870 /* Fixed factor clocks */
871 pll1_div2_clk: pll1_div2_clk {
872 compatible = "fixed-factor-clock";
873 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
877 clock-output-names = "pll1_div2";
880 compatible = "fixed-factor-clock";
881 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
885 clock-output-names = "zg";
888 compatible = "fixed-factor-clock";
889 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
893 clock-output-names = "zx";
896 compatible = "fixed-factor-clock";
897 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
901 clock-output-names = "zs";
904 compatible = "fixed-factor-clock";
905 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
909 clock-output-names = "hp";
912 compatible = "fixed-factor-clock";
913 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
917 clock-output-names = "i";
920 compatible = "fixed-factor-clock";
921 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
925 clock-output-names = "b";
928 compatible = "fixed-factor-clock";
929 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
933 clock-output-names = "p";
936 compatible = "fixed-factor-clock";
937 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
941 clock-output-names = "cl";
944 compatible = "fixed-factor-clock";
945 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
949 clock-output-names = "m2";
952 compatible = "fixed-factor-clock";
953 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
955 clock-div = <(48 * 1024)>;
957 clock-output-names = "rclk";
959 oscclk_clk: oscclk_clk {
960 compatible = "fixed-factor-clock";
961 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
963 clock-div = <(12 * 1024)>;
965 clock-output-names = "oscclk";
968 compatible = "fixed-factor-clock";
969 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
973 clock-output-names = "zb3";
975 zb3d2_clk: zb3d2_clk {
976 compatible = "fixed-factor-clock";
977 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
981 clock-output-names = "zb3d2";
984 compatible = "fixed-factor-clock";
985 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
989 clock-output-names = "ddr";
992 compatible = "fixed-factor-clock";
993 clocks = <&pll1_div2_clk>;
997 clock-output-names = "mp";
1000 compatible = "fixed-factor-clock";
1001 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1005 clock-output-names = "cp";
1009 compatible = "fixed-factor-clock";
1010 clocks = <&extal_clk>;
1014 clock-output-names = "acp";
1018 mstp0_clks: mstp0_clks@e6150130 {
1019 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1020 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1023 clock-indices = <R8A7794_CLK_MSIOF0>;
1024 clock-output-names = "msiof0";
1026 mstp1_clks: mstp1_clks@e6150134 {
1027 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1028 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1029 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1030 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1031 <&zs_clk>, <&zs_clk>;
1034 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1035 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1036 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1037 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1039 clock-output-names =
1040 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1041 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1043 mstp2_clks: mstp2_clks@e6150138 {
1044 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1045 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1046 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1047 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1048 <&zs_clk>, <&zs_clk>;
1051 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1052 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1053 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1054 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1056 clock-output-names =
1057 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1058 "scifb1", "msiof1", "scifb2",
1059 "sys-dmac1", "sys-dmac0";
1061 mstp3_clks: mstp3_clks@e615013c {
1062 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1063 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1064 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1065 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1068 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1069 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
1070 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1072 clock-output-names =
1073 "sdhi2", "sdhi1", "sdhi0",
1074 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
1076 mstp4_clks: mstp4_clks@e6150140 {
1077 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1078 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1081 clock-indices = <R8A7794_CLK_IRQC>;
1082 clock-output-names = "irqc";
1084 mstp7_clks: mstp7_clks@e615014c {
1085 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1086 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1087 clocks = <&mp_clk>, <&mp_clk>,
1088 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1089 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1093 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1094 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1095 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1096 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1097 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1099 clock-output-names =
1101 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1102 "scif3", "scif2", "scif1", "scif0", "du0";
1104 mstp8_clks: mstp8_clks@e6150990 {
1105 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1106 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1107 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
1110 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
1112 clock-output-names =
1113 "vin1", "vin0", "ether";
1115 mstp9_clks: mstp9_clks@e6150994 {
1116 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1117 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1118 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1119 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1120 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
1121 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1123 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1124 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1125 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1126 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
1127 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1128 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1129 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1130 clock-output-names =
1131 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1132 "gpio1", "gpio0", "qspi_mod",
1133 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1135 mstp11_clks: mstp11_clks@e615099c {
1136 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1137 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1138 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1141 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1143 clock-output-names = "scifa3", "scifa4", "scifa5";
1147 ipmmu_sy0: mmu@e6280000 {
1148 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1149 reg = <0 0xe6280000 0 0x1000>;
1150 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1153 status = "disabled";
1156 ipmmu_sy1: mmu@e6290000 {
1157 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1158 reg = <0 0xe6290000 0 0x1000>;
1159 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1161 status = "disabled";
1164 ipmmu_ds: mmu@e6740000 {
1165 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1166 reg = <0 0xe6740000 0 0x1000>;
1167 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1170 status = "disabled";
1173 ipmmu_mp: mmu@ec680000 {
1174 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1175 reg = <0 0xec680000 0 0x1000>;
1176 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1178 status = "disabled";
1181 ipmmu_mx: mmu@fe951000 {
1182 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1183 reg = <0 0xfe951000 0 0x1000>;
1184 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1187 status = "disabled";
1190 ipmmu_gp: mmu@e62a0000 {
1191 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1192 reg = <0 0xe62a0000 0 0x1000>;
1193 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1196 status = "disabled";