arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 spi = &spi;
  64         };
  65
  66         memory {
  67                 device_type = "memory";
  68                 reg = <0x60000000 0x40000000>;
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 enable-method = "rockchip,rk3036-smp";
  75
  76                 cpu0: cpu@f00 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0xf00>;
  80                         resets = <&cru SRST_CORE0>;
  81                         operating-points = <
  82                                 /* KHz    uV */
  83                                  816000 1000000
  84                         >;
  85                         clock-latency = <40000>;
  86                         clocks = <&cru ARMCLK>;
  87                 };
  88
  89                 cpu1: cpu@f01 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a7";
  92                         reg = <0xf01>;
  93                         resets = <&cru SRST_CORE1>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 pdma: pdma@20078000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0x20078000 0x4000>;
 106                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         arm,pl330-broken-no-flushp;
 110                         clocks = <&cru ACLK_DMAC2>;
 111                         clock-names = "apb_pclk";
 112                 };
 113         };
 114
 115         arm-pmu {
 116                 compatible = "arm,cortex-a7-pmu";
 117                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 119                 interrupt-affinity = <&cpu0>, <&cpu1>;
 120         };
 121
 122         timer {
 123                 compatible = "arm,armv7-timer";
 124                 arm,cpu-registers-not-fw-configured;
 125                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 126                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 129                 clock-frequency = <24000000>;
 130         };
 131
 132         xin24m: oscillator {
 133                 compatible = "fixed-clock";
 134                 clock-frequency = <24000000>;
 135                 clock-output-names = "xin24m";
 136                 #clock-cells = <0>;
 137         };
 138
 139         bus_intmem@10080000 {
 140                 compatible = "mmio-sram";
 141                 reg = <0x10080000 0x2000>;
 142                 #address-cells = <1>;
 143                 #size-cells = <1>;
 144                 ranges = <0 0x10080000 0x2000>;
 145
 146                 smp-sram@0 {
 147                         compatible = "rockchip,rk3066-smp-sram";
 148                         reg = <0x00 0x10>;
 149                 };
 150         };
 151
 152         gic: interrupt-controller@10139000 {
 153                 compatible = "arm,gic-400";
 154                 interrupt-controller;
 155                 #interrupt-cells = <3>;
 156                 #address-cells = <0>;
 157
 158                 reg = <0x10139000 0x1000>,
 159                       <0x1013a000 0x1000>,
 160                       <0x1013c000 0x2000>,
 161                       <0x1013e000 0x2000>;
 162                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 163         };
 164
 165         usb_otg: usb@10180000 {
 166                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 167                                 "snps,dwc2";
 168                 reg = <0x10180000 0x40000>;
 169                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&cru HCLK_OTG0>;
 171                 clock-names = "otg";
 172                 dr_mode = "otg";
 173                 g-np-tx-fifo-size = <16>;
 174                 g-rx-fifo-size = <275>;
 175                 g-tx-fifo-size = <256 128 128 64 64 32>;
 176                 g-use-dma;
 177                 status = "disabled";
 178         };
 179
 180         usb_host: usb@101c0000 {
 181                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 182                                 "snps,dwc2";
 183                 reg = <0x101c0000 0x40000>;
 184                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&cru HCLK_OTG1>;
 186                 clock-names = "otg";
 187                 dr_mode = "host";
 188                 status = "disabled";
 189         };
 190
 191         sdmmc: dwmmc@10214000 {
 192                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 193                 reg = <0x10214000 0x4000>;
 194                 clock-frequency = <37500000>;
 195                 clock-freq-min-max = <400000 37500000>;
 196                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 197                 clock-names = "biu", "ciu";
 198                 fifo-depth = <0x100>;
 199                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 200                 status = "disabled";
 201         };
 202
 203         sdio: dwmmc@10218000 {
 204                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 205                 reg = <0x10218000 0x4000>;
 206                 clock-freq-min-max = <400000 37500000>;
 207                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 208                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 209                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 210                 fifo-depth = <0x100>;
 211                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 212                 status = "disabled";
 213         };
 214
 215         emmc: dwmmc@1021c000 {
 216                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 217                 reg = <0x1021c000 0x4000>;
 218                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 219                 broken-cd;
 220                 bus-width = <8>;
 221                 cap-mmc-highspeed;
 222                 clock-frequency = <37500000>;
 223                 clock-freq-min-max = <400000 37500000>;
 224                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 225                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 226                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 227                 default-sample-phase = <158>;
 228                 disable-wp;
 229                 dmas = <&pdma 12>;
 230                 dma-names = "rx-tx";
 231                 fifo-depth = <0x100>;
 232                 mmc-ddr-1_8v;
 233                 non-removable;
 234                 num-slots = <1>;
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 237                 status = "disabled";
 238         };
 239
 240         i2s: i2s@10220000 {
 241                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 242                 reg = <0x10220000 0x4000>;
 243                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 clock-names = "i2s_clk", "i2s_hclk";
 247                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 248                 dmas = <&pdma 0>, <&pdma 1>;
 249                 dma-names = "tx", "rx";
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&i2s_bus>;
 252                 status = "disabled";
 253         };
 254
 255         cru: clock-controller@20000000 {
 256                 compatible = "rockchip,rk3036-cru";
 257                 reg = <0x20000000 0x1000>;
 258                 rockchip,grf = <&grf>;
 259                 #clock-cells = <1>;
 260                 #reset-cells = <1>;
 261                 assigned-clocks = <&cru PLL_GPLL>;
 262                 assigned-clock-rates = <594000000>;
 263         };
 264
 265         grf: syscon@20008000 {
 266                 compatible = "rockchip,rk3036-grf", "syscon";
 267                 reg = <0x20008000 0x1000>;
 268         };
 269
 270         acodec: acodec-ana@20030000 {
 271                 compatible = "rk3036-codec";
 272                 reg = <0x20030000 0x4000>;
 273                 rockchip,grf = <&grf>;
 274                 clock-names = "acodec_pclk";
 275                 clocks = <&cru PCLK_ACODEC>;
 276                 status = "disabled";
 277         };
 278
 279         timer: timer@20044000 {
 280                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 281                 reg = <0x20044000 0x20>;
 282                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 284                 clock-names = "timer", "pclk";
 285         };
 286
 287         pwm0: pwm@20050000 {
 288                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 289                 reg = <0x20050000 0x10>;
 290                 #pwm-cells = <3>;
 291                 clocks = <&cru PCLK_PWM>;
 292                 clock-names = "pwm";
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&pwm0_pin>;
 295                 status = "disabled";
 296         };
 297
 298         pwm1: pwm@20050010 {
 299                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 300                 reg = <0x20050010 0x10>;
 301                 #pwm-cells = <3>;
 302                 clocks = <&cru PCLK_PWM>;
 303                 clock-names = "pwm";
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&pwm1_pin>;
 306                 status = "disabled";
 307         };
 308
 309         pwm2: pwm@20050020 {
 310                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 311                 reg = <0x20050020 0x10>;
 312                 #pwm-cells = <3>;
 313                 clocks = <&cru PCLK_PWM>;
 314                 clock-names = "pwm";
 315                 pinctrl-names = "default";
 316                 pinctrl-0 = <&pwm2_pin>;
 317                 status = "disabled";
 318         };
 319
 320         pwm3: pwm@20050030 {
 321                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 322                 reg = <0x20050030 0x10>;
 323                 #pwm-cells = <2>;
 324                 clocks = <&cru PCLK_PWM>;
 325                 clock-names = "pwm";
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&pwm3_pin>;
 328                 status = "disabled";
 329         };
 330
 331         i2c1: i2c@20056000 {
 332                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 333                 reg = <0x20056000 0x1000>;
 334                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 clock-names = "i2c";
 338                 clocks = <&cru PCLK_I2C1>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&i2c1_xfer>;
 341                 status = "disabled";
 342         };
 343
 344         i2c2: i2c@2005a000 {
 345                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 346                 reg = <0x2005a000 0x1000>;
 347                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 clock-names = "i2c";
 351                 clocks = <&cru PCLK_I2C2>;
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&i2c2_xfer>;
 354                 status = "disabled";
 355         };
 356
 357         uart0: serial@20060000 {
 358                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 359                 reg = <0x20060000 0x100>;
 360                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 361                 reg-shift = <2>;
 362                 reg-io-width = <4>;
 363                 clock-frequency = <24000000>;
 364                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 365                 clock-names = "baudclk", "apb_pclk";
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 368                 status = "disabled";
 369         };
 370
 371         uart1: serial@20064000 {
 372                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 373                 reg = <0x20064000 0x100>;
 374                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 375                 reg-shift = <2>;
 376                 reg-io-width = <4>;
 377                 clock-frequency = <24000000>;
 378                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 379                 clock-names = "baudclk", "apb_pclk";
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&uart1_xfer>;
 382                 status = "disabled";
 383         };
 384
 385         uart2: serial@20068000 {
 386                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 387                 reg = <0x20068000 0x100>;
 388                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 389                 reg-shift = <2>;
 390                 reg-io-width = <4>;
 391                 clock-frequency = <24000000>;
 392                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 393                 clock-names = "baudclk", "apb_pclk";
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&uart2_xfer>;
 396                 status = "disabled";
 397         };
 398
 399         i2c0: i2c@20072000 {
 400                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 401                 reg = <0x20072000 0x1000>;
 402                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 clock-names = "i2c";
 406                 clocks = <&cru PCLK_I2C0>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&i2c0_xfer>;
 409                 status = "disabled";
 410         };
 411
 412         spi: spi@20074000 {
 413                 compatible = "rockchip,rockchip-spi";
 414                 reg = <0x20074000 0x1000>;
 415                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 417                 clock-names = "apb-pclk","spi_pclk";
 418                 dmas = <&pdma 8>, <&pdma 9>;
 419                 dma-names = "tx", "rx";
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 status = "disabled";
 425         };
 426
 427         pinctrl: pinctrl {
 428                 compatible = "rockchip,rk3036-pinctrl";
 429                 rockchip,grf = <&grf>;
 430                 #address-cells = <1>;
 431                 #size-cells = <1>;
 432                 ranges;
 433
 434                 gpio0: gpio0@2007c000 {
 435                         compatible = "rockchip,gpio-bank";
 436                         reg = <0x2007c000 0x100>;
 437                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&cru PCLK_GPIO0>;
 439
 440                         gpio-controller;
 441                         #gpio-cells = <2>;
 442
 443                         interrupt-controller;
 444                         #interrupt-cells = <2>;
 445                 };
 446
 447                 gpio1: gpio1@20080000 {
 448                         compatible = "rockchip,gpio-bank";
 449                         reg = <0x20080000 0x100>;
 450                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&cru PCLK_GPIO1>;
 452
 453                         gpio-controller;
 454                         #gpio-cells = <2>;
 455
 456                         interrupt-controller;
 457                         #interrupt-cells = <2>;
 458                 };
 459
 460                 gpio2: gpio2@20084000 {
 461                         compatible = "rockchip,gpio-bank";
 462                         reg = <0x20084000 0x100>;
 463                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&cru PCLK_GPIO2>;
 465
 466                         gpio-controller;
 467                         #gpio-cells = <2>;
 468
 469                         interrupt-controller;
 470                         #interrupt-cells = <2>;
 471                 };
 472
 473                 pcfg_pull_default: pcfg_pull_default {
 474                         bias-pull-pin-default;
 475                 };
 476
 477                 pcfg_pull_none: pcfg-pull-none {
 478                         bias-disable;
 479                 };
 480
 481                 pwm0 {
 482                         pwm0_pin: pwm0-pin {
 483                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 484                         };
 485                 };
 486
 487                 pwm1 {
 488                         pwm1_pin: pwm1-pin {
 489                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 490                         };
 491                 };
 492
 493                 pwm2 {
 494                         pwm2_pin: pwm2-pin {
 495                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 496                         };
 497                 };
 498
 499                 pwm3 {
 500                         pwm3_pin: pwm3-pin {
 501                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 502                         };
 503                 };
 504
 505                 sdmmc {
 506                         sdmmc_clk: sdmmc-clk {
 507                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 508                         };
 509
 510                         sdmmc_cmd: sdmmc-cmd {
 511                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 512                         };
 513
 514                         sdmmc_cd: sdmcc-cd {
 515                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 516                         };
 517
 518                         sdmmc_bus1: sdmmc-bus1 {
 519                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 520                         };
 521
 522                         sdmmc_bus4: sdmmc-bus4 {
 523                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 524                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 525                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 526                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 527                         };
 528                 };
 529
 530                 sdio {
 531                         sdio_bus1: sdio-bus1 {
 532                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 533                         };
 534
 535                         sdio_bus4: sdio-bus4 {
 536                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 537                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 538                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 539                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 540                         };
 541
 542                         sdio_cmd: sdio-cmd {
 543                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 544                         };
 545
 546                         sdio_clk: sdio-clk {
 547                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 548                         };
 549                 };
 550
 551                 emmc {
 552                         /*
 553                          * We run eMMC at max speed; bump up drive strength.
 554                          * We also have external pulls, so disable the internal ones.
 555                          */
 556                         emmc_clk: emmc-clk {
 557                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 558                         };
 559
 560                         emmc_cmd: emmc-cmd {
 561                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 562                         };
 563
 564                         emmc_bus8: emmc-bus8 {
 565                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 566                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 567                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 568                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 569                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 570                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 571                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 572                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 573                         };
 574                 };
 575
 576                 i2c0 {
 577                         i2c0_xfer: i2c0-xfer {
 578                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 579                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 580                         };
 581                 };
 582
 583                 i2c1 {
 584                         i2c1_xfer: i2c1-xfer {
 585                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 586                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 587                         };
 588                 };
 589
 590                 i2c2 {
 591                         i2c2_xfer: i2c2-xfer {
 592                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 593                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 594                         };
 595                 };
 596
 597                 i2s {
 598                         i2s_bus: i2s-bus {
 599                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 600                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 601                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 602                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 603                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 604                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 605                         };
 606                 };
 607
 608                 uart0 {
 609                         uart0_xfer: uart0-xfer {
 610                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 611                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 612                         };
 613
 614                         uart0_cts: uart0-cts {
 615                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 616                         };
 617
 618                         uart0_rts: uart0-rts {
 619                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 620                         };
 621                 };
 622
 623                 uart1 {
 624                         uart1_xfer: uart1-xfer {
 625                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 626                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 627                         };
 628                         /* no rts / cts for uart1 */
 629                 };
 630
 631                 uart2 {
 632                         uart2_xfer: uart2-xfer {
 633                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 634                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 635                         };
 636                         /* no rts / cts for uart2 */
 637                 };
 638
 639                 spi {
 640                         spi_txd:spi-txd {
 641                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 642                         };
 643
 644                         spi_rxd:spi-rxd {
 645                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 646                         };
 647
 648                         spi_clk:spi-clk {
 649                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 650                         };
 651
 652                         spi_cs0:spi-cs0 {
 653                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 654
 655                         };
 656
 657                         spi_cs1:spi-cs1 {
 658                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 659
 660                         };
 661                 };
 662         };
 663 };