2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include <dt-bindings/soc/rockchip,boot-mode.h>
52 compatible = "rockchip,rk3036";
54 interrupt-parent = <&gic>;
72 enable-method = "rockchip,rk3036-smp";
76 compatible = "arm,cortex-a7";
78 resets = <&cru SRST_CORE0>;
83 clock-latency = <40000>;
84 clocks = <&cru ARMCLK>;
89 compatible = "arm,cortex-a7";
91 resets = <&cru SRST_CORE1>;
96 compatible = "simple-bus";
101 pdma: pdma@20078000 {
102 compatible = "arm,pl330", "arm,primecell";
103 reg = <0x20078000 0x4000>;
104 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
107 arm,pl330-broken-no-flushp;
108 clocks = <&cru ACLK_DMAC2>;
109 clock-names = "apb_pclk";
114 compatible = "arm,cortex-a7-pmu";
115 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
117 interrupt-affinity = <&cpu0>, <&cpu1>;
121 compatible = "rockchip,display-subsystem";
126 compatible = "arm,armv7-timer";
127 arm,cpu-registers-not-fw-configured;
128 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
131 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
132 clock-frequency = <24000000>;
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
142 bus_intmem@10080000 {
143 compatible = "mmio-sram";
144 reg = <0x10080000 0x2000>;
145 #address-cells = <1>;
147 ranges = <0 0x10080000 0x2000>;
150 compatible = "rockchip,rk3066-smp-sram";
156 compatible = "rockchip,rk3036-vop";
157 reg = <0x10118000 0x19c>;
158 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
160 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
161 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
162 reset-names = "axi", "ahb", "dclk";
167 #address-cells = <1>;
169 vop_out_hdmi: endpoint@0 {
171 remote-endpoint = <&hdmi_in_vop>;
176 vop_mmu: iommu@10118300 {
177 compatible = "rockchip,iommu";
178 reg = <0x10118300 0x100>;
179 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "vop_mmu";
185 gic: interrupt-controller@10139000 {
186 compatible = "arm,gic-400";
187 interrupt-controller;
188 #interrupt-cells = <3>;
189 #address-cells = <0>;
191 reg = <0x10139000 0x1000>,
195 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
198 usb_otg: usb@10180000 {
199 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
201 reg = <0x10180000 0x40000>;
202 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cru HCLK_OTG0>;
206 g-np-tx-fifo-size = <16>;
207 g-rx-fifo-size = <275>;
208 g-tx-fifo-size = <256 128 128 64 64 32>;
212 usb_host: usb@101c0000 {
213 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
215 reg = <0x101c0000 0x40000>;
216 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru HCLK_OTG1>;
223 emac: ethernet@10200000 {
224 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
225 reg = <0x10200000 0x4000>;
226 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
227 #address-cells = <1>;
229 rockchip,grf = <&grf>;
230 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
231 clock-names = "hclk", "macref", "macclk";
233 * Fix the emac parent clock is DPLL instead of APLL.
234 * since that will cause some unstable things if the cpufreq
235 * is working. (e.g: the accurate 50MHz what mac_ref need)
237 assigned-clocks = <&cru SCLK_MACPLL>;
238 assigned-clock-parents = <&cru PLL_DPLL>;
244 sdmmc: dwmmc@10214000 {
245 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
246 reg = <0x10214000 0x4000>;
247 clock-frequency = <37500000>;
248 max-frequency = <37500000>;
249 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
250 clock-names = "biu", "ciu";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
253 resets = <&cru SRST_MMC0>;
254 reset-names = "reset";
258 sdio: dwmmc@10218000 {
259 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
260 reg = <0x10218000 0x4000>;
261 max-frequency = <37500000>;
262 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
263 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
267 resets = <&cru SRST_SDIO>;
268 reset-names = "reset";
272 emmc: dwmmc@1021c000 {
273 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
274 reg = <0x1021c000 0x4000>;
275 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
278 clock-frequency = <37500000>;
279 max-frequency = <37500000>;
280 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
281 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
282 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
283 default-sample-phase = <158>;
287 fifo-depth = <0x100>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
293 resets = <&cru SRST_EMMC>;
294 reset-names = "reset";
299 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
300 reg = <0x10220000 0x4000>;
301 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
302 #address-cells = <1>;
304 clock-names = "i2s_clk", "i2s_hclk";
305 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
306 dmas = <&pdma 0>, <&pdma 1>;
307 dma-names = "tx", "rx";
308 pinctrl-names = "default";
309 pinctrl-0 = <&i2s_bus>;
313 cru: clock-controller@20000000 {
314 compatible = "rockchip,rk3036-cru";
315 reg = <0x20000000 0x1000>;
316 rockchip,grf = <&grf>;
319 assigned-clocks = <&cru PLL_GPLL>;
320 assigned-clock-rates = <594000000>;
323 grf: syscon@20008000 {
324 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
325 reg = <0x20008000 0x1000>;
328 compatible = "syscon-reboot-mode";
330 mode-normal = <BOOT_NORMAL>;
331 mode-recovery = <BOOT_RECOVERY>;
332 mode-bootloader = <BOOT_FASTBOOT>;
333 mode-loader = <BOOT_BL_DOWNLOAD>;
337 acodec: acodec-ana@20030000 {
338 compatible = "rk3036-codec";
339 reg = <0x20030000 0x4000>;
340 rockchip,grf = <&grf>;
341 clock-names = "acodec_pclk";
342 clocks = <&cru PCLK_ACODEC>;
346 hdmi: hdmi@20034000 {
347 compatible = "rockchip,rk3036-inno-hdmi";
348 reg = <0x20034000 0x4000>;
349 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&cru PCLK_HDMI>;
351 clock-names = "pclk";
352 rockchip,grf = <&grf>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&hdmi_ctl>;
358 #address-cells = <1>;
360 hdmi_in_vop: endpoint@0 {
362 remote-endpoint = <&vop_out_hdmi>;
367 timer: timer@20044000 {
368 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
369 reg = <0x20044000 0x20>;
370 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&xin24m>, <&cru PCLK_TIMER>;
372 clock-names = "timer", "pclk";
376 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
377 reg = <0x20050000 0x10>;
379 clocks = <&cru PCLK_PWM>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pwm0_pin>;
387 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
388 reg = <0x20050010 0x10>;
390 clocks = <&cru PCLK_PWM>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pwm1_pin>;
398 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
399 reg = <0x20050020 0x10>;
401 clocks = <&cru PCLK_PWM>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pwm2_pin>;
409 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
410 reg = <0x20050030 0x10>;
412 clocks = <&cru PCLK_PWM>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pwm3_pin>;
420 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
421 reg = <0x20056000 0x1000>;
422 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
426 clocks = <&cru PCLK_I2C1>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c1_xfer>;
433 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
434 reg = <0x2005a000 0x1000>;
435 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
436 #address-cells = <1>;
439 clocks = <&cru PCLK_I2C2>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c2_xfer>;
445 uart0: serial@20060000 {
446 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
447 reg = <0x20060000 0x100>;
448 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
451 clock-frequency = <24000000>;
452 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
453 clock-names = "baudclk", "apb_pclk";
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
459 uart1: serial@20064000 {
460 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
461 reg = <0x20064000 0x100>;
462 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
465 clock-frequency = <24000000>;
466 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
467 clock-names = "baudclk", "apb_pclk";
468 pinctrl-names = "default";
469 pinctrl-0 = <&uart1_xfer>;
473 uart2: serial@20068000 {
474 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
475 reg = <0x20068000 0x100>;
476 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
479 clock-frequency = <24000000>;
480 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
481 clock-names = "baudclk", "apb_pclk";
482 pinctrl-names = "default";
483 pinctrl-0 = <&uart2_xfer>;
488 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
489 reg = <0x20072000 0x1000>;
490 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
494 clocks = <&cru PCLK_I2C0>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&i2c0_xfer>;
501 compatible = "rockchip,rockchip-spi";
502 reg = <0x20074000 0x1000>;
503 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
504 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
505 clock-names = "apb-pclk","spi_pclk";
506 dmas = <&pdma 8>, <&pdma 9>;
507 dma-names = "tx", "rx";
508 pinctrl-names = "default";
509 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
510 #address-cells = <1>;
516 compatible = "rockchip,rk3036-pinctrl";
517 rockchip,grf = <&grf>;
518 #address-cells = <1>;
522 gpio0: gpio0@2007c000 {
523 compatible = "rockchip,gpio-bank";
524 reg = <0x2007c000 0x100>;
525 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cru PCLK_GPIO0>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
535 gpio1: gpio1@20080000 {
536 compatible = "rockchip,gpio-bank";
537 reg = <0x20080000 0x100>;
538 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&cru PCLK_GPIO1>;
544 interrupt-controller;
545 #interrupt-cells = <2>;
548 gpio2: gpio2@20084000 {
549 compatible = "rockchip,gpio-bank";
550 reg = <0x20084000 0x100>;
551 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&cru PCLK_GPIO2>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
561 pcfg_pull_default: pcfg_pull_default {
562 bias-pull-pin-default;
565 pcfg_pull_none: pcfg-pull-none {
571 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
577 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
583 rockchip,pins = <0 1 2 &pcfg_pull_none>;
589 rockchip,pins = <0 27 1 &pcfg_pull_none>;
594 sdmmc_clk: sdmmc-clk {
595 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
598 sdmmc_cmd: sdmmc-cmd {
599 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
603 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
606 sdmmc_bus1: sdmmc-bus1 {
607 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
610 sdmmc_bus4: sdmmc-bus4 {
611 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
612 <1 19 RK_FUNC_1 &pcfg_pull_default>,
613 <1 20 RK_FUNC_1 &pcfg_pull_default>,
614 <1 21 RK_FUNC_1 &pcfg_pull_default>;
619 sdio_bus1: sdio-bus1 {
620 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
623 sdio_bus4: sdio-bus4 {
624 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
625 <0 12 RK_FUNC_1 &pcfg_pull_default>,
626 <0 13 RK_FUNC_1 &pcfg_pull_default>,
627 <0 14 RK_FUNC_1 &pcfg_pull_default>;
631 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
635 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
641 * We run eMMC at max speed; bump up drive strength.
642 * We also have external pulls, so disable the internal ones.
645 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
649 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
652 emmc_bus8: emmc-bus8 {
653 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
654 <1 25 RK_FUNC_2 &pcfg_pull_default>,
655 <1 26 RK_FUNC_2 &pcfg_pull_default>,
656 <1 27 RK_FUNC_2 &pcfg_pull_default>,
657 <1 28 RK_FUNC_2 &pcfg_pull_default>,
658 <1 29 RK_FUNC_2 &pcfg_pull_default>,
659 <1 30 RK_FUNC_2 &pcfg_pull_default>,
660 <1 31 RK_FUNC_2 &pcfg_pull_default>;
665 emac_xfer: emac-xfer {
666 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
667 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
668 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
669 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
670 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
671 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
672 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
673 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
676 emac_mdio: emac-mdio {
677 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
678 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
683 i2c0_xfer: i2c0-xfer {
684 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
685 <0 1 RK_FUNC_1 &pcfg_pull_none>;
690 i2c1_xfer: i2c1-xfer {
691 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
692 <0 3 RK_FUNC_1 &pcfg_pull_none>;
697 i2c2_xfer: i2c2-xfer {
698 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
699 <2 21 RK_FUNC_1 &pcfg_pull_none>;
705 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
706 <1 1 RK_FUNC_1 &pcfg_pull_default>,
707 <1 2 RK_FUNC_1 &pcfg_pull_default>,
708 <1 3 RK_FUNC_1 &pcfg_pull_default>,
709 <1 4 RK_FUNC_1 &pcfg_pull_default>,
710 <1 5 RK_FUNC_1 &pcfg_pull_default>;
716 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
717 <1 9 RK_FUNC_1 &pcfg_pull_none>,
718 <1 10 RK_FUNC_1 &pcfg_pull_none>,
719 <1 11 RK_FUNC_1 &pcfg_pull_none>;
724 uart0_xfer: uart0-xfer {
725 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
726 <0 17 RK_FUNC_1 &pcfg_pull_none>;
729 uart0_cts: uart0-cts {
730 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
733 uart0_rts: uart0-rts {
734 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
739 uart1_xfer: uart1-xfer {
740 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
741 <2 23 RK_FUNC_1 &pcfg_pull_none>;
743 /* no rts / cts for uart1 */
747 uart2_xfer: uart2-xfer {
748 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
749 <1 19 RK_FUNC_2 &pcfg_pull_none>;
751 /* no rts / cts for uart2 */
756 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
760 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
764 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
768 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
773 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;