2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
67 device_type = "memory";
68 reg = <0x60000000 0x40000000>;
74 enable-method = "rockchip,rk3036-smp";
78 compatible = "arm,cortex-a7";
80 resets = <&cru SRST_CORE0>;
85 clock-latency = <40000>;
86 clocks = <&cru ARMCLK>;
91 compatible = "arm,cortex-a7";
93 resets = <&cru SRST_CORE1>;
98 compatible = "simple-bus";
103 pdma: pdma@20078000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0x20078000 0x4000>;
106 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109 arm,pl330-broken-no-flushp;
110 clocks = <&cru ACLK_DMAC2>;
111 clock-names = "apb_pclk";
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&cpu0>, <&cpu1>;
123 compatible = "arm,armv7-timer";
124 arm,cpu-registers-not-fw-configured;
125 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
129 clock-frequency = <24000000>;
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "xin24m";
139 bus_intmem@10080000 {
140 compatible = "mmio-sram";
141 reg = <0x10080000 0x2000>;
142 #address-cells = <1>;
144 ranges = <0 0x10080000 0x2000>;
147 compatible = "rockchip,rk3066-smp-sram";
152 gic: interrupt-controller@10139000 {
153 compatible = "arm,gic-400";
154 interrupt-controller;
155 #interrupt-cells = <3>;
156 #address-cells = <0>;
158 reg = <0x10139000 0x1000>,
162 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
165 usb_otg: usb@10180000 {
166 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
168 reg = <0x10180000 0x40000>;
169 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru HCLK_OTG0>;
173 g-np-tx-fifo-size = <16>;
174 g-rx-fifo-size = <275>;
175 g-tx-fifo-size = <256 128 128 64 64 32>;
180 usb_host: usb@101c0000 {
181 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
183 reg = <0x101c0000 0x40000>;
184 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&cru HCLK_OTG1>;
191 emac: ethernet@10200000 {
192 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
193 reg = <0x10200000 0x4000>;
194 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
195 #address-cells = <1>;
197 rockchip,grf = <&grf>;
198 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
199 clock-names = "hclk", "macref", "macclk";
201 * Fix the emac parent clock is DPLL instead of APLL.
202 * since that will cause some unstable things if the cpufreq
203 * is working. (e.g: the accurate 50MHz what mac_ref need)
205 assigned-clocks = <&cru SCLK_MACPLL>;
206 assigned-clock-parents = <&cru PLL_DPLL>;
212 sdmmc: dwmmc@10214000 {
213 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
214 reg = <0x10214000 0x4000>;
215 clock-frequency = <37500000>;
216 clock-freq-min-max = <400000 37500000>;
217 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
218 clock-names = "biu", "ciu";
219 fifo-depth = <0x100>;
220 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
224 sdio: dwmmc@10218000 {
225 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
226 reg = <0x10218000 0x4000>;
227 clock-freq-min-max = <400000 37500000>;
228 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
229 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
230 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
231 fifo-depth = <0x100>;
232 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
236 emmc: dwmmc@1021c000 {
237 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
238 reg = <0x1021c000 0x4000>;
239 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
243 clock-frequency = <37500000>;
244 clock-freq-min-max = <400000 37500000>;
245 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
246 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
248 default-sample-phase = <158>;
252 fifo-depth = <0x100>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
262 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
263 reg = <0x10220000 0x4000>;
264 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
265 #address-cells = <1>;
267 clock-names = "i2s_clk", "i2s_hclk";
268 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
269 dmas = <&pdma 0>, <&pdma 1>;
270 dma-names = "tx", "rx";
271 pinctrl-names = "default";
272 pinctrl-0 = <&i2s_bus>;
276 cru: clock-controller@20000000 {
277 compatible = "rockchip,rk3036-cru";
278 reg = <0x20000000 0x1000>;
279 rockchip,grf = <&grf>;
282 assigned-clocks = <&cru PLL_GPLL>;
283 assigned-clock-rates = <594000000>;
286 grf: syscon@20008000 {
287 compatible = "rockchip,rk3036-grf", "syscon";
288 reg = <0x20008000 0x1000>;
291 acodec: acodec-ana@20030000 {
292 compatible = "rk3036-codec";
293 reg = <0x20030000 0x4000>;
294 rockchip,grf = <&grf>;
295 clock-names = "acodec_pclk";
296 clocks = <&cru PCLK_ACODEC>;
300 timer: timer@20044000 {
301 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
302 reg = <0x20044000 0x20>;
303 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&xin24m>, <&cru PCLK_TIMER>;
305 clock-names = "timer", "pclk";
309 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
310 reg = <0x20050000 0x10>;
312 clocks = <&cru PCLK_PWM>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pwm0_pin>;
320 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
321 reg = <0x20050010 0x10>;
323 clocks = <&cru PCLK_PWM>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pwm1_pin>;
331 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
332 reg = <0x20050020 0x10>;
334 clocks = <&cru PCLK_PWM>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pwm2_pin>;
342 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
343 reg = <0x20050030 0x10>;
345 clocks = <&cru PCLK_PWM>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pwm3_pin>;
353 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
354 reg = <0x20056000 0x1000>;
355 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
356 #address-cells = <1>;
359 clocks = <&cru PCLK_I2C1>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c1_xfer>;
366 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
367 reg = <0x2005a000 0x1000>;
368 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
369 #address-cells = <1>;
372 clocks = <&cru PCLK_I2C2>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&i2c2_xfer>;
378 uart0: serial@20060000 {
379 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
380 reg = <0x20060000 0x100>;
381 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
384 clock-frequency = <24000000>;
385 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
386 clock-names = "baudclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
392 uart1: serial@20064000 {
393 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
394 reg = <0x20064000 0x100>;
395 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
398 clock-frequency = <24000000>;
399 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
400 clock-names = "baudclk", "apb_pclk";
401 pinctrl-names = "default";
402 pinctrl-0 = <&uart1_xfer>;
406 uart2: serial@20068000 {
407 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
408 reg = <0x20068000 0x100>;
409 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
412 clock-frequency = <24000000>;
413 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
414 clock-names = "baudclk", "apb_pclk";
415 pinctrl-names = "default";
416 pinctrl-0 = <&uart2_xfer>;
421 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
422 reg = <0x20072000 0x1000>;
423 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
424 #address-cells = <1>;
427 clocks = <&cru PCLK_I2C0>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c0_xfer>;
434 compatible = "rockchip,rockchip-spi";
435 reg = <0x20074000 0x1000>;
436 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
437 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
438 clock-names = "apb-pclk","spi_pclk";
439 dmas = <&pdma 8>, <&pdma 9>;
440 dma-names = "tx", "rx";
441 pinctrl-names = "default";
442 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
443 #address-cells = <1>;
449 compatible = "rockchip,rk3036-pinctrl";
450 rockchip,grf = <&grf>;
451 #address-cells = <1>;
455 gpio0: gpio0@2007c000 {
456 compatible = "rockchip,gpio-bank";
457 reg = <0x2007c000 0x100>;
458 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&cru PCLK_GPIO0>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
468 gpio1: gpio1@20080000 {
469 compatible = "rockchip,gpio-bank";
470 reg = <0x20080000 0x100>;
471 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&cru PCLK_GPIO1>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
481 gpio2: gpio2@20084000 {
482 compatible = "rockchip,gpio-bank";
483 reg = <0x20084000 0x100>;
484 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cru PCLK_GPIO2>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
494 pcfg_pull_default: pcfg_pull_default {
495 bias-pull-pin-default;
498 pcfg_pull_none: pcfg-pull-none {
504 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
510 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
516 rockchip,pins = <0 1 2 &pcfg_pull_none>;
522 rockchip,pins = <0 27 1 &pcfg_pull_none>;
527 sdmmc_clk: sdmmc-clk {
528 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
531 sdmmc_cmd: sdmmc-cmd {
532 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
536 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
539 sdmmc_bus1: sdmmc-bus1 {
540 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
543 sdmmc_bus4: sdmmc-bus4 {
544 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
545 <1 19 RK_FUNC_1 &pcfg_pull_default>,
546 <1 20 RK_FUNC_1 &pcfg_pull_default>,
547 <1 21 RK_FUNC_1 &pcfg_pull_default>;
552 sdio_bus1: sdio-bus1 {
553 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
556 sdio_bus4: sdio-bus4 {
557 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
558 <0 12 RK_FUNC_1 &pcfg_pull_default>,
559 <0 13 RK_FUNC_1 &pcfg_pull_default>,
560 <0 14 RK_FUNC_1 &pcfg_pull_default>;
564 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
568 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
574 * We run eMMC at max speed; bump up drive strength.
575 * We also have external pulls, so disable the internal ones.
578 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
582 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
585 emmc_bus8: emmc-bus8 {
586 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
587 <1 25 RK_FUNC_2 &pcfg_pull_default>,
588 <1 26 RK_FUNC_2 &pcfg_pull_default>,
589 <1 27 RK_FUNC_2 &pcfg_pull_default>,
590 <1 28 RK_FUNC_2 &pcfg_pull_default>,
591 <1 29 RK_FUNC_2 &pcfg_pull_default>,
592 <1 30 RK_FUNC_2 &pcfg_pull_default>,
593 <1 31 RK_FUNC_2 &pcfg_pull_default>;
598 emac_xfer: emac-xfer {
599 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
600 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
601 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
602 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
603 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
604 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
605 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
606 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
609 emac_mdio: emac-mdio {
610 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
611 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
616 i2c0_xfer: i2c0-xfer {
617 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
618 <0 1 RK_FUNC_1 &pcfg_pull_none>;
623 i2c1_xfer: i2c1-xfer {
624 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
625 <0 3 RK_FUNC_1 &pcfg_pull_none>;
630 i2c2_xfer: i2c2-xfer {
631 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
632 <2 21 RK_FUNC_1 &pcfg_pull_none>;
638 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
639 <1 1 RK_FUNC_1 &pcfg_pull_default>,
640 <1 2 RK_FUNC_1 &pcfg_pull_default>,
641 <1 3 RK_FUNC_1 &pcfg_pull_default>,
642 <1 4 RK_FUNC_1 &pcfg_pull_default>,
643 <1 5 RK_FUNC_1 &pcfg_pull_default>;
648 uart0_xfer: uart0-xfer {
649 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
650 <0 17 RK_FUNC_1 &pcfg_pull_none>;
653 uart0_cts: uart0-cts {
654 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
657 uart0_rts: uart0-rts {
658 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
663 uart1_xfer: uart1-xfer {
664 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
665 <2 23 RK_FUNC_1 &pcfg_pull_none>;
667 /* no rts / cts for uart1 */
671 uart2_xfer: uart2-xfer {
672 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
673 <1 19 RK_FUNC_2 &pcfg_pull_none>;
675 /* no rts / cts for uart2 */
680 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
684 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
688 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
692 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
697 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;