2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include "rk3xxx.dtsi"
19 #include "rk3066a-clocks.dtsi"
22 compatible = "rockchip,rk3066a";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
44 compatible = "snps,dw-apb-timer-osc";
45 reg = <0x20038000 0x100>;
46 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&clk_gates1 0>, <&clk_gates7 7>;
48 clock-names = "timer", "pclk";
52 compatible = "snps,dw-apb-timer-osc";
53 reg = <0x2003a000 0x100>;
54 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&clk_gates1 1>, <&clk_gates7 8>;
56 clock-names = "timer", "pclk";
60 compatible = "snps,dw-apb-timer-osc";
61 reg = <0x2000e000 0x100>;
62 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&clk_gates1 2>, <&clk_gates7 9>;
64 clock-names = "timer", "pclk";
68 compatible = "rockchip,rk3066a-pinctrl";
69 reg = <0x20008000 0x150>;
74 gpio0: gpio0@20034000 {
75 compatible = "rockchip,gpio-bank";
76 reg = <0x20034000 0x100>;
77 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&clk_gates8 9>;
84 #interrupt-cells = <2>;
87 gpio1: gpio1@2003c000 {
88 compatible = "rockchip,gpio-bank";
89 reg = <0x2003c000 0x100>;
90 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&clk_gates8 10>;
97 #interrupt-cells = <2>;
100 gpio2: gpio2@2003e000 {
101 compatible = "rockchip,gpio-bank";
102 reg = <0x2003e000 0x100>;
103 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&clk_gates8 11>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
113 gpio3: gpio3@20080000 {
114 compatible = "rockchip,gpio-bank";
115 reg = <0x20080000 0x100>;
116 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&clk_gates8 12>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
126 gpio4: gpio4@20084000 {
127 compatible = "rockchip,gpio-bank";
128 reg = <0x20084000 0x100>;
129 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&clk_gates8 13>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
139 gpio6: gpio6@2000a000 {
140 compatible = "rockchip,gpio-bank";
141 reg = <0x2000a000 0x100>;
142 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&clk_gates8 15>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
152 pcfg_pull_default: pcfg_pull_default {
153 bias-pull-pin-default;
156 pcfg_pull_none: pcfg_pull_none {
161 uart0_xfer: uart0-xfer {
162 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
163 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
166 uart0_cts: uart0-cts {
167 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
170 uart0_rts: uart0-rts {
171 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
176 uart1_xfer: uart1-xfer {
177 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
178 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
181 uart1_cts: uart1-cts {
182 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
185 uart1_rts: uart1-rts {
186 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
191 uart2_xfer: uart2-xfer {
192 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
193 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
195 /* no rts / cts for uart2 */
199 uart3_xfer: uart3-xfer {
200 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
201 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
204 uart3_cts: uart3-cts {
205 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
208 uart3_rts: uart3-rts {
209 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
215 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
219 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
223 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
227 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
230 sd0_bus1: sd0-bus-width1 {
231 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
234 sd0_bus4: sd0-bus-width4 {
235 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
236 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
237 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
238 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
244 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
248 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
252 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
256 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
259 sd1_bus1: sd1-bus-width1 {
260 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
263 sd1_bus4: sd1-bus-width4 {
264 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
265 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
266 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
267 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;