2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/pinctrl/rockchip.h>
46 #include <dt-bindings/clock/rk3188-cru.h>
47 #include "rk3xxx.dtsi"
50 compatible = "rockchip,rk3188";
55 enable-method = "rockchip,rk3066-smp";
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
73 clock-latency = <40000>;
74 clocks = <&cru ARMCLK>;
78 compatible = "arm,cortex-a9";
79 next-level-cache = <&L2>;
84 compatible = "arm,cortex-a9";
85 next-level-cache = <&L2>;
90 compatible = "arm,cortex-a9";
91 next-level-cache = <&L2>;
97 compatible = "mmio-sram";
98 reg = <0x10080000 0x8000>;
101 ranges = <0 0x10080000 0x8000>;
104 compatible = "rockchip,rk3066-smp-sram";
110 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
111 reg = <0x1011a000 0x2000>;
112 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
113 #address-cells = <1>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2s0_bus>;
117 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
118 dma-names = "tx", "rx";
119 clock-names = "i2s_hclk", "i2s_clk";
120 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
121 rockchip,playback-channels = <2>;
122 rockchip,capture-channels = <2>;
126 spdif: sound@1011e000 {
127 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
128 reg = <0x1011e000 0x2000>;
129 #sound-dai-cells = <0>;
130 clock-names = "hclk", "mclk";
131 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
134 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&spdif_tx>;
140 cru: clock-controller@20000000 {
141 compatible = "rockchip,rk3188-cru";
142 reg = <0x20000000 0x1000>;
143 rockchip,grf = <&grf>;
149 efuse: efuse@20010000 {
150 compatible = "rockchip,rockchip-efuse";
151 reg = <0x20010000 0x4000>;
152 #address-cells = <1>;
154 clocks = <&cru PCLK_EFUSE>;
155 clock-names = "pclk_efuse";
157 cpu_leakage: cpu_leakage {
163 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
164 rockchip,grf = <&grf>;
165 #address-cells = <1>;
172 clocks = <&cru SCLK_OTGPHY0>;
173 clock-names = "phyclk";
179 clocks = <&cru SCLK_OTGPHY1>;
180 clock-names = "phyclk";
185 compatible = "rockchip,rk3188-pinctrl";
186 rockchip,grf = <&grf>;
187 rockchip,pmu = <&pmu>;
189 #address-cells = <1>;
193 gpio0: gpio0@2000a000 {
194 compatible = "rockchip,rk3188-gpio-bank0";
195 reg = <0x2000a000 0x100>;
196 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&cru PCLK_GPIO0>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
206 gpio1: gpio1@2003c000 {
207 compatible = "rockchip,gpio-bank";
208 reg = <0x2003c000 0x100>;
209 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&cru PCLK_GPIO1>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
219 gpio2: gpio2@2003e000 {
220 compatible = "rockchip,gpio-bank";
221 reg = <0x2003e000 0x100>;
222 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru PCLK_GPIO2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
232 gpio3: gpio3@20080000 {
233 compatible = "rockchip,gpio-bank";
234 reg = <0x20080000 0x100>;
235 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&cru PCLK_GPIO3>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
245 pcfg_pull_up: pcfg_pull_up {
249 pcfg_pull_down: pcfg_pull_down {
253 pcfg_pull_none: pcfg_pull_none {
259 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
263 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
267 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
271 * The data pins are shared between nandc and emmc and
272 * not accessible through pinctrl. Also they should've
273 * been already set correctly by firmware, as
274 * flash/emmc is the boot-device.
279 emac_xfer: emac-xfer {
280 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
281 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
282 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
283 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
284 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
285 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
286 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
287 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
290 emac_mdio: emac-mdio {
291 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
292 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
297 i2c0_xfer: i2c0-xfer {
298 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
299 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
304 i2c1_xfer: i2c1-xfer {
305 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
306 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
311 i2c2_xfer: i2c2-xfer {
312 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
313 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
318 i2c3_xfer: i2c3-xfer {
319 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
320 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
325 i2c4_xfer: i2c4-xfer {
326 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
327 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
333 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
339 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
345 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
351 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
357 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
360 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
363 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
366 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
369 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
375 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
378 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
381 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
384 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
387 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
392 uart0_xfer: uart0-xfer {
393 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
394 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
397 uart0_cts: uart0-cts {
398 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
401 uart0_rts: uart0-rts {
402 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
407 uart1_xfer: uart1-xfer {
408 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
409 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
412 uart1_cts: uart1-cts {
413 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
416 uart1_rts: uart1-rts {
417 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
422 uart2_xfer: uart2-xfer {
423 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
424 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
426 /* no rts / cts for uart2 */
430 uart3_xfer: uart3-xfer {
431 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
432 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
435 uart3_cts: uart3-cts {
436 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
439 uart3_rts: uart3-rts {
440 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
446 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
450 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
454 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
458 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
462 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
465 sd0_bus1: sd0-bus-width1 {
466 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
469 sd0_bus4: sd0-bus-width4 {
470 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
471 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
472 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
473 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
479 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
483 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
487 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
491 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
494 sd1_bus1: sd1-bus-width1 {
495 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
498 sd1_bus4: sd1-bus-width4 {
499 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
500 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
501 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
502 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
508 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
509 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
510 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
511 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
512 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
513 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
519 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
526 compatible = "rockchip,rk3188-emac";
530 interrupts = <GIC_PPI 11 0xf04>;
534 interrupts = <GIC_PPI 13 0xf04>;
538 compatible = "rockchip,rk3188-i2c";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c0_xfer>;
544 compatible = "rockchip,rk3188-i2c";
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2c1_xfer>;
550 compatible = "rockchip,rk3188-i2c";
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c2_xfer>;
556 compatible = "rockchip,rk3188-i2c";
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2c3_xfer>;
562 compatible = "rockchip,rk3188-i2c";
563 pinctrl-names = "default";
564 pinctrl-0 = <&i2c4_xfer>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pwm0_out>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&pwm1_out>;
578 pinctrl-names = "default";
579 pinctrl-0 = <&pwm2_out>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pwm3_out>;
588 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
589 pinctrl-names = "default";
590 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
594 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
595 pinctrl-names = "default";
596 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&uart0_xfer>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&uart1_xfer>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&uart2_xfer>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&uart3_xfer>;
620 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";