2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3228-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
52 interrupt-parent = <&gic>;
66 compatible = "arm,cortex-a7";
68 resets = <&cru SRST_CORE0>;
69 operating-points-v2 = <&cpu0_opp_table>;
70 #cooling-cells = <2>; /* min followed by max */
71 clock-latency = <40000>;
72 clocks = <&cru ARMCLK>;
77 compatible = "arm,cortex-a7";
79 resets = <&cru SRST_CORE1>;
80 operating-points-v2 = <&cpu0_opp_table>;
85 compatible = "arm,cortex-a7";
87 resets = <&cru SRST_CORE2>;
88 operating-points-v2 = <&cpu0_opp_table>;
93 compatible = "arm,cortex-a7";
95 resets = <&cru SRST_CORE3>;
96 operating-points-v2 = <&cpu0_opp_table>;
100 cpu0_opp_table: opp_table0 {
101 compatible = "operating-points-v2";
105 opp-hz = /bits/ 64 <408000000>;
106 opp-microvolt = <950000>;
107 clock-latency-ns = <40000>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <975000>;
115 opp-hz = /bits/ 64 <816000000>;
116 opp-microvolt = <1000000>;
119 opp-hz = /bits/ 64 <1008000000>;
120 opp-microvolt = <1175000>;
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <1275000>;
129 compatible = "simple-bus";
130 #address-cells = <1>;
134 pdma: pdma@110f0000 {
135 compatible = "arm,pl330", "arm,primecell";
136 reg = <0x110f0000 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&cru ACLK_DMAC>;
141 clock-names = "apb_pclk";
146 compatible = "arm,cortex-a7-pmu";
147 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
155 compatible = "arm,armv7-timer";
156 arm,cpu-registers-not-fw-configured;
157 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
158 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
159 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
160 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
161 clock-frequency = <24000000>;
165 compatible = "fixed-clock";
166 clock-frequency = <24000000>;
167 clock-output-names = "xin24m";
171 i2s1: i2s1@100b0000 {
172 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
173 reg = <0x100b0000 0x4000>;
174 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
175 #address-cells = <1>;
177 clock-names = "i2s_clk", "i2s_hclk";
178 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
179 dmas = <&pdma 14>, <&pdma 15>;
180 dma-names = "tx", "rx";
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2s1_bus>;
186 i2s0: i2s0@100c0000 {
187 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
188 reg = <0x100c0000 0x4000>;
189 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
190 #address-cells = <1>;
192 clock-names = "i2s_clk", "i2s_hclk";
193 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
194 dmas = <&pdma 11>, <&pdma 12>;
195 dma-names = "tx", "rx";
199 i2s2: i2s2@100e0000 {
200 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
201 reg = <0x100e0000 0x4000>;
202 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
203 #address-cells = <1>;
205 clock-names = "i2s_clk", "i2s_hclk";
206 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
207 dmas = <&pdma 0>, <&pdma 1>;
208 dma-names = "tx", "rx";
212 grf: syscon@11000000 {
213 compatible = "syscon", "simple-mfd";
214 reg = <0x11000000 0x1000>;
215 #address-cells = <1>;
218 u2phy0: usb2-phy@760 {
219 compatible = "rockchip,rk3228-usb2phy";
221 clocks = <&cru SCLK_OTGPHY0>;
222 clock-names = "phyclk";
223 clock-output-names = "usb480m_phy0";
227 u2phy0_otg: otg-port {
228 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "otg-bvalid", "otg-id",
237 u2phy0_host: host-port {
238 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-names = "linestate";
245 u2phy1: usb2-phy@800 {
246 compatible = "rockchip,rk3228-usb2phy";
248 clocks = <&cru SCLK_OTGPHY1>;
249 clock-names = "phyclk";
250 clock-output-names = "usb480m_phy1";
254 u2phy1_otg: otg-port {
255 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
256 interrupt-names = "linestate";
261 u2phy1_host: host-port {
262 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "linestate";
270 uart0: serial@11010000 {
271 compatible = "snps,dw-apb-uart";
272 reg = <0x11010000 0x100>;
273 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
274 clock-frequency = <24000000>;
275 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
276 clock-names = "baudclk", "apb_pclk";
277 pinctrl-names = "default";
278 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
284 uart1: serial@11020000 {
285 compatible = "snps,dw-apb-uart";
286 reg = <0x11020000 0x100>;
287 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
288 clock-frequency = <24000000>;
289 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
290 clock-names = "baudclk", "apb_pclk";
291 pinctrl-names = "default";
292 pinctrl-0 = <&uart1_xfer>;
298 uart2: serial@11030000 {
299 compatible = "snps,dw-apb-uart";
300 reg = <0x11030000 0x100>;
301 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
302 clock-frequency = <24000000>;
303 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
304 clock-names = "baudclk", "apb_pclk";
305 pinctrl-names = "default";
306 pinctrl-0 = <&uart2_xfer>;
313 compatible = "rockchip,rk3228-i2c";
314 reg = <0x11050000 0x1000>;
315 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>;
319 clocks = <&cru PCLK_I2C0>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c0_xfer>;
326 compatible = "rockchip,rk3228-i2c";
327 reg = <0x11060000 0x1000>;
328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
332 clocks = <&cru PCLK_I2C1>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c1_xfer>;
339 compatible = "rockchip,rk3228-i2c";
340 reg = <0x11070000 0x1000>;
341 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
345 clocks = <&cru PCLK_I2C2>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c2_xfer>;
352 compatible = "rockchip,rk3228-i2c";
353 reg = <0x11080000 0x1000>;
354 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
358 clocks = <&cru PCLK_I2C3>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&i2c3_xfer>;
364 wdt: watchdog@110a0000 {
365 compatible = "snps,dw-wdt";
366 reg = <0x110a0000 0x100>;
367 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cru PCLK_CPU>;
373 compatible = "rockchip,rk3288-pwm";
374 reg = <0x110b0000 0x10>;
376 clocks = <&cru PCLK_PWM>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&pwm0_pin>;
384 compatible = "rockchip,rk3288-pwm";
385 reg = <0x110b0010 0x10>;
387 clocks = <&cru PCLK_PWM>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pwm1_pin>;
395 compatible = "rockchip,rk3288-pwm";
396 reg = <0x110b0020 0x10>;
398 clocks = <&cru PCLK_PWM>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pwm2_pin>;
406 compatible = "rockchip,rk3288-pwm";
407 reg = <0x110b0030 0x10>;
409 clocks = <&cru PCLK_PWM>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pwm3_pin>;
416 timer: timer@110c0000 {
417 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
418 reg = <0x110c0000 0x20>;
419 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&xin24m>, <&cru PCLK_TIMER>;
421 clock-names = "timer", "pclk";
424 cru: clock-controller@110e0000 {
425 compatible = "rockchip,rk3228-cru";
426 reg = <0x110e0000 0x1000>;
427 rockchip,grf = <&grf>;
431 <&cru PLL_GPLL>, <&cru ARMCLK>,
432 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
433 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
434 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
436 assigned-clock-rates =
437 <594000000>, <816000000>,
438 <500000000>, <150000000>,
439 <150000000>, <75000000>,
440 <150000000>, <150000000>,
445 cpu_thermal: cpu-thermal {
446 polling-delay-passive = <100>; /* milliseconds */
447 polling-delay = <5000>; /* milliseconds */
449 thermal-sensors = <&tsadc 0>;
452 cpu_alert0: cpu_alert0 {
453 temperature = <70000>; /* millicelsius */
454 hysteresis = <2000>; /* millicelsius */
457 cpu_alert1: cpu_alert1 {
458 temperature = <75000>; /* millicelsius */
459 hysteresis = <2000>; /* millicelsius */
463 temperature = <90000>; /* millicelsius */
464 hysteresis = <2000>; /* millicelsius */
471 trip = <&cpu_alert0>;
473 <&cpu0 THERMAL_NO_LIMIT 6>;
476 trip = <&cpu_alert1>;
478 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
484 tsadc: tsadc@11150000 {
485 compatible = "rockchip,rk3228-tsadc";
486 reg = <0x11150000 0x100>;
487 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
489 clock-names = "tsadc", "apb_pclk";
490 assigned-clocks = <&cru SCLK_TSADC>;
491 assigned-clock-rates = <32768>;
492 resets = <&cru SRST_TSADC>;
493 reset-names = "tsadc-apb";
494 pinctrl-names = "init", "default", "sleep";
495 pinctrl-0 = <&otp_gpio>;
496 pinctrl-1 = <&otp_out>;
497 pinctrl-2 = <&otp_gpio>;
498 #thermal-sensor-cells = <0>;
499 rockchip,hw-tshut-temp = <95000>;
503 emmc: dwmmc@30020000 {
504 compatible = "rockchip,rk3288-dw-mshc";
505 reg = <0x30020000 0x4000>;
506 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
507 clock-frequency = <37500000>;
508 max-frequency = <37500000>;
509 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
510 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
511 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
513 default-sample-phase = <158>;
515 fifo-depth = <0x100>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
518 resets = <&cru SRST_EMMC>;
519 reset-names = "reset";
523 usb_otg: usb@30040000 {
524 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
526 reg = <0x30040000 0x40000>;
527 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cru HCLK_OTG>;
531 g-np-tx-fifo-size = <16>;
532 g-rx-fifo-size = <280>;
533 g-tx-fifo-size = <256 128 128 64 32 16>;
535 phys = <&u2phy0_otg>;
536 phy-names = "usb2-phy";
540 usb_host0_ehci: usb@30080000 {
541 compatible = "generic-ehci";
542 reg = <0x30080000 0x20000>;
543 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
545 clock-names = "usbhost", "utmi";
546 phys = <&u2phy0_host>;
551 usb_host0_ohci: usb@300a0000 {
552 compatible = "generic-ohci";
553 reg = <0x300a0000 0x20000>;
554 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
556 clock-names = "usbhost", "utmi";
557 phys = <&u2phy0_host>;
562 usb_host1_ehci: usb@300c0000 {
563 compatible = "generic-ehci";
564 reg = <0x300c0000 0x20000>;
565 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
567 clock-names = "usbhost", "utmi";
568 phys = <&u2phy1_otg>;
573 usb_host1_ohci: usb@300e0000 {
574 compatible = "generic-ohci";
575 reg = <0x300e0000 0x20000>;
576 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
578 clock-names = "usbhost", "utmi";
579 phys = <&u2phy1_otg>;
584 usb_host2_ehci: usb@30100000 {
585 compatible = "generic-ehci";
586 reg = <0x30100000 0x20000>;
587 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
589 phys = <&u2phy1_host>;
591 clock-names = "usbhost", "utmi";
595 usb_host2_ohci: usb@30120000 {
596 compatible = "generic-ohci";
597 reg = <0x30120000 0x20000>;
598 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
600 clock-names = "usbhost", "utmi";
601 phys = <&u2phy1_host>;
606 gmac: ethernet@30200000 {
607 compatible = "rockchip,rk3228-gmac";
608 reg = <0x30200000 0x10000>;
609 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-names = "macirq";
611 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
612 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
613 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
615 clock-names = "stmmaceth", "mac_clk_rx",
616 "mac_clk_tx", "clk_mac_ref",
617 "clk_mac_refout", "aclk_mac",
619 resets = <&cru SRST_GMAC>;
620 reset-names = "stmmaceth";
621 rockchip,grf = <&grf>;
625 gic: interrupt-controller@32010000 {
626 compatible = "arm,gic-400";
627 interrupt-controller;
628 #interrupt-cells = <3>;
629 #address-cells = <0>;
631 reg = <0x32011000 0x1000>,
635 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
639 compatible = "rockchip,rk3228-pinctrl";
640 rockchip,grf = <&grf>;
641 #address-cells = <1>;
645 gpio0: gpio0@11110000 {
646 compatible = "rockchip,gpio-bank";
647 reg = <0x11110000 0x100>;
648 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cru PCLK_GPIO0>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
658 gpio1: gpio1@11120000 {
659 compatible = "rockchip,gpio-bank";
660 reg = <0x11120000 0x100>;
661 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cru PCLK_GPIO1>;
667 interrupt-controller;
668 #interrupt-cells = <2>;
671 gpio2: gpio2@11130000 {
672 compatible = "rockchip,gpio-bank";
673 reg = <0x11130000 0x100>;
674 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cru PCLK_GPIO2>;
680 interrupt-controller;
681 #interrupt-cells = <2>;
684 gpio3: gpio3@11140000 {
685 compatible = "rockchip,gpio-bank";
686 reg = <0x11140000 0x100>;
687 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cru PCLK_GPIO3>;
693 interrupt-controller;
694 #interrupt-cells = <2>;
697 pcfg_pull_up: pcfg-pull-up {
701 pcfg_pull_down: pcfg-pull-down {
705 pcfg_pull_none: pcfg-pull-none {
709 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
710 drive-strength = <12>;
715 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
719 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
722 emmc_bus8: emmc-bus8 {
723 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
724 <1 25 RK_FUNC_2 &pcfg_pull_none>,
725 <1 26 RK_FUNC_2 &pcfg_pull_none>,
726 <1 27 RK_FUNC_2 &pcfg_pull_none>,
727 <1 28 RK_FUNC_2 &pcfg_pull_none>,
728 <1 29 RK_FUNC_2 &pcfg_pull_none>,
729 <1 30 RK_FUNC_2 &pcfg_pull_none>,
730 <1 31 RK_FUNC_2 &pcfg_pull_none>;
735 rgmii_pins: rgmii-pins {
736 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
737 <2 12 RK_FUNC_1 &pcfg_pull_none>,
738 <2 25 RK_FUNC_1 &pcfg_pull_none>,
739 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
740 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
741 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
742 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
743 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
744 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
745 <2 17 RK_FUNC_1 &pcfg_pull_none>,
746 <2 16 RK_FUNC_1 &pcfg_pull_none>,
747 <2 21 RK_FUNC_2 &pcfg_pull_none>,
748 <2 20 RK_FUNC_2 &pcfg_pull_none>,
749 <2 11 RK_FUNC_1 &pcfg_pull_none>,
750 <2 8 RK_FUNC_1 &pcfg_pull_none>;
753 rmii_pins: rmii-pins {
754 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
755 <2 12 RK_FUNC_1 &pcfg_pull_none>,
756 <2 25 RK_FUNC_1 &pcfg_pull_none>,
757 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
758 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
759 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
760 <2 17 RK_FUNC_1 &pcfg_pull_none>,
761 <2 16 RK_FUNC_1 &pcfg_pull_none>,
762 <2 8 RK_FUNC_1 &pcfg_pull_none>,
763 <2 15 RK_FUNC_1 &pcfg_pull_none>;
767 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
768 <2 8 RK_FUNC_2 &pcfg_pull_none>;
773 i2c0_xfer: i2c0-xfer {
774 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
775 <0 1 RK_FUNC_1 &pcfg_pull_none>;
780 i2c1_xfer: i2c1-xfer {
781 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
782 <0 3 RK_FUNC_1 &pcfg_pull_none>;
787 i2c2_xfer: i2c2-xfer {
788 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
789 <2 21 RK_FUNC_1 &pcfg_pull_none>;
794 i2c3_xfer: i2c3-xfer {
795 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
796 <0 7 RK_FUNC_1 &pcfg_pull_none>;
802 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
803 <0 9 RK_FUNC_1 &pcfg_pull_none>,
804 <0 11 RK_FUNC_1 &pcfg_pull_none>,
805 <0 12 RK_FUNC_1 &pcfg_pull_none>,
806 <0 13 RK_FUNC_1 &pcfg_pull_none>,
807 <0 14 RK_FUNC_1 &pcfg_pull_none>,
808 <1 2 RK_FUNC_2 &pcfg_pull_none>,
809 <1 4 RK_FUNC_2 &pcfg_pull_none>,
810 <1 5 RK_FUNC_2 &pcfg_pull_none>;
816 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
822 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
828 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
834 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
840 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
844 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
849 uart0_xfer: uart0-xfer {
850 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
851 <2 27 RK_FUNC_1 &pcfg_pull_none>;
854 uart0_cts: uart0-cts {
855 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
858 uart0_rts: uart0-rts {
859 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
864 uart1_xfer: uart1-xfer {
865 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
866 <1 10 RK_FUNC_1 &pcfg_pull_none>;
869 uart1_cts: uart1-cts {
870 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
873 uart1_rts: uart1-rts {
874 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
879 uart2_xfer: uart2-xfer {
880 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
881 <1 19 RK_FUNC_2 &pcfg_pull_none>;
884 uart21_xfer: uart21-xfer {
885 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
886 <1 9 RK_FUNC_2 &pcfg_pull_none>;
889 uart2_cts: uart2-cts {
890 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
893 uart2_rts: uart2-rts {
894 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;