2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dt-bindings/thermal/thermal.h>
19 #include "skeleton.dtsi"
22 compatible = "rockchip,rk3288";
24 interrupt-parent = <&gic>;
50 enable-method = "rockchip,rk3066-smp";
51 rockchip,pmu = <&pmu>;
55 compatible = "arm,cortex-a12";
57 resets = <&cru SRST_CORE0>;
73 #cooling-cells = <2>; /* min followed by max */
74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
79 compatible = "arm,cortex-a12";
81 resets = <&cru SRST_CORE1>;
85 compatible = "arm,cortex-a12";
87 resets = <&cru SRST_CORE2>;
91 compatible = "arm,cortex-a12";
93 resets = <&cru SRST_CORE3>;
98 compatible = "arm,amba-bus";
103 dmac_peri: dma-controller@ff250000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0xff250000 0x4000>;
106 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
113 dmac_bus_ns: dma-controller@ff600000 {
114 compatible = "arm,pl330", "arm,primecell";
115 reg = <0xff600000 0x4000>;
116 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&cru ACLK_DMAC1>;
120 clock-names = "apb_pclk";
124 dmac_bus_s: dma-controller@ffb20000 {
125 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
143 compatible = "arm,armv7-timer";
144 arm,cpu-registers-not-fw-configured;
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 clock-frequency = <24000000>;
152 timer: timer@ff810000 {
153 compatible = "rockchip,rk3288-timer";
154 reg = <0xff810000 0x20>;
155 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&xin24m>, <&cru PCLK_TIMER>;
157 clock-names = "timer", "pclk";
161 compatible = "rockchip,display-subsystem";
162 ports = <&vopl_out>, <&vopb_out>;
165 sdmmc: dwmmc@ff0c0000 {
166 compatible = "rockchip,rk3288-dw-mshc";
167 clock-freq-min-max = <400000 150000000>;
168 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
169 clock-names = "biu", "ciu";
170 fifo-depth = <0x100>;
171 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
172 reg = <0xff0c0000 0x4000>;
176 sdio0: dwmmc@ff0d0000 {
177 compatible = "rockchip,rk3288-dw-mshc";
178 clock-freq-min-max = <400000 150000000>;
179 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
180 clock-names = "biu", "ciu";
181 fifo-depth = <0x100>;
182 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
183 reg = <0xff0d0000 0x4000>;
187 sdio1: dwmmc@ff0e0000 {
188 compatible = "rockchip,rk3288-dw-mshc";
189 clock-freq-min-max = <400000 150000000>;
190 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
191 clock-names = "biu", "ciu";
192 fifo-depth = <0x100>;
193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
194 reg = <0xff0e0000 0x4000>;
198 emmc: dwmmc@ff0f0000 {
199 compatible = "rockchip,rk3288-dw-mshc";
200 clock-freq-min-max = <400000 150000000>;
201 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
202 clock-names = "biu", "ciu";
203 fifo-depth = <0x100>;
204 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
205 reg = <0xff0f0000 0x4000>;
209 saradc: saradc@ff100000 {
210 compatible = "rockchip,saradc";
211 reg = <0xff100000 0x100>;
212 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
213 #io-channel-cells = <1>;
214 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
215 clock-names = "saradc", "apb_pclk";
220 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
221 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
222 clock-names = "spiclk", "apb_pclk";
223 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
224 dma-names = "tx", "rx";
225 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
228 reg = <0xff110000 0x1000>;
229 #address-cells = <1>;
235 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
236 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
237 clock-names = "spiclk", "apb_pclk";
238 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
239 dma-names = "tx", "rx";
240 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
243 reg = <0xff120000 0x1000>;
244 #address-cells = <1>;
250 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
251 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
252 clock-names = "spiclk", "apb_pclk";
253 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
254 dma-names = "tx", "rx";
255 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
258 reg = <0xff130000 0x1000>;
259 #address-cells = <1>;
265 compatible = "rockchip,rk3288-i2c";
266 reg = <0xff140000 0x1000>;
267 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
271 clocks = <&cru PCLK_I2C1>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c1_xfer>;
278 compatible = "rockchip,rk3288-i2c";
279 reg = <0xff150000 0x1000>;
280 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
284 clocks = <&cru PCLK_I2C3>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c3_xfer>;
291 compatible = "rockchip,rk3288-i2c";
292 reg = <0xff160000 0x1000>;
293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
297 clocks = <&cru PCLK_I2C4>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&i2c4_xfer>;
304 compatible = "rockchip,rk3288-i2c";
305 reg = <0xff170000 0x1000>;
306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
307 #address-cells = <1>;
310 clocks = <&cru PCLK_I2C5>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&i2c5_xfer>;
316 uart0: serial@ff180000 {
317 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
318 reg = <0xff180000 0x100>;
319 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
323 clock-names = "baudclk", "apb_pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart0_xfer>;
329 uart1: serial@ff190000 {
330 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
331 reg = <0xff190000 0x100>;
332 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
336 clock-names = "baudclk", "apb_pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_xfer>;
342 uart2: serial@ff690000 {
343 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
344 reg = <0xff690000 0x100>;
345 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clock-names = "baudclk", "apb_pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart2_xfer>;
355 uart3: serial@ff1b0000 {
356 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
357 reg = <0xff1b0000 0x100>;
358 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
362 clock-names = "baudclk", "apb_pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart3_xfer>;
368 uart4: serial@ff1c0000 {
369 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
370 reg = <0xff1c0000 0x100>;
371 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
375 clock-names = "baudclk", "apb_pclk";
376 pinctrl-names = "default";
377 pinctrl-0 = <&uart4_xfer>;
382 #include "rk3288-thermal.dtsi"
385 tsadc: tsadc@ff280000 {
386 compatible = "rockchip,rk3288-tsadc";
387 reg = <0xff280000 0x100>;
388 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
390 clock-names = "tsadc", "apb_pclk";
391 resets = <&cru SRST_TSADC>;
392 reset-names = "tsadc-apb";
393 pinctrl-names = "default";
394 pinctrl-0 = <&otp_out>;
395 #thermal-sensor-cells = <1>;
396 rockchip,hw-tshut-temp = <95000>;
400 gmac: ethernet@ff290000 {
401 compatible = "rockchip,rk3288-gmac";
402 reg = <0xff290000 0x10000>;
403 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-names = "macirq";
405 rockchip,grf = <&grf>;
406 clocks = <&cru SCLK_MAC>,
407 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
408 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
409 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
410 clock-names = "stmmaceth",
411 "mac_clk_rx", "mac_clk_tx",
412 "clk_mac_ref", "clk_mac_refout",
413 "aclk_mac", "pclk_mac";
416 usb_host0_ehci: usb@ff500000 {
417 compatible = "generic-ehci";
418 reg = <0xff500000 0x100>;
419 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cru HCLK_USBHOST0>;
421 clock-names = "usbhost";
425 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
427 usb_host1: usb@ff540000 {
428 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
430 reg = <0xff540000 0x40000>;
431 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cru HCLK_USBHOST1>;
437 usb_otg: usb@ff580000 {
438 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
440 reg = <0xff580000 0x40000>;
441 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru HCLK_OTG0>;
447 usb_hsic: usb@ff5c0000 {
448 compatible = "generic-ehci";
449 reg = <0xff5c0000 0x100>;
450 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru HCLK_HSIC>;
452 clock-names = "usbhost";
457 compatible = "rockchip,rk3288-i2c";
458 reg = <0xff650000 0x1000>;
459 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
463 clocks = <&cru PCLK_I2C0>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c0_xfer>;
470 compatible = "rockchip,rk3288-i2c";
471 reg = <0xff660000 0x1000>;
472 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
476 clocks = <&cru PCLK_I2C2>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c2_xfer>;
483 compatible = "rockchip,rk3288-pwm";
484 reg = <0xff680000 0x10>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pwm0_pin>;
488 clocks = <&cru PCLK_PWM>;
494 compatible = "rockchip,rk3288-pwm";
495 reg = <0xff680010 0x10>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pwm1_pin>;
499 clocks = <&cru PCLK_PWM>;
505 compatible = "rockchip,rk3288-pwm";
506 reg = <0xff680020 0x10>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&pwm2_pin>;
510 clocks = <&cru PCLK_PWM>;
516 compatible = "rockchip,rk3288-pwm";
517 reg = <0xff680030 0x10>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&pwm3_pin>;
521 clocks = <&cru PCLK_PWM>;
526 bus_intmem@ff700000 {
527 compatible = "mmio-sram";
528 reg = <0xff700000 0x18000>;
529 #address-cells = <1>;
531 ranges = <0 0xff700000 0x18000>;
533 compatible = "rockchip,rk3066-smp-sram";
539 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
540 reg = <0xff720000 0x1000>;
543 pmu: power-management@ff730000 {
544 compatible = "rockchip,rk3288-pmu", "syscon";
545 reg = <0xff730000 0x100>;
548 sgrf: syscon@ff740000 {
549 compatible = "rockchip,rk3288-sgrf", "syscon";
550 reg = <0xff740000 0x1000>;
553 cru: clock-controller@ff760000 {
554 compatible = "rockchip,rk3288-cru";
555 reg = <0xff760000 0x1000>;
556 rockchip,grf = <&grf>;
559 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
560 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
561 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
562 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
564 assigned-clock-rates = <594000000>, <400000000>,
565 <500000000>, <300000000>,
566 <150000000>, <75000000>,
567 <300000000>, <150000000>,
571 grf: syscon@ff770000 {
572 compatible = "rockchip,rk3288-grf", "syscon";
573 reg = <0xff770000 0x1000>;
576 wdt: watchdog@ff800000 {
577 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
578 reg = <0xff800000 0x100>;
579 clocks = <&cru PCLK_WDT>;
580 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
585 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
586 reg = <0xff890000 0x10000>;
587 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
588 #address-cells = <1>;
590 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
591 dma-names = "tx", "rx";
592 clock-names = "i2s_hclk", "i2s_clk";
593 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2s0_bus>;
600 compatible = "rockchip,rk3288-vop";
601 reg = <0xff930000 0x19c>;
602 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
604 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
605 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
606 reset-names = "axi", "ahb", "dclk";
607 iommus = <&vopb_mmu>;
611 #address-cells = <1>;
614 vopb_out_hdmi: endpoint@0 {
616 remote-endpoint = <&hdmi_in_vopb>;
621 vopb_mmu: iommu@ff930300 {
622 compatible = "rockchip,iommu";
623 reg = <0xff930300 0x100>;
624 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "vopb_mmu";
631 compatible = "rockchip,rk3288-vop";
632 reg = <0xff940000 0x19c>;
633 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
635 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
636 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
637 reset-names = "axi", "ahb", "dclk";
638 iommus = <&vopl_mmu>;
642 #address-cells = <1>;
645 vopl_out_hdmi: endpoint@0 {
647 remote-endpoint = <&hdmi_in_vopl>;
652 vopl_mmu: iommu@ff940300 {
653 compatible = "rockchip,iommu";
654 reg = <0xff940300 0x100>;
655 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
656 interrupt-names = "vopl_mmu";
661 hdmi: hdmi@ff980000 {
662 compatible = "rockchip,rk3288-dw-hdmi";
663 reg = <0xff980000 0x20000>;
665 rockchip,grf = <&grf>;
666 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
668 clock-names = "iahb", "isfr";
673 #address-cells = <1>;
675 hdmi_in_vopb: endpoint@0 {
677 remote-endpoint = <&vopb_out_hdmi>;
679 hdmi_in_vopl: endpoint@1 {
681 remote-endpoint = <&vopl_out_hdmi>;
687 gic: interrupt-controller@ffc01000 {
688 compatible = "arm,gic-400";
689 interrupt-controller;
690 #interrupt-cells = <3>;
691 #address-cells = <0>;
693 reg = <0xffc01000 0x1000>,
697 interrupts = <GIC_PPI 9 0xf04>;
701 compatible = "rockchip,rk3288-pinctrl";
702 rockchip,grf = <&grf>;
703 rockchip,pmu = <&pmu>;
704 #address-cells = <1>;
708 gpio0: gpio0@ff750000 {
709 compatible = "rockchip,gpio-bank";
710 reg = <0xff750000 0x100>;
711 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&cru PCLK_GPIO0>;
717 interrupt-controller;
718 #interrupt-cells = <2>;
721 gpio1: gpio1@ff780000 {
722 compatible = "rockchip,gpio-bank";
723 reg = <0xff780000 0x100>;
724 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cru PCLK_GPIO1>;
730 interrupt-controller;
731 #interrupt-cells = <2>;
734 gpio2: gpio2@ff790000 {
735 compatible = "rockchip,gpio-bank";
736 reg = <0xff790000 0x100>;
737 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&cru PCLK_GPIO2>;
743 interrupt-controller;
744 #interrupt-cells = <2>;
747 gpio3: gpio3@ff7a0000 {
748 compatible = "rockchip,gpio-bank";
749 reg = <0xff7a0000 0x100>;
750 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&cru PCLK_GPIO3>;
756 interrupt-controller;
757 #interrupt-cells = <2>;
760 gpio4: gpio4@ff7b0000 {
761 compatible = "rockchip,gpio-bank";
762 reg = <0xff7b0000 0x100>;
763 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&cru PCLK_GPIO4>;
769 interrupt-controller;
770 #interrupt-cells = <2>;
773 gpio5: gpio5@ff7c0000 {
774 compatible = "rockchip,gpio-bank";
775 reg = <0xff7c0000 0x100>;
776 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&cru PCLK_GPIO5>;
782 interrupt-controller;
783 #interrupt-cells = <2>;
786 gpio6: gpio6@ff7d0000 {
787 compatible = "rockchip,gpio-bank";
788 reg = <0xff7d0000 0x100>;
789 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru PCLK_GPIO6>;
795 interrupt-controller;
796 #interrupt-cells = <2>;
799 gpio7: gpio7@ff7e0000 {
800 compatible = "rockchip,gpio-bank";
801 reg = <0xff7e0000 0x100>;
802 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&cru PCLK_GPIO7>;
808 interrupt-controller;
809 #interrupt-cells = <2>;
812 gpio8: gpio8@ff7f0000 {
813 compatible = "rockchip,gpio-bank";
814 reg = <0xff7f0000 0x100>;
815 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&cru PCLK_GPIO8>;
821 interrupt-controller;
822 #interrupt-cells = <2>;
825 pcfg_pull_up: pcfg-pull-up {
829 pcfg_pull_down: pcfg-pull-down {
833 pcfg_pull_none: pcfg-pull-none {
837 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
839 drive-strength = <12>;
843 global_pwroff: global-pwroff {
844 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
847 ddrio_pwroff: ddrio-pwroff {
848 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
851 ddr0_retention: ddr0-retention {
852 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
855 ddr1_retention: ddr1-retention {
856 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
861 i2c0_xfer: i2c0-xfer {
862 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
863 <0 16 RK_FUNC_1 &pcfg_pull_none>;
868 i2c1_xfer: i2c1-xfer {
869 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
870 <8 5 RK_FUNC_1 &pcfg_pull_none>;
875 i2c2_xfer: i2c2-xfer {
876 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
877 <6 10 RK_FUNC_1 &pcfg_pull_none>;
882 i2c3_xfer: i2c3-xfer {
883 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
884 <2 17 RK_FUNC_1 &pcfg_pull_none>;
889 i2c4_xfer: i2c4-xfer {
890 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
891 <7 18 RK_FUNC_1 &pcfg_pull_none>;
896 i2c5_xfer: i2c5-xfer {
897 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
898 <7 20 RK_FUNC_1 &pcfg_pull_none>;
904 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
905 <6 1 RK_FUNC_1 &pcfg_pull_none>,
906 <6 2 RK_FUNC_1 &pcfg_pull_none>,
907 <6 3 RK_FUNC_1 &pcfg_pull_none>,
908 <6 4 RK_FUNC_1 &pcfg_pull_none>,
909 <6 8 RK_FUNC_1 &pcfg_pull_none>;
914 sdmmc_clk: sdmmc-clk {
915 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
918 sdmmc_cmd: sdmmc-cmd {
919 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
923 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
926 sdmmc_bus1: sdmmc-bus1 {
927 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
930 sdmmc_bus4: sdmmc-bus4 {
931 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
932 <6 17 RK_FUNC_1 &pcfg_pull_up>,
933 <6 18 RK_FUNC_1 &pcfg_pull_up>,
934 <6 19 RK_FUNC_1 &pcfg_pull_up>;
939 sdio0_bus1: sdio0-bus1 {
940 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
943 sdio0_bus4: sdio0-bus4 {
944 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
945 <4 21 RK_FUNC_1 &pcfg_pull_up>,
946 <4 22 RK_FUNC_1 &pcfg_pull_up>,
947 <4 23 RK_FUNC_1 &pcfg_pull_up>;
950 sdio0_cmd: sdio0-cmd {
951 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
954 sdio0_clk: sdio0-clk {
955 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
959 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
963 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
966 sdio0_pwr: sdio0-pwr {
967 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
970 sdio0_bkpwr: sdio0-bkpwr {
971 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
974 sdio0_int: sdio0-int {
975 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
980 sdio1_bus1: sdio1-bus1 {
981 rockchip,pins = <3 24 4 &pcfg_pull_up>;
984 sdio1_bus4: sdio1-bus4 {
985 rockchip,pins = <3 24 4 &pcfg_pull_up>,
986 <3 25 4 &pcfg_pull_up>,
987 <3 26 4 &pcfg_pull_up>,
988 <3 27 4 &pcfg_pull_up>;
992 rockchip,pins = <3 28 4 &pcfg_pull_up>;
996 rockchip,pins = <3 29 4 &pcfg_pull_up>;
999 sdio1_bkpwr: sdio1-bkpwr {
1000 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1003 sdio1_int: sdio1-int {
1004 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1007 sdio1_cmd: sdio1-cmd {
1008 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1011 sdio1_clk: sdio1-clk {
1012 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1015 sdio1_pwr: sdio1-pwr {
1016 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1021 emmc_clk: emmc-clk {
1022 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1025 emmc_cmd: emmc-cmd {
1026 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1029 emmc_pwr: emmc-pwr {
1030 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1033 emmc_bus1: emmc-bus1 {
1034 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1037 emmc_bus4: emmc-bus4 {
1038 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1039 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1040 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1041 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1044 emmc_bus8: emmc-bus8 {
1045 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1046 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1047 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1048 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1049 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1050 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1051 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1052 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1057 spi0_clk: spi0-clk {
1058 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1060 spi0_cs0: spi0-cs0 {
1061 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1064 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1067 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1069 spi0_cs1: spi0-cs1 {
1070 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1074 spi1_clk: spi1-clk {
1075 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1077 spi1_cs0: spi1-cs0 {
1078 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1081 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1084 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1089 spi2_cs1: spi2-cs1 {
1090 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1092 spi2_clk: spi2-clk {
1093 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1095 spi2_cs0: spi2-cs0 {
1096 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1099 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1102 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1107 uart0_xfer: uart0-xfer {
1108 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1109 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1112 uart0_cts: uart0-cts {
1113 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1116 uart0_rts: uart0-rts {
1117 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1122 uart1_xfer: uart1-xfer {
1123 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1124 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1127 uart1_cts: uart1-cts {
1128 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1131 uart1_rts: uart1-rts {
1132 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1137 uart2_xfer: uart2-xfer {
1138 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1139 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1141 /* no rts / cts for uart2 */
1145 uart3_xfer: uart3-xfer {
1146 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1147 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1150 uart3_cts: uart3-cts {
1151 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1154 uart3_rts: uart3-rts {
1155 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1160 uart4_xfer: uart4-xfer {
1161 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1162 <5 13 3 &pcfg_pull_none>;
1165 uart4_cts: uart4-cts {
1166 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1169 uart4_rts: uart4-rts {
1170 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1176 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1181 pwm0_pin: pwm0-pin {
1182 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1187 pwm1_pin: pwm1-pin {
1188 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1193 pwm2_pin: pwm2-pin {
1194 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1199 pwm3_pin: pwm3-pin {
1200 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1205 rgmii_pins: rgmii-pins {
1206 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1207 <3 31 3 &pcfg_pull_none>,
1208 <3 26 3 &pcfg_pull_none>,
1209 <3 27 3 &pcfg_pull_none>,
1210 <3 28 3 &pcfg_pull_none_12ma>,
1211 <3 29 3 &pcfg_pull_none_12ma>,
1212 <3 24 3 &pcfg_pull_none_12ma>,
1213 <3 25 3 &pcfg_pull_none_12ma>,
1214 <4 0 3 &pcfg_pull_none>,
1215 <4 5 3 &pcfg_pull_none>,
1216 <4 6 3 &pcfg_pull_none>,
1217 <4 9 3 &pcfg_pull_none_12ma>,
1218 <4 4 3 &pcfg_pull_none_12ma>,
1219 <4 1 3 &pcfg_pull_none>,
1220 <4 3 3 &pcfg_pull_none>;
1223 rmii_pins: rmii-pins {
1224 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1225 <3 31 3 &pcfg_pull_none>,
1226 <3 28 3 &pcfg_pull_none>,
1227 <3 29 3 &pcfg_pull_none>,
1228 <4 0 3 &pcfg_pull_none>,
1229 <4 5 3 &pcfg_pull_none>,
1230 <4 4 3 &pcfg_pull_none>,
1231 <4 1 3 &pcfg_pull_none>,
1232 <4 2 3 &pcfg_pull_none>,
1233 <4 3 3 &pcfg_pull_none>;