2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include "skeleton.dtsi"
50 compatible = "rockchip,rk3288";
52 interrupt-parent = <&gic>;
76 compatible = "arm,cortex-a12-pmu";
77 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
81 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
87 enable-method = "rockchip,rk3066-smp";
88 rockchip,pmu = <&pmu>;
92 compatible = "arm,cortex-a12";
94 resets = <&cru SRST_CORE0>;
110 #cooling-cells = <2>; /* min followed by max */
111 clock-latency = <40000>;
112 clocks = <&cru ARMCLK>;
116 compatible = "arm,cortex-a12";
118 resets = <&cru SRST_CORE1>;
122 compatible = "arm,cortex-a12";
124 resets = <&cru SRST_CORE2>;
128 compatible = "arm,cortex-a12";
130 resets = <&cru SRST_CORE3>;
135 compatible = "arm,amba-bus";
136 #address-cells = <1>;
140 dmac_peri: dma-controller@ff250000 {
141 compatible = "arm,pl330", "arm,primecell";
142 reg = <0xff250000 0x4000>;
143 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cru ACLK_DMAC2>;
147 clock-names = "apb_pclk";
150 dmac_bus_ns: dma-controller@ff600000 {
151 compatible = "arm,pl330", "arm,primecell";
152 reg = <0xff600000 0x4000>;
153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cru ACLK_DMAC1>;
157 clock-names = "apb_pclk";
161 dmac_bus_s: dma-controller@ffb20000 {
162 compatible = "arm,pl330", "arm,primecell";
163 reg = <0xffb20000 0x4000>;
164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&cru ACLK_DMAC1>;
168 clock-names = "apb_pclk";
173 compatible = "fixed-clock";
174 clock-frequency = <24000000>;
175 clock-output-names = "xin24m";
180 compatible = "arm,armv7-timer";
181 arm,cpu-registers-not-fw-configured;
182 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
183 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
184 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
185 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
186 clock-frequency = <24000000>;
189 timer: timer@ff810000 {
190 compatible = "rockchip,rk3288-timer";
191 reg = <0xff810000 0x20>;
192 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&xin24m>, <&cru PCLK_TIMER>;
194 clock-names = "timer", "pclk";
198 compatible = "rockchip,display-subsystem";
199 ports = <&vopl_out>, <&vopb_out>;
202 sdmmc: dwmmc@ff0c0000 {
203 compatible = "rockchip,rk3288-dw-mshc";
204 clock-freq-min-max = <400000 150000000>;
205 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
206 clock-names = "biu", "ciu";
207 fifo-depth = <0x100>;
208 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
209 reg = <0xff0c0000 0x4000>;
213 sdio0: dwmmc@ff0d0000 {
214 compatible = "rockchip,rk3288-dw-mshc";
215 clock-freq-min-max = <400000 150000000>;
216 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
217 clock-names = "biu", "ciu";
218 fifo-depth = <0x100>;
219 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
220 reg = <0xff0d0000 0x4000>;
224 sdio1: dwmmc@ff0e0000 {
225 compatible = "rockchip,rk3288-dw-mshc";
226 clock-freq-min-max = <400000 150000000>;
227 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
228 clock-names = "biu", "ciu";
229 fifo-depth = <0x100>;
230 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
231 reg = <0xff0e0000 0x4000>;
235 emmc: dwmmc@ff0f0000 {
236 compatible = "rockchip,rk3288-dw-mshc";
237 clock-freq-min-max = <400000 150000000>;
238 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
239 clock-names = "biu", "ciu";
240 fifo-depth = <0x100>;
241 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
242 reg = <0xff0f0000 0x4000>;
246 saradc: saradc@ff100000 {
247 compatible = "rockchip,saradc";
248 reg = <0xff100000 0x100>;
249 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
250 #io-channel-cells = <1>;
251 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
252 clock-names = "saradc", "apb_pclk";
257 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
258 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
259 clock-names = "spiclk", "apb_pclk";
260 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
261 dma-names = "tx", "rx";
262 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
265 reg = <0xff110000 0x1000>;
266 #address-cells = <1>;
272 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
273 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
274 clock-names = "spiclk", "apb_pclk";
275 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
276 dma-names = "tx", "rx";
277 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
280 reg = <0xff120000 0x1000>;
281 #address-cells = <1>;
287 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
288 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
289 clock-names = "spiclk", "apb_pclk";
290 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
291 dma-names = "tx", "rx";
292 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
295 reg = <0xff130000 0x1000>;
296 #address-cells = <1>;
302 compatible = "rockchip,rk3288-i2c";
303 reg = <0xff140000 0x1000>;
304 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
308 clocks = <&cru PCLK_I2C1>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c1_xfer>;
315 compatible = "rockchip,rk3288-i2c";
316 reg = <0xff150000 0x1000>;
317 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
321 clocks = <&cru PCLK_I2C3>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c3_xfer>;
328 compatible = "rockchip,rk3288-i2c";
329 reg = <0xff160000 0x1000>;
330 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
334 clocks = <&cru PCLK_I2C4>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c4_xfer>;
341 compatible = "rockchip,rk3288-i2c";
342 reg = <0xff170000 0x1000>;
343 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
347 clocks = <&cru PCLK_I2C5>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c5_xfer>;
353 uart0: serial@ff180000 {
354 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
355 reg = <0xff180000 0x100>;
356 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
360 clock-names = "baudclk", "apb_pclk";
361 pinctrl-names = "default";
362 pinctrl-0 = <&uart0_xfer>;
366 uart1: serial@ff190000 {
367 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
368 reg = <0xff190000 0x100>;
369 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
373 clock-names = "baudclk", "apb_pclk";
374 pinctrl-names = "default";
375 pinctrl-0 = <&uart1_xfer>;
379 uart2: serial@ff690000 {
380 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
381 reg = <0xff690000 0x100>;
382 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
386 clock-names = "baudclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart2_xfer>;
392 uart3: serial@ff1b0000 {
393 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
394 reg = <0xff1b0000 0x100>;
395 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
399 clock-names = "baudclk", "apb_pclk";
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart3_xfer>;
405 uart4: serial@ff1c0000 {
406 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
407 reg = <0xff1c0000 0x100>;
408 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
412 clock-names = "baudclk", "apb_pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&uart4_xfer>;
419 #include "rk3288-thermal.dtsi"
422 tsadc: tsadc@ff280000 {
423 compatible = "rockchip,rk3288-tsadc";
424 reg = <0xff280000 0x100>;
425 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
427 clock-names = "tsadc", "apb_pclk";
428 resets = <&cru SRST_TSADC>;
429 reset-names = "tsadc-apb";
430 pinctrl-names = "default";
431 pinctrl-0 = <&otp_out>;
432 #thermal-sensor-cells = <1>;
433 rockchip,hw-tshut-temp = <95000>;
437 gmac: ethernet@ff290000 {
438 compatible = "rockchip,rk3288-gmac";
439 reg = <0xff290000 0x10000>;
440 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-names = "macirq";
442 rockchip,grf = <&grf>;
443 clocks = <&cru SCLK_MAC>,
444 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
445 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
446 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
447 clock-names = "stmmaceth",
448 "mac_clk_rx", "mac_clk_tx",
449 "clk_mac_ref", "clk_mac_refout",
450 "aclk_mac", "pclk_mac";
451 resets = <&cru SRST_MAC>;
452 reset-names = "stmmaceth";
456 usb_host0_ehci: usb@ff500000 {
457 compatible = "generic-ehci";
458 reg = <0xff500000 0x100>;
459 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cru HCLK_USBHOST0>;
461 clock-names = "usbhost";
467 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
469 usb_host1: usb@ff540000 {
470 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
472 reg = <0xff540000 0x40000>;
473 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&cru HCLK_USBHOST1>;
478 phy-names = "usb2-phy";
482 usb_otg: usb@ff580000 {
483 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
485 reg = <0xff580000 0x40000>;
486 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru HCLK_OTG0>;
490 g-np-tx-fifo-size = <16>;
491 g-rx-fifo-size = <275>;
492 g-tx-fifo-size = <256 128 128 64 64 32>;
495 phy-names = "usb2-phy";
499 usb_hsic: usb@ff5c0000 {
500 compatible = "generic-ehci";
501 reg = <0xff5c0000 0x100>;
502 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru HCLK_HSIC>;
504 clock-names = "usbhost";
509 compatible = "rockchip,rk3288-i2c";
510 reg = <0xff650000 0x1000>;
511 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
515 clocks = <&cru PCLK_I2C0>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c0_xfer>;
522 compatible = "rockchip,rk3288-i2c";
523 reg = <0xff660000 0x1000>;
524 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
525 #address-cells = <1>;
528 clocks = <&cru PCLK_I2C2>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2c2_xfer>;
535 compatible = "rockchip,rk3288-pwm";
536 reg = <0xff680000 0x10>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pwm0_pin>;
540 clocks = <&cru PCLK_PWM>;
546 compatible = "rockchip,rk3288-pwm";
547 reg = <0xff680010 0x10>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&pwm1_pin>;
551 clocks = <&cru PCLK_PWM>;
557 compatible = "rockchip,rk3288-pwm";
558 reg = <0xff680020 0x10>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pwm2_pin>;
562 clocks = <&cru PCLK_PWM>;
568 compatible = "rockchip,rk3288-pwm";
569 reg = <0xff680030 0x10>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&pwm3_pin>;
573 clocks = <&cru PCLK_PWM>;
578 bus_intmem@ff700000 {
579 compatible = "mmio-sram";
580 reg = <0xff700000 0x18000>;
581 #address-cells = <1>;
583 ranges = <0 0xff700000 0x18000>;
585 compatible = "rockchip,rk3066-smp-sram";
591 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
592 reg = <0xff720000 0x1000>;
595 pmu: power-management@ff730000 {
596 compatible = "rockchip,rk3288-pmu", "syscon";
597 reg = <0xff730000 0x100>;
600 sgrf: syscon@ff740000 {
601 compatible = "rockchip,rk3288-sgrf", "syscon";
602 reg = <0xff740000 0x1000>;
605 cru: clock-controller@ff760000 {
606 compatible = "rockchip,rk3288-cru";
607 reg = <0xff760000 0x1000>;
608 rockchip,grf = <&grf>;
611 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
612 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
613 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
614 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
616 assigned-clock-rates = <594000000>, <400000000>,
617 <500000000>, <300000000>,
618 <150000000>, <75000000>,
619 <300000000>, <150000000>,
623 grf: syscon@ff770000 {
624 compatible = "rockchip,rk3288-grf", "syscon";
625 reg = <0xff770000 0x1000>;
628 wdt: watchdog@ff800000 {
629 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
630 reg = <0xff800000 0x100>;
631 clocks = <&cru PCLK_WDT>;
632 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
637 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
638 reg = <0xff890000 0x10000>;
639 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
640 #address-cells = <1>;
642 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
643 dma-names = "tx", "rx";
644 clock-names = "i2s_hclk", "i2s_clk";
645 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&i2s0_bus>;
652 compatible = "rockchip,rk3288-vop";
653 reg = <0xff930000 0x19c>;
654 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
656 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
657 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
658 reset-names = "axi", "ahb", "dclk";
659 iommus = <&vopb_mmu>;
663 #address-cells = <1>;
666 vopb_out_hdmi: endpoint@0 {
668 remote-endpoint = <&hdmi_in_vopb>;
673 vopb_mmu: iommu@ff930300 {
674 compatible = "rockchip,iommu";
675 reg = <0xff930300 0x100>;
676 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
677 interrupt-names = "vopb_mmu";
683 compatible = "rockchip,rk3288-vop";
684 reg = <0xff940000 0x19c>;
685 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
687 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
688 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
689 reset-names = "axi", "ahb", "dclk";
690 iommus = <&vopl_mmu>;
694 #address-cells = <1>;
697 vopl_out_hdmi: endpoint@0 {
699 remote-endpoint = <&hdmi_in_vopl>;
704 vopl_mmu: iommu@ff940300 {
705 compatible = "rockchip,iommu";
706 reg = <0xff940300 0x100>;
707 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
708 interrupt-names = "vopl_mmu";
713 hdmi: hdmi@ff980000 {
714 compatible = "rockchip,rk3288-dw-hdmi";
715 reg = <0xff980000 0x20000>;
717 rockchip,grf = <&grf>;
718 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
720 clock-names = "iahb", "isfr";
725 #address-cells = <1>;
727 hdmi_in_vopb: endpoint@0 {
729 remote-endpoint = <&vopb_out_hdmi>;
731 hdmi_in_vopl: endpoint@1 {
733 remote-endpoint = <&vopl_out_hdmi>;
739 gic: interrupt-controller@ffc01000 {
740 compatible = "arm,gic-400";
741 interrupt-controller;
742 #interrupt-cells = <3>;
743 #address-cells = <0>;
745 reg = <0xffc01000 0x1000>,
749 interrupts = <GIC_PPI 9 0xf04>;
753 compatible = "rockchip,rk3288-usb-phy";
754 rockchip,grf = <&grf>;
755 #address-cells = <1>;
762 clocks = <&cru SCLK_OTGPHY0>;
763 clock-names = "phyclk";
769 clocks = <&cru SCLK_OTGPHY1>;
770 clock-names = "phyclk";
776 clocks = <&cru SCLK_OTGPHY2>;
777 clock-names = "phyclk";
782 compatible = "rockchip,rk3288-pinctrl";
783 rockchip,grf = <&grf>;
784 rockchip,pmu = <&pmu>;
785 #address-cells = <1>;
789 gpio0: gpio0@ff750000 {
790 compatible = "rockchip,gpio-bank";
791 reg = <0xff750000 0x100>;
792 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&cru PCLK_GPIO0>;
798 interrupt-controller;
799 #interrupt-cells = <2>;
802 gpio1: gpio1@ff780000 {
803 compatible = "rockchip,gpio-bank";
804 reg = <0xff780000 0x100>;
805 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&cru PCLK_GPIO1>;
811 interrupt-controller;
812 #interrupt-cells = <2>;
815 gpio2: gpio2@ff790000 {
816 compatible = "rockchip,gpio-bank";
817 reg = <0xff790000 0x100>;
818 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&cru PCLK_GPIO2>;
824 interrupt-controller;
825 #interrupt-cells = <2>;
828 gpio3: gpio3@ff7a0000 {
829 compatible = "rockchip,gpio-bank";
830 reg = <0xff7a0000 0x100>;
831 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&cru PCLK_GPIO3>;
837 interrupt-controller;
838 #interrupt-cells = <2>;
841 gpio4: gpio4@ff7b0000 {
842 compatible = "rockchip,gpio-bank";
843 reg = <0xff7b0000 0x100>;
844 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cru PCLK_GPIO4>;
850 interrupt-controller;
851 #interrupt-cells = <2>;
854 gpio5: gpio5@ff7c0000 {
855 compatible = "rockchip,gpio-bank";
856 reg = <0xff7c0000 0x100>;
857 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&cru PCLK_GPIO5>;
863 interrupt-controller;
864 #interrupt-cells = <2>;
867 gpio6: gpio6@ff7d0000 {
868 compatible = "rockchip,gpio-bank";
869 reg = <0xff7d0000 0x100>;
870 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru PCLK_GPIO6>;
876 interrupt-controller;
877 #interrupt-cells = <2>;
880 gpio7: gpio7@ff7e0000 {
881 compatible = "rockchip,gpio-bank";
882 reg = <0xff7e0000 0x100>;
883 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&cru PCLK_GPIO7>;
889 interrupt-controller;
890 #interrupt-cells = <2>;
893 gpio8: gpio8@ff7f0000 {
894 compatible = "rockchip,gpio-bank";
895 reg = <0xff7f0000 0x100>;
896 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&cru PCLK_GPIO8>;
902 interrupt-controller;
903 #interrupt-cells = <2>;
906 pcfg_pull_up: pcfg-pull-up {
910 pcfg_pull_down: pcfg-pull-down {
914 pcfg_pull_none: pcfg-pull-none {
918 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
920 drive-strength = <12>;
924 global_pwroff: global-pwroff {
925 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
928 ddrio_pwroff: ddrio-pwroff {
929 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
932 ddr0_retention: ddr0-retention {
933 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
936 ddr1_retention: ddr1-retention {
937 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
942 i2c0_xfer: i2c0-xfer {
943 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
944 <0 16 RK_FUNC_1 &pcfg_pull_none>;
949 i2c1_xfer: i2c1-xfer {
950 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
951 <8 5 RK_FUNC_1 &pcfg_pull_none>;
956 i2c2_xfer: i2c2-xfer {
957 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
958 <6 10 RK_FUNC_1 &pcfg_pull_none>;
963 i2c3_xfer: i2c3-xfer {
964 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
965 <2 17 RK_FUNC_1 &pcfg_pull_none>;
970 i2c4_xfer: i2c4-xfer {
971 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
972 <7 18 RK_FUNC_1 &pcfg_pull_none>;
977 i2c5_xfer: i2c5-xfer {
978 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
979 <7 20 RK_FUNC_1 &pcfg_pull_none>;
985 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
986 <6 1 RK_FUNC_1 &pcfg_pull_none>,
987 <6 2 RK_FUNC_1 &pcfg_pull_none>,
988 <6 3 RK_FUNC_1 &pcfg_pull_none>,
989 <6 4 RK_FUNC_1 &pcfg_pull_none>,
990 <6 8 RK_FUNC_1 &pcfg_pull_none>;
995 sdmmc_clk: sdmmc-clk {
996 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
999 sdmmc_cmd: sdmmc-cmd {
1000 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1003 sdmmc_cd: sdmcc-cd {
1004 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1007 sdmmc_bus1: sdmmc-bus1 {
1008 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1011 sdmmc_bus4: sdmmc-bus4 {
1012 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1013 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1014 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1015 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1020 sdio0_bus1: sdio0-bus1 {
1021 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1024 sdio0_bus4: sdio0-bus4 {
1025 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1026 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1027 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1028 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1031 sdio0_cmd: sdio0-cmd {
1032 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1035 sdio0_clk: sdio0-clk {
1036 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1039 sdio0_cd: sdio0-cd {
1040 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1043 sdio0_wp: sdio0-wp {
1044 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1047 sdio0_pwr: sdio0-pwr {
1048 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1051 sdio0_bkpwr: sdio0-bkpwr {
1052 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1055 sdio0_int: sdio0-int {
1056 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1061 sdio1_bus1: sdio1-bus1 {
1062 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1065 sdio1_bus4: sdio1-bus4 {
1066 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1067 <3 25 4 &pcfg_pull_up>,
1068 <3 26 4 &pcfg_pull_up>,
1069 <3 27 4 &pcfg_pull_up>;
1072 sdio1_cd: sdio1-cd {
1073 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1076 sdio1_wp: sdio1-wp {
1077 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1080 sdio1_bkpwr: sdio1-bkpwr {
1081 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1084 sdio1_int: sdio1-int {
1085 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1088 sdio1_cmd: sdio1-cmd {
1089 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1092 sdio1_clk: sdio1-clk {
1093 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1096 sdio1_pwr: sdio1-pwr {
1097 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1102 emmc_clk: emmc-clk {
1103 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1106 emmc_cmd: emmc-cmd {
1107 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1110 emmc_pwr: emmc-pwr {
1111 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1114 emmc_bus1: emmc-bus1 {
1115 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1118 emmc_bus4: emmc-bus4 {
1119 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1120 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1121 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1122 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1125 emmc_bus8: emmc-bus8 {
1126 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1127 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1128 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1129 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1130 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1131 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1132 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1133 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1138 spi0_clk: spi0-clk {
1139 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1141 spi0_cs0: spi0-cs0 {
1142 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1145 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1148 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1150 spi0_cs1: spi0-cs1 {
1151 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1155 spi1_clk: spi1-clk {
1156 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1158 spi1_cs0: spi1-cs0 {
1159 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1162 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1165 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1170 spi2_cs1: spi2-cs1 {
1171 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1173 spi2_clk: spi2-clk {
1174 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1176 spi2_cs0: spi2-cs0 {
1177 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1180 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1183 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1188 uart0_xfer: uart0-xfer {
1189 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1190 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1193 uart0_cts: uart0-cts {
1194 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1197 uart0_rts: uart0-rts {
1198 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1203 uart1_xfer: uart1-xfer {
1204 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1205 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1208 uart1_cts: uart1-cts {
1209 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1212 uart1_rts: uart1-rts {
1213 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1218 uart2_xfer: uart2-xfer {
1219 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1220 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1222 /* no rts / cts for uart2 */
1226 uart3_xfer: uart3-xfer {
1227 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1228 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1231 uart3_cts: uart3-cts {
1232 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1235 uart3_rts: uart3-rts {
1236 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1241 uart4_xfer: uart4-xfer {
1242 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1243 <5 13 3 &pcfg_pull_none>;
1246 uart4_cts: uart4-cts {
1247 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1250 uart4_rts: uart4-rts {
1251 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1257 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1262 pwm0_pin: pwm0-pin {
1263 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1268 pwm1_pin: pwm1-pin {
1269 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1274 pwm2_pin: pwm2-pin {
1275 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1280 pwm3_pin: pwm3-pin {
1281 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1286 rgmii_pins: rgmii-pins {
1287 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1288 <3 31 3 &pcfg_pull_none>,
1289 <3 26 3 &pcfg_pull_none>,
1290 <3 27 3 &pcfg_pull_none>,
1291 <3 28 3 &pcfg_pull_none_12ma>,
1292 <3 29 3 &pcfg_pull_none_12ma>,
1293 <3 24 3 &pcfg_pull_none_12ma>,
1294 <3 25 3 &pcfg_pull_none_12ma>,
1295 <4 0 3 &pcfg_pull_none>,
1296 <4 5 3 &pcfg_pull_none>,
1297 <4 6 3 &pcfg_pull_none>,
1298 <4 9 3 &pcfg_pull_none_12ma>,
1299 <4 4 3 &pcfg_pull_none_12ma>,
1300 <4 1 3 &pcfg_pull_none>,
1301 <4 3 3 &pcfg_pull_none>;
1304 rmii_pins: rmii-pins {
1305 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1306 <3 31 3 &pcfg_pull_none>,
1307 <3 28 3 &pcfg_pull_none>,
1308 <3 29 3 &pcfg_pull_none>,
1309 <4 0 3 &pcfg_pull_none>,
1310 <4 5 3 &pcfg_pull_none>,
1311 <4 4 3 &pcfg_pull_none>,
1312 <4 1 3 &pcfg_pull_none>,
1313 <4 2 3 &pcfg_pull_none>,
1314 <4 3 3 &pcfg_pull_none>;