2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include "skeleton.dtsi"
51 compatible = "rockchip,rk3288";
53 interrupt-parent = <&gic>;
78 compatible = "arm,cortex-a12-pmu";
79 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
89 enable-method = "rockchip,rk3066-smp";
90 rockchip,pmu = <&pmu>;
94 compatible = "arm,cortex-a12";
96 resets = <&cru SRST_CORE0>;
112 #cooling-cells = <2>; /* min followed by max */
113 clock-latency = <40000>;
114 clocks = <&cru ARMCLK>;
118 compatible = "arm,cortex-a12";
120 resets = <&cru SRST_CORE1>;
124 compatible = "arm,cortex-a12";
126 resets = <&cru SRST_CORE2>;
130 compatible = "arm,cortex-a12";
132 resets = <&cru SRST_CORE3>;
137 compatible = "simple-bus";
138 #address-cells = <1>;
142 dmac_peri: dma-controller@ff250000 {
143 compatible = "arm,pl330", "arm,primecell";
144 reg = <0xff250000 0x4000>;
145 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
148 arm,pl330-broken-no-flushp;
149 clocks = <&cru ACLK_DMAC2>;
150 clock-names = "apb_pclk";
153 dmac_bus_ns: dma-controller@ff600000 {
154 compatible = "arm,pl330", "arm,primecell";
155 reg = <0xff600000 0x4000>;
156 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
159 arm,pl330-broken-no-flushp;
160 clocks = <&cru ACLK_DMAC1>;
161 clock-names = "apb_pclk";
165 dmac_bus_s: dma-controller@ffb20000 {
166 compatible = "arm,pl330", "arm,primecell";
167 reg = <0xffb20000 0x4000>;
168 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
171 arm,pl330-broken-no-flushp;
172 clocks = <&cru ACLK_DMAC1>;
173 clock-names = "apb_pclk";
178 #address-cells = <1>;
183 * The rk3288 cannot use the memory area above 0xfe000000
184 * for dma operations for some reason. While there is
185 * probably a better solution available somewhere, we
186 * haven't found it yet and while devices with 2GB of ram
187 * are not affected, this issue prevents 4GB from booting.
188 * So to make these devices at least bootable, block
189 * this area for the time being until the real solution
192 dma-unusable@fe000000 {
193 reg = <0xfe000000 0x1000000>;
198 compatible = "fixed-clock";
199 clock-frequency = <24000000>;
200 clock-output-names = "xin24m";
205 compatible = "arm,armv7-timer";
206 arm,cpu-registers-not-fw-configured;
207 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
208 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
210 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 clock-frequency = <24000000>;
214 timer: timer@ff810000 {
215 compatible = "rockchip,rk3288-timer";
216 reg = <0xff810000 0x20>;
217 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&xin24m>, <&cru PCLK_TIMER>;
219 clock-names = "timer", "pclk";
223 compatible = "rockchip,display-subsystem";
224 ports = <&vopl_out>, <&vopb_out>;
227 sdmmc: dwmmc@ff0c0000 {
228 compatible = "rockchip,rk3288-dw-mshc";
229 clock-freq-min-max = <400000 150000000>;
230 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
231 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
232 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
233 fifo-depth = <0x100>;
234 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
235 reg = <0xff0c0000 0x4000>;
239 sdio0: dwmmc@ff0d0000 {
240 compatible = "rockchip,rk3288-dw-mshc";
241 clock-freq-min-max = <400000 150000000>;
242 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
243 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
244 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
245 fifo-depth = <0x100>;
246 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
247 reg = <0xff0d0000 0x4000>;
251 sdio1: dwmmc@ff0e0000 {
252 compatible = "rockchip,rk3288-dw-mshc";
253 clock-freq-min-max = <400000 150000000>;
254 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
255 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
256 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
257 fifo-depth = <0x100>;
258 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
259 reg = <0xff0e0000 0x4000>;
263 emmc: dwmmc@ff0f0000 {
264 compatible = "rockchip,rk3288-dw-mshc";
265 clock-freq-min-max = <400000 150000000>;
266 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
267 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
268 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
269 fifo-depth = <0x100>;
270 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
271 reg = <0xff0f0000 0x4000>;
275 saradc: saradc@ff100000 {
276 compatible = "rockchip,saradc";
277 reg = <0xff100000 0x100>;
278 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
279 #io-channel-cells = <1>;
280 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
281 clock-names = "saradc", "apb_pclk";
286 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
287 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
288 clock-names = "spiclk", "apb_pclk";
289 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
290 dma-names = "tx", "rx";
291 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
294 reg = <0xff110000 0x1000>;
295 #address-cells = <1>;
301 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
302 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
303 clock-names = "spiclk", "apb_pclk";
304 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
305 dma-names = "tx", "rx";
306 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
309 reg = <0xff120000 0x1000>;
310 #address-cells = <1>;
316 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
317 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
318 clock-names = "spiclk", "apb_pclk";
319 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
320 dma-names = "tx", "rx";
321 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
324 reg = <0xff130000 0x1000>;
325 #address-cells = <1>;
331 compatible = "rockchip,rk3288-i2c";
332 reg = <0xff140000 0x1000>;
333 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
337 clocks = <&cru PCLK_I2C1>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c1_xfer>;
344 compatible = "rockchip,rk3288-i2c";
345 reg = <0xff150000 0x1000>;
346 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
350 clocks = <&cru PCLK_I2C3>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c3_xfer>;
357 compatible = "rockchip,rk3288-i2c";
358 reg = <0xff160000 0x1000>;
359 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
363 clocks = <&cru PCLK_I2C4>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c4_xfer>;
370 compatible = "rockchip,rk3288-i2c";
371 reg = <0xff170000 0x1000>;
372 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
373 #address-cells = <1>;
376 clocks = <&cru PCLK_I2C5>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c5_xfer>;
382 uart0: serial@ff180000 {
383 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
384 reg = <0xff180000 0x100>;
385 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
389 clock-names = "baudclk", "apb_pclk";
390 pinctrl-names = "default";
391 pinctrl-0 = <&uart0_xfer>;
395 uart1: serial@ff190000 {
396 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
397 reg = <0xff190000 0x100>;
398 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
402 clock-names = "baudclk", "apb_pclk";
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart1_xfer>;
408 uart2: serial@ff690000 {
409 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
410 reg = <0xff690000 0x100>;
411 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
415 clock-names = "baudclk", "apb_pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&uart2_xfer>;
421 uart3: serial@ff1b0000 {
422 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
423 reg = <0xff1b0000 0x100>;
424 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
428 clock-names = "baudclk", "apb_pclk";
429 pinctrl-names = "default";
430 pinctrl-0 = <&uart3_xfer>;
434 uart4: serial@ff1c0000 {
435 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
436 reg = <0xff1c0000 0x100>;
437 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
441 clock-names = "baudclk", "apb_pclk";
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart4_xfer>;
448 #include "rk3288-thermal.dtsi"
451 tsadc: tsadc@ff280000 {
452 compatible = "rockchip,rk3288-tsadc";
453 reg = <0xff280000 0x100>;
454 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
456 clock-names = "tsadc", "apb_pclk";
457 resets = <&cru SRST_TSADC>;
458 reset-names = "tsadc-apb";
459 pinctrl-names = "init", "default", "sleep";
460 pinctrl-0 = <&otp_gpio>;
461 pinctrl-1 = <&otp_out>;
462 pinctrl-2 = <&otp_gpio>;
463 #thermal-sensor-cells = <1>;
464 rockchip,hw-tshut-temp = <95000>;
468 gmac: ethernet@ff290000 {
469 compatible = "rockchip,rk3288-gmac";
470 reg = <0xff290000 0x10000>;
471 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-names = "macirq";
473 rockchip,grf = <&grf>;
474 clocks = <&cru SCLK_MAC>,
475 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
476 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
477 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
478 clock-names = "stmmaceth",
479 "mac_clk_rx", "mac_clk_tx",
480 "clk_mac_ref", "clk_mac_refout",
481 "aclk_mac", "pclk_mac";
482 resets = <&cru SRST_MAC>;
483 reset-names = "stmmaceth";
487 usb_host0_ehci: usb@ff500000 {
488 compatible = "generic-ehci";
489 reg = <0xff500000 0x100>;
490 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cru HCLK_USBHOST0>;
492 clock-names = "usbhost";
498 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
500 usb_host1: usb@ff540000 {
501 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
503 reg = <0xff540000 0x40000>;
504 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&cru HCLK_USBHOST1>;
509 phy-names = "usb2-phy";
513 usb_otg: usb@ff580000 {
514 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
516 reg = <0xff580000 0x40000>;
517 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru HCLK_OTG0>;
521 g-np-tx-fifo-size = <16>;
522 g-rx-fifo-size = <275>;
523 g-tx-fifo-size = <256 128 128 64 64 32>;
526 phy-names = "usb2-phy";
530 usb_hsic: usb@ff5c0000 {
531 compatible = "generic-ehci";
532 reg = <0xff5c0000 0x100>;
533 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cru HCLK_HSIC>;
535 clock-names = "usbhost";
540 compatible = "rockchip,rk3288-i2c";
541 reg = <0xff650000 0x1000>;
542 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
543 #address-cells = <1>;
546 clocks = <&cru PCLK_I2C0>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c0_xfer>;
553 compatible = "rockchip,rk3288-i2c";
554 reg = <0xff660000 0x1000>;
555 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
556 #address-cells = <1>;
559 clocks = <&cru PCLK_I2C2>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c2_xfer>;
566 compatible = "rockchip,rk3288-pwm";
567 reg = <0xff680000 0x10>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&pwm0_pin>;
571 clocks = <&cru PCLK_PWM>;
577 compatible = "rockchip,rk3288-pwm";
578 reg = <0xff680010 0x10>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&pwm1_pin>;
582 clocks = <&cru PCLK_PWM>;
588 compatible = "rockchip,rk3288-pwm";
589 reg = <0xff680020 0x10>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&pwm2_pin>;
593 clocks = <&cru PCLK_PWM>;
599 compatible = "rockchip,rk3288-pwm";
600 reg = <0xff680030 0x10>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&pwm3_pin>;
604 clocks = <&cru PCLK_PWM>;
609 bus_intmem@ff700000 {
610 compatible = "mmio-sram";
611 reg = <0xff700000 0x18000>;
612 #address-cells = <1>;
614 ranges = <0 0xff700000 0x18000>;
616 compatible = "rockchip,rk3066-smp-sram";
622 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
623 reg = <0xff720000 0x1000>;
626 pmu: power-management@ff730000 {
627 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
628 reg = <0xff730000 0x100>;
630 power: power-controller {
631 compatible = "rockchip,rk3288-power-controller";
632 #power-domain-cells = <1>;
633 #address-cells = <1>;
636 assigned-clocks = <&cru SCLK_EDP_24M>;
637 assigned-clock-parents = <&xin24m>;
640 * Note: Although SCLK_* are the working clocks
641 * of device without including on the NOC, needed for
644 * The clocks on the which NOC:
645 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
646 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
647 * ACLK_RGA is on ACLK_RGA_NIU.
648 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
650 * Which clock are device clocks:
652 * *_IEP IEP:Image Enhancement Processor
653 * *_ISP ISP:Image Signal Processing
654 * *_VIP VIP:Video Input Processor
655 * *_VOP* VOP:Visual Output Processor
663 reg = <RK3288_PD_VIO>;
664 clocks = <&cru ACLK_IEP>,
678 <&cru PCLK_EDP_CTRL>,
679 <&cru PCLK_HDMI_CTRL>,
680 <&cru PCLK_LVDS_PHY>,
681 <&cru PCLK_MIPI_CSI>,
682 <&cru PCLK_MIPI_DSI0>,
683 <&cru PCLK_MIPI_DSI1>,
692 * Note: The following 3 are HEVC(H.265) clocks,
693 * and on the ACLK_HEVC_NIU (NOC).
696 reg = <RK3288_PD_HEVC>;
697 clocks = <&cru ACLK_HEVC>,
698 <&cru SCLK_HEVC_CABAC>,
699 <&cru SCLK_HEVC_CORE>;
703 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
704 * (video endecoder & decoder) clocks that on the
705 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
708 reg = <RK3288_PD_VIDEO>;
709 clocks = <&cru ACLK_VCODEC>,
714 * Note: ACLK_GPU is the GPU clock,
715 * and on the ACLK_GPU_NIU (NOC).
718 reg = <RK3288_PD_GPU>;
719 clocks = <&cru ACLK_GPU>;
724 sgrf: syscon@ff740000 {
725 compatible = "rockchip,rk3288-sgrf", "syscon";
726 reg = <0xff740000 0x1000>;
729 cru: clock-controller@ff760000 {
730 compatible = "rockchip,rk3288-cru";
731 reg = <0xff760000 0x1000>;
732 rockchip,grf = <&grf>;
735 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
736 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
737 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
738 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
740 assigned-clock-rates = <594000000>, <400000000>,
741 <500000000>, <300000000>,
742 <150000000>, <75000000>,
743 <300000000>, <150000000>,
747 grf: syscon@ff770000 {
748 compatible = "rockchip,rk3288-grf", "syscon";
749 reg = <0xff770000 0x1000>;
752 wdt: watchdog@ff800000 {
753 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
754 reg = <0xff800000 0x100>;
755 clocks = <&cru PCLK_WDT>;
756 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
760 spdif: sound@ff88b0000 {
761 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
762 reg = <0xff8b0000 0x10000>;
763 #sound-dai-cells = <0>;
764 clock-names = "hclk", "mclk";
765 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
766 dmas = <&dmac_bus_s 3>;
768 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&spdif_tx>;
771 rockchip,grf = <&grf>;
776 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
777 reg = <0xff890000 0x10000>;
778 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
779 #address-cells = <1>;
781 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
782 dma-names = "tx", "rx";
783 clock-names = "i2s_hclk", "i2s_clk";
784 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
785 pinctrl-names = "default";
786 pinctrl-0 = <&i2s0_bus>;
787 rockchip,playback-channels = <8>;
788 rockchip,capture-channels = <2>;
792 crypto: cypto-controller@ff8a0000 {
793 compatible = "rockchip,rk3288-crypto";
794 reg = <0xff8a0000 0x4000>;
795 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
797 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
798 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
799 resets = <&cru SRST_CRYPTO>;
800 reset-names = "crypto-rst";
805 compatible = "rockchip,rk3288-vop";
806 reg = <0xff930000 0x19c>;
807 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
809 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
810 power-domains = <&power RK3288_PD_VIO>;
811 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
812 reset-names = "axi", "ahb", "dclk";
813 iommus = <&vopb_mmu>;
817 #address-cells = <1>;
820 vopb_out_hdmi: endpoint@0 {
822 remote-endpoint = <&hdmi_in_vopb>;
824 vopb_out_mipi: endpoint@2 {
826 remote-endpoint = <&mipi_in_vopb>;
831 vopb_mmu: iommu@ff930300 {
832 compatible = "rockchip,iommu";
833 reg = <0xff930300 0x100>;
834 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "vopb_mmu";
836 power-domains = <&power RK3288_PD_VIO>;
842 compatible = "rockchip,rk3288-vop";
843 reg = <0xff940000 0x19c>;
844 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
846 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
847 power-domains = <&power RK3288_PD_VIO>;
848 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
849 reset-names = "axi", "ahb", "dclk";
850 iommus = <&vopl_mmu>;
854 #address-cells = <1>;
857 vopl_out_hdmi: endpoint@0 {
859 remote-endpoint = <&hdmi_in_vopl>;
861 vopl_out_mipi: endpoint@2 {
863 remote-endpoint = <&mipi_in_vopl>;
868 vopl_mmu: iommu@ff940300 {
869 compatible = "rockchip,iommu";
870 reg = <0xff940300 0x100>;
871 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
872 interrupt-names = "vopl_mmu";
873 power-domains = <&power RK3288_PD_VIO>;
878 mipi_dsi: mipi@ff960000 {
879 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
880 reg = <0xff960000 0x4000>;
881 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
883 clock-names = "ref", "pclk";
884 rockchip,grf = <&grf>;
885 #address-cells = <1>;
890 #address-cells = <1>;
895 #address-cells = <1>;
897 mipi_in_vopb: endpoint@0 {
899 remote-endpoint = <&vopb_out_mipi>;
901 mipi_in_vopl: endpoint@1 {
903 remote-endpoint = <&vopl_out_mipi>;
909 hdmi: hdmi@ff980000 {
910 compatible = "rockchip,rk3288-dw-hdmi";
911 reg = <0xff980000 0x20000>;
913 rockchip,grf = <&grf>;
914 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
916 clock-names = "iahb", "isfr";
917 power-domains = <&power RK3288_PD_VIO>;
922 #address-cells = <1>;
924 hdmi_in_vopb: endpoint@0 {
926 remote-endpoint = <&vopb_out_hdmi>;
928 hdmi_in_vopl: endpoint@1 {
930 remote-endpoint = <&vopl_out_hdmi>;
936 gic: interrupt-controller@ffc01000 {
937 compatible = "arm,gic-400";
938 interrupt-controller;
939 #interrupt-cells = <3>;
940 #address-cells = <0>;
942 reg = <0xffc01000 0x1000>,
946 interrupts = <GIC_PPI 9 0xf04>;
949 efuse: efuse@ffb40000 {
950 compatible = "rockchip,rockchip-efuse";
951 reg = <0xffb40000 0x20>;
952 #address-cells = <1>;
954 clocks = <&cru PCLK_EFUSE256>;
955 clock-names = "pclk_efuse";
957 cpu_leakage: cpu_leakage@17 {
963 compatible = "rockchip,rk3288-usb-phy";
964 rockchip,grf = <&grf>;
965 #address-cells = <1>;
972 clocks = <&cru SCLK_OTGPHY0>;
973 clock-names = "phyclk";
980 clocks = <&cru SCLK_OTGPHY1>;
981 clock-names = "phyclk";
988 clocks = <&cru SCLK_OTGPHY2>;
989 clock-names = "phyclk";
995 compatible = "rockchip,rk3288-pinctrl";
996 rockchip,grf = <&grf>;
997 rockchip,pmu = <&pmu>;
998 #address-cells = <1>;
1002 gpio0: gpio0@ff750000 {
1003 compatible = "rockchip,gpio-bank";
1004 reg = <0xff750000 0x100>;
1005 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&cru PCLK_GPIO0>;
1011 interrupt-controller;
1012 #interrupt-cells = <2>;
1015 gpio1: gpio1@ff780000 {
1016 compatible = "rockchip,gpio-bank";
1017 reg = <0xff780000 0x100>;
1018 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&cru PCLK_GPIO1>;
1024 interrupt-controller;
1025 #interrupt-cells = <2>;
1028 gpio2: gpio2@ff790000 {
1029 compatible = "rockchip,gpio-bank";
1030 reg = <0xff790000 0x100>;
1031 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cru PCLK_GPIO2>;
1037 interrupt-controller;
1038 #interrupt-cells = <2>;
1041 gpio3: gpio3@ff7a0000 {
1042 compatible = "rockchip,gpio-bank";
1043 reg = <0xff7a0000 0x100>;
1044 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&cru PCLK_GPIO3>;
1050 interrupt-controller;
1051 #interrupt-cells = <2>;
1054 gpio4: gpio4@ff7b0000 {
1055 compatible = "rockchip,gpio-bank";
1056 reg = <0xff7b0000 0x100>;
1057 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&cru PCLK_GPIO4>;
1063 interrupt-controller;
1064 #interrupt-cells = <2>;
1067 gpio5: gpio5@ff7c0000 {
1068 compatible = "rockchip,gpio-bank";
1069 reg = <0xff7c0000 0x100>;
1070 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&cru PCLK_GPIO5>;
1076 interrupt-controller;
1077 #interrupt-cells = <2>;
1080 gpio6: gpio6@ff7d0000 {
1081 compatible = "rockchip,gpio-bank";
1082 reg = <0xff7d0000 0x100>;
1083 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&cru PCLK_GPIO6>;
1089 interrupt-controller;
1090 #interrupt-cells = <2>;
1093 gpio7: gpio7@ff7e0000 {
1094 compatible = "rockchip,gpio-bank";
1095 reg = <0xff7e0000 0x100>;
1096 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&cru PCLK_GPIO7>;
1102 interrupt-controller;
1103 #interrupt-cells = <2>;
1106 gpio8: gpio8@ff7f0000 {
1107 compatible = "rockchip,gpio-bank";
1108 reg = <0xff7f0000 0x100>;
1109 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&cru PCLK_GPIO8>;
1115 interrupt-controller;
1116 #interrupt-cells = <2>;
1120 hdmi_ddc: hdmi-ddc {
1121 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1122 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1126 pcfg_pull_up: pcfg-pull-up {
1130 pcfg_pull_down: pcfg-pull-down {
1134 pcfg_pull_none: pcfg-pull-none {
1138 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1140 drive-strength = <12>;
1144 global_pwroff: global-pwroff {
1145 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1148 ddrio_pwroff: ddrio-pwroff {
1149 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1152 ddr0_retention: ddr0-retention {
1153 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1156 ddr1_retention: ddr1-retention {
1157 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1162 i2c0_xfer: i2c0-xfer {
1163 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1164 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1169 i2c1_xfer: i2c1-xfer {
1170 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1171 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1176 i2c2_xfer: i2c2-xfer {
1177 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1178 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1183 i2c3_xfer: i2c3-xfer {
1184 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1185 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1190 i2c4_xfer: i2c4-xfer {
1191 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1192 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1197 i2c5_xfer: i2c5-xfer {
1198 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1199 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1204 i2s0_bus: i2s0-bus {
1205 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1206 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1207 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1208 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1209 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1210 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1215 sdmmc_clk: sdmmc-clk {
1216 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1219 sdmmc_cmd: sdmmc-cmd {
1220 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1223 sdmmc_cd: sdmmc-cd {
1224 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1227 sdmmc_bus1: sdmmc-bus1 {
1228 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1231 sdmmc_bus4: sdmmc-bus4 {
1232 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1233 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1234 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1235 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1240 sdio0_bus1: sdio0-bus1 {
1241 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1244 sdio0_bus4: sdio0-bus4 {
1245 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1246 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1247 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1248 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1251 sdio0_cmd: sdio0-cmd {
1252 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1255 sdio0_clk: sdio0-clk {
1256 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1259 sdio0_cd: sdio0-cd {
1260 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1263 sdio0_wp: sdio0-wp {
1264 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1267 sdio0_pwr: sdio0-pwr {
1268 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1271 sdio0_bkpwr: sdio0-bkpwr {
1272 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1275 sdio0_int: sdio0-int {
1276 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1281 sdio1_bus1: sdio1-bus1 {
1282 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1285 sdio1_bus4: sdio1-bus4 {
1286 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1287 <3 25 4 &pcfg_pull_up>,
1288 <3 26 4 &pcfg_pull_up>,
1289 <3 27 4 &pcfg_pull_up>;
1292 sdio1_cd: sdio1-cd {
1293 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1296 sdio1_wp: sdio1-wp {
1297 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1300 sdio1_bkpwr: sdio1-bkpwr {
1301 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1304 sdio1_int: sdio1-int {
1305 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1308 sdio1_cmd: sdio1-cmd {
1309 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1312 sdio1_clk: sdio1-clk {
1313 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1316 sdio1_pwr: sdio1-pwr {
1317 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1322 emmc_clk: emmc-clk {
1323 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1326 emmc_cmd: emmc-cmd {
1327 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1330 emmc_pwr: emmc-pwr {
1331 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1334 emmc_bus1: emmc-bus1 {
1335 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1338 emmc_bus4: emmc-bus4 {
1339 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1340 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1341 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1342 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1345 emmc_bus8: emmc-bus8 {
1346 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1347 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1348 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1349 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1350 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1351 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1352 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1353 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1358 spi0_clk: spi0-clk {
1359 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1361 spi0_cs0: spi0-cs0 {
1362 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1365 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1368 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1370 spi0_cs1: spi0-cs1 {
1371 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1375 spi1_clk: spi1-clk {
1376 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1378 spi1_cs0: spi1-cs0 {
1379 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1382 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1385 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1390 spi2_cs1: spi2-cs1 {
1391 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1393 spi2_clk: spi2-clk {
1394 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1396 spi2_cs0: spi2-cs0 {
1397 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1400 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1403 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1408 uart0_xfer: uart0-xfer {
1409 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1410 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1413 uart0_cts: uart0-cts {
1414 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1417 uart0_rts: uart0-rts {
1418 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1423 uart1_xfer: uart1-xfer {
1424 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1425 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1428 uart1_cts: uart1-cts {
1429 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1432 uart1_rts: uart1-rts {
1433 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1438 uart2_xfer: uart2-xfer {
1439 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1440 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1442 /* no rts / cts for uart2 */
1446 uart3_xfer: uart3-xfer {
1447 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1448 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1451 uart3_cts: uart3-cts {
1452 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1455 uart3_rts: uart3-rts {
1456 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1461 uart4_xfer: uart4-xfer {
1462 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1463 <5 13 3 &pcfg_pull_none>;
1466 uart4_cts: uart4-cts {
1467 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1470 uart4_rts: uart4-rts {
1471 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1476 otp_gpio: otp-gpio {
1477 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1481 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1486 pwm0_pin: pwm0-pin {
1487 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1492 pwm1_pin: pwm1-pin {
1493 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1498 pwm2_pin: pwm2-pin {
1499 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1504 pwm3_pin: pwm3-pin {
1505 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1510 rgmii_pins: rgmii-pins {
1511 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1512 <3 31 3 &pcfg_pull_none>,
1513 <3 26 3 &pcfg_pull_none>,
1514 <3 27 3 &pcfg_pull_none>,
1515 <3 28 3 &pcfg_pull_none_12ma>,
1516 <3 29 3 &pcfg_pull_none_12ma>,
1517 <3 24 3 &pcfg_pull_none_12ma>,
1518 <3 25 3 &pcfg_pull_none_12ma>,
1519 <4 0 3 &pcfg_pull_none>,
1520 <4 5 3 &pcfg_pull_none>,
1521 <4 6 3 &pcfg_pull_none>,
1522 <4 9 3 &pcfg_pull_none_12ma>,
1523 <4 4 3 &pcfg_pull_none_12ma>,
1524 <4 1 3 &pcfg_pull_none>,
1525 <4 3 3 &pcfg_pull_none>;
1528 rmii_pins: rmii-pins {
1529 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1530 <3 31 3 &pcfg_pull_none>,
1531 <3 28 3 &pcfg_pull_none>,
1532 <3 29 3 &pcfg_pull_none>,
1533 <4 0 3 &pcfg_pull_none>,
1534 <4 5 3 &pcfg_pull_none>,
1535 <4 4 3 &pcfg_pull_none>,
1536 <4 1 3 &pcfg_pull_none>,
1537 <4 2 3 &pcfg_pull_none>,
1538 <4 3 3 &pcfg_pull_none>;
1543 spdif_tx: spdif-tx {
1544 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;