arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/soc/rockchip,boot-mode.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 ethernet0 = &emac;
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 mshc0 = &emmc;
  62                 mshc1 = &mmc0;
  63                 mshc2 = &mmc1;
  64                 serial0 = &uart0;
  65                 serial1 = &uart1;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         amba {
  73                 compatible = "simple-bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77
  78                 dmac1_s: dma-controller@20018000 {
  79                         compatible = "arm,pl330", "arm,primecell";
  80                         reg = <0x20018000 0x4000>;
  81                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  83                         #dma-cells = <1>;
  84                         arm,pl330-broken-no-flushp;
  85                         clocks = <&cru ACLK_DMA1>;
  86                         clock-names = "apb_pclk";
  87                 };
  88
  89                 dmac1_ns: dma-controller@2001c000 {
  90                         compatible = "arm,pl330", "arm,primecell";
  91                         reg = <0x2001c000 0x4000>;
  92                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  94                         #dma-cells = <1>;
  95                         arm,pl330-broken-no-flushp;
  96                         clocks = <&cru ACLK_DMA1>;
  97                         clock-names = "apb_pclk";
  98                         status = "disabled";
  99                 };
 100
 101                 dmac2: dma-controller@20078000 {
 102                         compatible = "arm,pl330", "arm,primecell";
 103                         reg = <0x20078000 0x4000>;
 104                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 106                         #dma-cells = <1>;
 107                         arm,pl330-broken-no-flushp;
 108                         clocks = <&cru ACLK_DMA2>;
 109                         clock-names = "apb_pclk";
 110                 };
 111         };
 112
 113         xin24m: oscillator {
 114                 compatible = "fixed-clock";
 115                 clock-frequency = <24000000>;
 116                 #clock-cells = <0>;
 117                 clock-output-names = "xin24m";
 118         };
 119
 120         L2: l2-cache-controller@10138000 {
 121                 compatible = "arm,pl310-cache";
 122                 reg = <0x10138000 0x1000>;
 123                 cache-unified;
 124                 cache-level = <2>;
 125         };
 126
 127         scu@1013c000 {
 128                 compatible = "arm,cortex-a9-scu";
 129                 reg = <0x1013c000 0x100>;
 130         };
 131
 132         global_timer: global-timer@1013c200 {
 133                 compatible = "arm,cortex-a9-global-timer";
 134                 reg = <0x1013c200 0x20>;
 135                 interrupts = <GIC_PPI 11 0x304>;
 136                 clocks = <&cru CORE_PERI>;
 137         };
 138
 139         local_timer: local-timer@1013c600 {
 140                 compatible = "arm,cortex-a9-twd-timer";
 141                 reg = <0x1013c600 0x20>;
 142                 interrupts = <GIC_PPI 13 0x304>;
 143                 clocks = <&cru CORE_PERI>;
 144         };
 145
 146         gic: interrupt-controller@1013d000 {
 147                 compatible = "arm,cortex-a9-gic";
 148                 interrupt-controller;
 149                 #interrupt-cells = <3>;
 150                 reg = <0x1013d000 0x1000>,
 151                       <0x1013c100 0x0100>;
 152         };
 153
 154         uart0: serial@10124000 {
 155                 compatible = "snps,dw-apb-uart";
 156                 reg = <0x10124000 0x400>;
 157                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 158                 reg-shift = <2>;
 159                 reg-io-width = <1>;
 160                 clock-names = "baudclk", "apb_pclk";
 161                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 162                 status = "disabled";
 163         };
 164
 165         uart1: serial@10126000 {
 166                 compatible = "snps,dw-apb-uart";
 167                 reg = <0x10126000 0x400>;
 168                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 169                 reg-shift = <2>;
 170                 reg-io-width = <1>;
 171                 clock-names = "baudclk", "apb_pclk";
 172                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 173                 status = "disabled";
 174         };
 175
 176         usb_otg: usb@10180000 {
 177                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 178                 reg = <0x10180000 0x40000>;
 179                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 180                 clocks = <&cru HCLK_OTG0>;
 181                 clock-names = "otg";
 182                 dr_mode = "otg";
 183                 g-np-tx-fifo-size = <16>;
 184                 g-rx-fifo-size = <275>;
 185                 g-tx-fifo-size = <256 128 128 64 64 32>;
 186                 phys = <&usbphy0>;
 187                 phy-names = "usb2-phy";
 188                 status = "disabled";
 189         };
 190
 191         usb_host: usb@101c0000 {
 192                 compatible = "snps,dwc2";
 193                 reg = <0x101c0000 0x40000>;
 194                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 195                 clocks = <&cru HCLK_OTG1>;
 196                 clock-names = "otg";
 197                 dr_mode = "host";
 198                 phys = <&usbphy1>;
 199                 phy-names = "usb2-phy";
 200                 status = "disabled";
 201         };
 202
 203         emac: ethernet@10204000 {
 204                 compatible = "snps,arc-emac";
 205                 reg = <0x10204000 0x3c>;
 206                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 207                 #address-cells = <1>;
 208                 #size-cells = <0>;
 209
 210                 rockchip,grf = <&grf>;
 211
 212                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 213                 clock-names = "hclk", "macref";
 214                 max-speed = <100>;
 215                 phy-mode = "rmii";
 216
 217                 status = "disabled";
 218         };
 219
 220         mmc0: dwmmc@10214000 {
 221                 compatible = "rockchip,rk2928-dw-mshc";
 222                 reg = <0x10214000 0x1000>;
 223                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 225                 clock-names = "biu", "ciu";
 226                 fifo-depth = <256>;
 227                 status = "disabled";
 228         };
 229
 230         mmc1: dwmmc@10218000 {
 231                 compatible = "rockchip,rk2928-dw-mshc";
 232                 reg = <0x10218000 0x1000>;
 233                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 235                 clock-names = "biu", "ciu";
 236                 fifo-depth = <256>;
 237                 status = "disabled";
 238         };
 239
 240         emmc: dwmmc@1021c000 {
 241                 compatible = "rockchip,rk2928-dw-mshc";
 242                 reg = <0x1021c000 0x1000>;
 243                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 244                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 245                 clock-names = "biu", "ciu";
 246                 fifo-depth = <256>;
 247                 status = "disabled";
 248         };
 249
 250         pmu: pmu@20004000 {
 251                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 252                 reg = <0x20004000 0x100>;
 253
 254                 reboot-mode {
 255                         compatible = "syscon-reboot-mode";
 256                         offset = <0x40>;
 257                         mode-normal = <BOOT_NORMAL>;
 258                         mode-recovery = <BOOT_RECOVERY>;
 259                         mode-bootloader = <BOOT_FASTBOOT>;
 260                         mode-loader = <BOOT_BL_DOWNLOAD>;
 261                 };
 262         };
 263
 264         grf: grf@20008000 {
 265                 compatible = "syscon";
 266                 reg = <0x20008000 0x200>;
 267         };
 268
 269         i2c0: i2c@2002d000 {
 270                 compatible = "rockchip,rk3066-i2c";
 271                 reg = <0x2002d000 0x1000>;
 272                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275
 276                 rockchip,grf = <&grf>;
 277
 278                 clock-names = "i2c";
 279                 clocks = <&cru PCLK_I2C0>;
 280
 281                 status = "disabled";
 282         };
 283
 284         i2c1: i2c@2002f000 {
 285                 compatible = "rockchip,rk3066-i2c";
 286                 reg = <0x2002f000 0x1000>;
 287                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290
 291                 rockchip,grf = <&grf>;
 292
 293                 clocks = <&cru PCLK_I2C1>;
 294                 clock-names = "i2c";
 295
 296                 status = "disabled";
 297         };
 298
 299         pwm0: pwm@20030000 {
 300                 compatible = "rockchip,rk2928-pwm";
 301                 reg = <0x20030000 0x10>;
 302                 #pwm-cells = <2>;
 303                 clocks = <&cru PCLK_PWM01>;
 304                 status = "disabled";
 305         };
 306
 307         pwm1: pwm@20030010 {
 308                 compatible = "rockchip,rk2928-pwm";
 309                 reg = <0x20030010 0x10>;
 310                 #pwm-cells = <2>;
 311                 clocks = <&cru PCLK_PWM01>;
 312                 status = "disabled";
 313         };
 314
 315         wdt: watchdog@2004c000 {
 316                 compatible = "snps,dw-wdt";
 317                 reg = <0x2004c000 0x100>;
 318                 clocks = <&cru PCLK_WDT>;
 319                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 320                 status = "disabled";
 321         };
 322
 323         pwm2: pwm@20050020 {
 324                 compatible = "rockchip,rk2928-pwm";
 325                 reg = <0x20050020 0x10>;
 326                 #pwm-cells = <2>;
 327                 clocks = <&cru PCLK_PWM23>;
 328                 status = "disabled";
 329         };
 330
 331         pwm3: pwm@20050030 {
 332                 compatible = "rockchip,rk2928-pwm";
 333                 reg = <0x20050030 0x10>;
 334                 #pwm-cells = <2>;
 335                 clocks = <&cru PCLK_PWM23>;
 336                 status = "disabled";
 337         };
 338
 339         i2c2: i2c@20056000 {
 340                 compatible = "rockchip,rk3066-i2c";
 341                 reg = <0x20056000 0x1000>;
 342                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345
 346                 rockchip,grf = <&grf>;
 347
 348                 clocks = <&cru PCLK_I2C2>;
 349                 clock-names = "i2c";
 350
 351                 status = "disabled";
 352         };
 353
 354         i2c3: i2c@2005a000 {
 355                 compatible = "rockchip,rk3066-i2c";
 356                 reg = <0x2005a000 0x1000>;
 357                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360
 361                 rockchip,grf = <&grf>;
 362
 363                 clocks = <&cru PCLK_I2C3>;
 364                 clock-names = "i2c";
 365
 366                 status = "disabled";
 367         };
 368
 369         i2c4: i2c@2005e000 {
 370                 compatible = "rockchip,rk3066-i2c";
 371                 reg = <0x2005e000 0x1000>;
 372                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375
 376                 rockchip,grf = <&grf>;
 377
 378                 clocks = <&cru PCLK_I2C4>;
 379                 clock-names = "i2c";
 380
 381                 status = "disabled";
 382         };
 383
 384         uart2: serial@20064000 {
 385                 compatible = "snps,dw-apb-uart";
 386                 reg = <0x20064000 0x400>;
 387                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 388                 reg-shift = <2>;
 389                 reg-io-width = <1>;
 390                 clock-names = "baudclk", "apb_pclk";
 391                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 392                 status = "disabled";
 393         };
 394
 395         uart3: serial@20068000 {
 396                 compatible = "snps,dw-apb-uart";
 397                 reg = <0x20068000 0x400>;
 398                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 399                 reg-shift = <2>;
 400                 reg-io-width = <1>;
 401                 clock-names = "baudclk", "apb_pclk";
 402                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 403                 status = "disabled";
 404         };
 405
 406         saradc: saradc@2006c000 {
 407                 compatible = "rockchip,saradc";
 408                 reg = <0x2006c000 0x100>;
 409                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 410                 #io-channel-cells = <1>;
 411                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 412                 clock-names = "saradc", "apb_pclk";
 413                 resets = <&cru SRST_SARADC>;
 414                 reset-names = "saradc-apb";
 415                 status = "disabled";
 416         };
 417
 418         spi0: spi@20070000 {
 419                 compatible = "rockchip,rk3066-spi";
 420                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 421                 clock-names = "spiclk", "apb_pclk";
 422                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 423                 reg = <0x20070000 0x1000>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 dmas = <&dmac2 10>, <&dmac2 11>;
 427                 dma-names = "tx", "rx";
 428                 status = "disabled";
 429         };
 430
 431         spi1: spi@20074000 {
 432                 compatible = "rockchip,rk3066-spi";
 433                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 434                 clock-names = "spiclk", "apb_pclk";
 435                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 436                 reg = <0x20074000 0x1000>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 dmas = <&dmac2 12>, <&dmac2 13>;
 440                 dma-names = "tx", "rx";
 441                 status = "disabled";
 442         };
 443 };