2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
69 compatible = "arm,cortex-a5";
71 next-level-cache = <&L2>;
76 reg = <0x20000000 0x20000000>;
80 slow_xtal: slow_xtal {
81 compatible = "fixed-clock";
83 clock-frequency = <0>;
86 main_xtal: main_xtal {
87 compatible = "fixed-clock";
89 clock-frequency = <0>;
92 adc_op_clk: adc_op_clk{
93 compatible = "fixed-clock";
95 clock-frequency = <1000000>;
99 ns_sram: sram@00200000 {
100 compatible = "mmio-sram";
101 reg = <0x00200000 0x20000>;
105 compatible = "simple-bus";
106 #address-cells = <1>;
110 usb0: gadget@00300000 {
111 #address-cells = <1>;
113 compatible = "atmel,sama5d3-udc";
114 reg = <0x00300000 0x100000
116 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
117 clocks = <&udphs_clk>, <&utmi>;
118 clock-names = "pclk", "hclk";
123 atmel,fifo-size = <64>;
124 atmel,nb-banks = <1>;
129 atmel,fifo-size = <1024>;
130 atmel,nb-banks = <3>;
137 atmel,fifo-size = <1024>;
138 atmel,nb-banks = <3>;
145 atmel,fifo-size = <1024>;
146 atmel,nb-banks = <2>;
153 atmel,fifo-size = <1024>;
154 atmel,nb-banks = <2>;
161 atmel,fifo-size = <1024>;
162 atmel,nb-banks = <2>;
169 atmel,fifo-size = <1024>;
170 atmel,nb-banks = <2>;
177 atmel,fifo-size = <1024>;
178 atmel,nb-banks = <2>;
185 atmel,fifo-size = <1024>;
186 atmel,nb-banks = <2>;
192 atmel,fifo-size = <1024>;
193 atmel,nb-banks = <2>;
199 atmel,fifo-size = <1024>;
200 atmel,nb-banks = <2>;
206 atmel,fifo-size = <1024>;
207 atmel,nb-banks = <2>;
213 atmel,fifo-size = <1024>;
214 atmel,nb-banks = <2>;
220 atmel,fifo-size = <1024>;
221 atmel,nb-banks = <2>;
227 atmel,fifo-size = <1024>;
228 atmel,nb-banks = <2>;
234 atmel,fifo-size = <1024>;
235 atmel,nb-banks = <2>;
240 usb1: ohci@00400000 {
241 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
242 reg = <0x00400000 0x100000>;
243 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
244 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
245 clock-names = "ohci_clk", "hclk", "uhpck";
249 usb2: ehci@00500000 {
250 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
251 reg = <0x00500000 0x100000>;
252 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
253 clocks = <&utmi>, <&uhphs_clk>;
254 clock-names = "usb_clk", "ehci_clk";
258 L2: cache-controller@00a00000 {
259 compatible = "arm,pl310-cache";
260 reg = <0x00a00000 0x1000>;
261 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
266 sdmmc0: sdio-host@a0000000 {
267 compatible = "atmel,sama5d2-sdhci";
268 reg = <0xa0000000 0x300>;
269 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
270 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
271 clock-names = "hclock", "multclk", "baseclk";
275 sdmmc1: sdio-host@b0000000 {
276 compatible = "atmel,sama5d2-sdhci";
277 reg = <0xb0000000 0x300>;
278 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
279 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
280 clock-names = "hclock", "multclk", "baseclk";
285 compatible = "simple-bus";
286 #address-cells = <1>;
290 ramc0: ramc@f000c000 {
291 compatible = "atmel,sama5d3-ddramc";
292 reg = <0xf000c000 0x200>;
293 clocks = <&ddrck>, <&mpddr_clk>;
294 clock-names = "ddrck", "mpddr";
297 dma0: dma-controller@f0010000 {
298 compatible = "atmel,sama5d4-dma";
299 reg = <0xf0010000 0x1000>;
300 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
302 clocks = <&dma0_clk>;
303 clock-names = "dma_clk";
307 compatible = "atmel,sama5d2-pmc", "syscon";
308 reg = <0xf0014000 0x160>;
309 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
310 interrupt-controller;
311 #address-cells = <1>;
313 #interrupt-cells = <1>;
315 main_rc_osc: main_rc_osc {
316 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
318 interrupt-parent = <&pmc>;
319 interrupts = <AT91_PMC_MOSCRCS>;
320 clock-frequency = <12000000>;
321 clock-accuracy = <100000000>;
325 compatible = "atmel,at91rm9200-clk-main-osc";
327 interrupt-parent = <&pmc>;
328 interrupts = <AT91_PMC_MOSCS>;
329 clocks = <&main_xtal>;
333 compatible = "atmel,at91sam9x5-clk-main";
335 interrupt-parent = <&pmc>;
336 interrupts = <AT91_PMC_MOSCSELS>;
337 clocks = <&main_rc_osc &main_osc>;
341 compatible = "atmel,sama5d3-clk-pll";
343 interrupt-parent = <&pmc>;
344 interrupts = <AT91_PMC_LOCKA>;
347 atmel,clk-input-range = <12000000 12000000>;
348 #atmel,pll-clk-output-range-cells = <4>;
349 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
353 compatible = "atmel,at91sam9x5-clk-plldiv";
359 compatible = "atmel,at91sam9x5-clk-utmi";
361 interrupt-parent = <&pmc>;
362 interrupts = <AT91_PMC_LOCKU>;
367 compatible = "atmel,at91sam9x5-clk-master";
369 interrupt-parent = <&pmc>;
370 interrupts = <AT91_PMC_MCKRDY>;
371 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
372 atmel,clk-output-range = <124000000 166000000>;
373 atmel,clk-divisors = <1 2 4 3>;
378 compatible = "atmel,sama5d4-clk-h32mx";
383 compatible = "atmel,at91sam9x5-clk-usb";
385 clocks = <&plladiv>, <&utmi>;
389 compatible = "atmel,at91sam9x5-clk-programmable";
390 #address-cells = <1>;
392 interrupt-parent = <&pmc>;
393 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
398 interrupts = <AT91_PMC_PCKRDY(0)>;
404 interrupts = <AT91_PMC_PCKRDY(1)>;
410 interrupts = <AT91_PMC_PCKRDY(2)>;
415 compatible = "atmel,at91rm9200-clk-system";
416 #address-cells = <1>;
469 compatible = "atmel,at91sam9x5-clk-peripheral";
470 #address-cells = <1>;
474 macb0_clk: macb0_clk {
477 atmel,clk-output-range = <0 83000000>;
483 atmel,clk-output-range = <0 83000000>;
486 matrix1_clk: matrix1_clk {
499 atmel,clk-output-range = <0 83000000>;
505 atmel,clk-output-range = <0 83000000>;
511 atmel,clk-output-range = <0 83000000>;
517 atmel,clk-output-range = <0 83000000>;
523 atmel,clk-output-range = <0 83000000>;
529 atmel,clk-output-range = <0 83000000>;
532 uart0_clk: uart0_clk {
535 atmel,clk-output-range = <0 83000000>;
538 uart1_clk: uart1_clk {
541 atmel,clk-output-range = <0 83000000>;
544 uart2_clk: uart2_clk {
547 atmel,clk-output-range = <0 83000000>;
550 uart3_clk: uart3_clk {
553 atmel,clk-output-range = <0 83000000>;
556 uart4_clk: uart4_clk {
559 atmel,clk-output-range = <0 83000000>;
565 atmel,clk-output-range = <0 83000000>;
571 atmel,clk-output-range = <0 83000000>;
577 atmel,clk-output-range = <0 83000000>;
583 atmel,clk-output-range = <0 83000000>;
589 atmel,clk-output-range = <0 83000000>;
595 atmel,clk-output-range = <0 83000000>;
601 atmel,clk-output-range = <0 83000000>;
607 atmel,clk-output-range = <0 83000000>;
610 uhphs_clk: uhphs_clk {
613 atmel,clk-output-range = <0 83000000>;
616 udphs_clk: udphs_clk {
619 atmel,clk-output-range = <0 83000000>;
625 atmel,clk-output-range = <0 83000000>;
631 atmel,clk-output-range = <0 83000000>;
637 atmel,clk-output-range = <0 83000000>;
640 pdmic_clk: pdmic_clk {
643 atmel,clk-output-range = <0 83000000>;
649 atmel,clk-output-range = <0 83000000>;
655 atmel,clk-output-range = <0 83000000>;
658 classd_clk: classd_clk {
661 atmel,clk-output-range = <0 83000000>;
666 compatible = "atmel,at91sam9x5-clk-peripheral";
667 #address-cells = <1>;
696 mpddr_clk: mpddr_clk {
701 matrix0_clk: matrix0_clk {
706 sdmmc0_hclk: sdmmc0_hclk {
711 sdmmc1_hclk: sdmmc1_hclk {
726 qspi0_clk: qspi0_clk {
731 qspi1_clk: qspi1_clk {
738 compatible = "atmel,sama5d2-clk-generated";
739 #address-cells = <1>;
741 interrupt-parent = <&pmc>;
742 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
744 sdmmc0_gclk: sdmmc0_gclk {
749 sdmmc1_gclk: sdmmc1_gclk {
754 tcb0_gclk: tcb0_gclk {
757 atmel,clk-output-range = <0 83000000>;
760 tcb1_gclk: tcb1_gclk {
763 atmel,clk-output-range = <0 83000000>;
769 atmel,clk-output-range = <0 83000000>;
772 pdmic_gclk: pdmic_gclk {
777 i2s0_gclk: i2s0_gclk {
782 i2s1_gclk: i2s1_gclk {
790 compatible = "atmel,at91sam9g46-sha";
791 reg = <0xf0028000 0x100>;
792 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
794 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
795 AT91_XDMAC_DT_PERID(30))>;
798 clock-names = "sha_clk";
803 compatible = "atmel,at91sam9g46-aes";
804 reg = <0xf002c000 0x100>;
805 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
807 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
808 AT91_XDMAC_DT_PERID(26))>,
810 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
811 AT91_XDMAC_DT_PERID(27))>;
812 dma-names = "tx", "rx";
814 clock-names = "aes_clk";
819 compatible = "atmel,at91rm9200-spi";
820 reg = <0xf8000000 0x100>;
821 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
823 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
824 AT91_XDMAC_DT_PERID(6))>,
826 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
827 AT91_XDMAC_DT_PERID(7))>;
828 dma-names = "tx", "rx";
829 clocks = <&spi0_clk>;
830 clock-names = "spi_clk";
831 atmel,fifo-size = <16>;
832 #address-cells = <1>;
837 macb0: ethernet@f8008000 {
838 compatible = "atmel,sama5d2-gem";
839 reg = <0xf8008000 0x1000>;
840 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
841 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
842 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
843 #address-cells = <1>;
845 clocks = <&macb0_clk>, <&macb0_clk>;
846 clock-names = "hclk", "pclk";
850 tcb0: timer@f800c000 {
851 compatible = "atmel,at91sam9x5-tcb";
852 reg = <0xf800c000 0x100>;
853 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
854 clocks = <&tcb0_clk>, <&clk32k>;
855 clock-names = "t0_clk", "slow_clk";
858 tcb1: timer@f8010000 {
859 compatible = "atmel,at91sam9x5-tcb";
860 reg = <0xf8010000 0x100>;
861 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
862 clocks = <&tcb1_clk>, <&clk32k>;
863 clock-names = "t0_clk", "slow_clk";
866 pdmic: pdmic@f8018000 {
867 compatible = "atmel,sama5d2-pdmic";
868 reg = <0xf8018000 0x124>;
869 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
871 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
872 | AT91_XDMAC_DT_PERID(50))>;
874 clocks = <&pdmic_clk>, <&pdmic_gclk>;
875 clock-names = "pclk", "gclk";
879 uart0: serial@f801c000 {
880 compatible = "atmel,at91sam9260-usart";
881 reg = <0xf801c000 0x100>;
882 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
883 clocks = <&uart0_clk>;
884 clock-names = "usart";
888 uart1: serial@f8020000 {
889 compatible = "atmel,at91sam9260-usart";
890 reg = <0xf8020000 0x100>;
891 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
892 clocks = <&uart1_clk>;
893 clock-names = "usart";
897 uart2: serial@f8024000 {
898 compatible = "atmel,at91sam9260-usart";
899 reg = <0xf8024000 0x100>;
900 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
901 clocks = <&uart2_clk>;
902 clock-names = "usart";
907 compatible = "atmel,sama5d2-i2c";
908 reg = <0xf8028000 0x100>;
909 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
911 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
912 AT91_XDMAC_DT_PERID(0))>,
914 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
915 AT91_XDMAC_DT_PERID(1))>;
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
919 clocks = <&twi0_clk>;
923 flx0: flexcom@f8034000 {
924 compatible = "atmel,sama5d2-flexcom";
925 reg = <0xf8034000 0x200>;
926 clocks = <&flx0_clk>;
927 #address-cells = <1>;
929 ranges = <0x0 0xf8034000 0x800>;
933 flx1: flexcom@f8038000 {
934 compatible = "atmel,sama5d2-flexcom";
935 reg = <0xf8038000 0x200>;
936 clocks = <&flx1_clk>;
937 #address-cells = <1>;
939 ranges = <0x0 0xf8038000 0x800>;
944 compatible = "atmel,sama5d3-rstc";
945 reg = <0xf8048000 0x10>;
949 pit: timer@f8048030 {
950 compatible = "atmel,at91sam9260-pit";
951 reg = <0xf8048030 0x10>;
952 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
957 compatible = "atmel,sama5d4-wdt";
958 reg = <0xf8048040 0x10>;
959 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
964 compatible = "atmel,at91sam9x5-sckc";
965 reg = <0xf8048050 0x4>;
967 slow_rc_osc: slow_rc_osc {
968 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
970 clock-frequency = <32768>;
971 clock-accuracy = <250000000>;
972 atmel,startup-time-usec = <75>;
976 compatible = "atmel,at91sam9x5-clk-slow-osc";
978 clocks = <&slow_xtal>;
979 atmel,startup-time-usec = <1200000>;
983 compatible = "atmel,at91sam9x5-clk-slow";
985 clocks = <&slow_rc_osc &slow_osc>;
990 compatible = "atmel,at91rm9200-rtc";
991 reg = <0xf80480b0 0x30>;
992 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
997 compatible = "atmel,at91rm9200-spi";
998 reg = <0xfc000000 0x100>;
999 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1001 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1002 AT91_XDMAC_DT_PERID(8))>,
1004 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1005 AT91_XDMAC_DT_PERID(9))>;
1006 dma-names = "tx", "rx";
1007 clocks = <&spi1_clk>;
1008 clock-names = "spi_clk";
1009 atmel,fifo-size = <16>;
1010 #address-cells = <1>;
1012 status = "disabled";
1015 uart3: serial@fc008000 {
1016 compatible = "atmel,at91sam9260-usart";
1017 reg = <0xfc008000 0x100>;
1018 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1019 clocks = <&uart3_clk>;
1020 clock-names = "usart";
1021 status = "disabled";
1024 uart4: serial@fc00c000 {
1025 compatible = "atmel,at91sam9260-usart";
1026 reg = <0xfc00c000 0x100>;
1027 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1028 clocks = <&uart4_clk>;
1029 clock-names = "usart";
1030 status = "disabled";
1033 flx2: flexcom@fc010000 {
1034 compatible = "atmel,sama5d2-flexcom";
1035 reg = <0xfc010000 0x200>;
1036 clocks = <&flx2_clk>;
1037 #address-cells = <1>;
1039 ranges = <0x0 0xfc010000 0x800>;
1040 status = "disabled";
1043 flx3: flexcom@fc014000 {
1044 compatible = "atmel,sama5d2-flexcom";
1045 reg = <0xfc014000 0x200>;
1046 clocks = <&flx3_clk>;
1047 #address-cells = <1>;
1049 ranges = <0x0 0xfc014000 0x800>;
1050 status = "disabled";
1053 flx4: flexcom@fc018000 {
1054 compatible = "atmel,sama5d2-flexcom";
1055 reg = <0xfc018000 0x200>;
1056 clocks = <&flx4_clk>;
1057 #address-cells = <1>;
1059 ranges = <0x0 0xfc018000 0x800>;
1060 status = "disabled";
1063 aic: interrupt-controller@fc020000 {
1064 #interrupt-cells = <3>;
1065 compatible = "atmel,sama5d2-aic";
1066 interrupt-controller;
1067 reg = <0xfc020000 0x200>;
1068 atmel,external-irqs = <49>;
1071 i2c1: i2c@fc028000 {
1072 compatible = "atmel,sama5d2-i2c";
1073 reg = <0xfc028000 0x100>;
1074 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1076 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1077 AT91_XDMAC_DT_PERID(2))>,
1079 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1080 AT91_XDMAC_DT_PERID(3))>;
1081 dma-names = "tx", "rx";
1082 #address-cells = <1>;
1084 clocks = <&twi1_clk>;
1085 status = "disabled";
1088 pioA: pinctrl@fc038000 {
1089 compatible = "atmel,sama5d2-pinctrl";
1090 reg = <0xfc038000 0x600>;
1091 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1092 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1093 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1094 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1095 interrupt-controller;
1096 #interrupt-cells = <2>;
1099 clocks = <&pioA_clk>;
1103 compatible = "atmel,at91sam9g46-tdes";
1104 reg = <0xfc044000 0x100>;
1105 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1107 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1108 AT91_XDMAC_DT_PERID(28))>,
1110 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1111 AT91_XDMAC_DT_PERID(29))>;
1112 dma-names = "tx", "rx";
1113 clocks = <&tdes_clk>;
1114 clock-names = "tdes_clk";