2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
69 compatible = "arm,cortex-a5";
71 next-level-cache = <&L2>;
76 reg = <0x20000000 0x20000000>;
80 slow_xtal: slow_xtal {
81 compatible = "fixed-clock";
83 clock-frequency = <0>;
86 main_xtal: main_xtal {
87 compatible = "fixed-clock";
89 clock-frequency = <0>;
93 ns_sram: sram@00200000 {
94 compatible = "mmio-sram";
95 reg = <0x00200000 0x20000>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 usb0: gadget@00300000 {
105 #address-cells = <1>;
107 compatible = "atmel,sama5d3-udc";
108 reg = <0x00300000 0x100000
110 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
111 clocks = <&udphs_clk>, <&utmi>;
112 clock-names = "pclk", "hclk";
117 atmel,fifo-size = <64>;
118 atmel,nb-banks = <1>;
123 atmel,fifo-size = <1024>;
124 atmel,nb-banks = <3>;
131 atmel,fifo-size = <1024>;
132 atmel,nb-banks = <3>;
139 atmel,fifo-size = <1024>;
140 atmel,nb-banks = <2>;
147 atmel,fifo-size = <1024>;
148 atmel,nb-banks = <2>;
155 atmel,fifo-size = <1024>;
156 atmel,nb-banks = <2>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <2>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <2>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
234 usb1: ohci@00400000 {
235 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
236 reg = <0x00400000 0x100000>;
237 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
238 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
239 clock-names = "ohci_clk", "hclk", "uhpck";
243 usb2: ehci@00500000 {
244 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
245 reg = <0x00500000 0x100000>;
246 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
247 clocks = <&utmi>, <&uhphs_clk>;
248 clock-names = "usb_clk", "ehci_clk";
252 L2: cache-controller@00a00000 {
253 compatible = "arm,pl310-cache";
254 reg = <0x00a00000 0x1000>;
255 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
260 nand0: nand@80000000 {
261 compatible = "atmel,sama5d2-nand";
262 #address-cells = <1>;
265 reg = < /* EBI CS3 */
266 0x80000000 0x08000000
268 0xf8014070 0x00000490
269 /* SMC PMECC Error Location regs */
270 0xf8014500 0x00000200
271 /* ROM Galois tables */
272 0x00040000 0x00018000
274 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
275 atmel,nand-addr-offset = <21>;
276 atmel,nand-cmd-offset = <22>;
279 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
283 compatible = "atmel,sama5d4-nfc";
284 #address-cells = <1>;
286 reg = < /* NFC Command Registers */
287 0xc0000000 0x08000000
289 0xf8014000 0x00000070
291 0x00100000 0x00100000
293 clocks = <&hsmc_clk>;
298 sdmmc0: sdio-host@a0000000 {
299 compatible = "atmel,sama5d2-sdhci";
300 reg = <0xa0000000 0x300>;
301 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
302 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
303 clock-names = "hclock", "multclk", "baseclk";
307 sdmmc1: sdio-host@b0000000 {
308 compatible = "atmel,sama5d2-sdhci";
309 reg = <0xb0000000 0x300>;
310 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
311 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
312 clock-names = "hclock", "multclk", "baseclk";
317 compatible = "simple-bus";
318 #address-cells = <1>;
322 ramc0: ramc@f000c000 {
323 compatible = "atmel,sama5d3-ddramc";
324 reg = <0xf000c000 0x200>;
325 clocks = <&ddrck>, <&mpddr_clk>;
326 clock-names = "ddrck", "mpddr";
329 dma0: dma-controller@f0010000 {
330 compatible = "atmel,sama5d4-dma";
331 reg = <0xf0010000 0x1000>;
332 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
334 clocks = <&dma0_clk>;
335 clock-names = "dma_clk";
339 compatible = "atmel,sama5d2-pmc", "syscon";
340 reg = <0xf0014000 0x160>;
341 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
342 interrupt-controller;
343 #address-cells = <1>;
345 #interrupt-cells = <1>;
347 main_rc_osc: main_rc_osc {
348 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
350 interrupt-parent = <&pmc>;
351 interrupts = <AT91_PMC_MOSCRCS>;
352 clock-frequency = <12000000>;
353 clock-accuracy = <100000000>;
357 compatible = "atmel,at91rm9200-clk-main-osc";
359 interrupt-parent = <&pmc>;
360 interrupts = <AT91_PMC_MOSCS>;
361 clocks = <&main_xtal>;
365 compatible = "atmel,at91sam9x5-clk-main";
367 interrupt-parent = <&pmc>;
368 interrupts = <AT91_PMC_MOSCSELS>;
369 clocks = <&main_rc_osc &main_osc>;
373 compatible = "atmel,sama5d3-clk-pll";
375 interrupt-parent = <&pmc>;
376 interrupts = <AT91_PMC_LOCKA>;
379 atmel,clk-input-range = <12000000 12000000>;
380 #atmel,pll-clk-output-range-cells = <4>;
381 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
385 compatible = "atmel,at91sam9x5-clk-plldiv";
391 compatible = "atmel,at91sam9x5-clk-utmi";
393 interrupt-parent = <&pmc>;
394 interrupts = <AT91_PMC_LOCKU>;
399 compatible = "atmel,at91sam9x5-clk-master";
401 interrupt-parent = <&pmc>;
402 interrupts = <AT91_PMC_MCKRDY>;
403 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
404 atmel,clk-output-range = <124000000 166000000>;
405 atmel,clk-divisors = <1 2 4 3>;
410 compatible = "atmel,sama5d4-clk-h32mx";
415 compatible = "atmel,at91sam9x5-clk-usb";
417 clocks = <&plladiv>, <&utmi>;
421 compatible = "atmel,at91sam9x5-clk-programmable";
422 #address-cells = <1>;
424 interrupt-parent = <&pmc>;
425 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
430 interrupts = <AT91_PMC_PCKRDY(0)>;
436 interrupts = <AT91_PMC_PCKRDY(1)>;
442 interrupts = <AT91_PMC_PCKRDY(2)>;
447 compatible = "atmel,at91rm9200-clk-system";
448 #address-cells = <1>;
501 compatible = "atmel,at91sam9x5-clk-peripheral";
502 #address-cells = <1>;
506 macb0_clk: macb0_clk {
509 atmel,clk-output-range = <0 83000000>;
515 atmel,clk-output-range = <0 83000000>;
518 matrix1_clk: matrix1_clk {
531 atmel,clk-output-range = <0 83000000>;
537 atmel,clk-output-range = <0 83000000>;
543 atmel,clk-output-range = <0 83000000>;
549 atmel,clk-output-range = <0 83000000>;
555 atmel,clk-output-range = <0 83000000>;
561 atmel,clk-output-range = <0 83000000>;
564 uart0_clk: uart0_clk {
567 atmel,clk-output-range = <0 83000000>;
570 uart1_clk: uart1_clk {
573 atmel,clk-output-range = <0 83000000>;
576 uart2_clk: uart2_clk {
579 atmel,clk-output-range = <0 83000000>;
582 uart3_clk: uart3_clk {
585 atmel,clk-output-range = <0 83000000>;
588 uart4_clk: uart4_clk {
591 atmel,clk-output-range = <0 83000000>;
597 atmel,clk-output-range = <0 83000000>;
603 atmel,clk-output-range = <0 83000000>;
609 atmel,clk-output-range = <0 83000000>;
615 atmel,clk-output-range = <0 83000000>;
621 atmel,clk-output-range = <0 83000000>;
627 atmel,clk-output-range = <0 83000000>;
633 atmel,clk-output-range = <0 83000000>;
639 atmel,clk-output-range = <0 83000000>;
642 uhphs_clk: uhphs_clk {
645 atmel,clk-output-range = <0 83000000>;
648 udphs_clk: udphs_clk {
651 atmel,clk-output-range = <0 83000000>;
657 atmel,clk-output-range = <0 83000000>;
663 atmel,clk-output-range = <0 83000000>;
669 atmel,clk-output-range = <0 83000000>;
672 pdmic_clk: pdmic_clk {
675 atmel,clk-output-range = <0 83000000>;
681 atmel,clk-output-range = <0 83000000>;
687 atmel,clk-output-range = <0 83000000>;
690 classd_clk: classd_clk {
693 atmel,clk-output-range = <0 83000000>;
698 compatible = "atmel,at91sam9x5-clk-peripheral";
699 #address-cells = <1>;
728 mpddr_clk: mpddr_clk {
733 matrix0_clk: matrix0_clk {
738 sdmmc0_hclk: sdmmc0_hclk {
743 sdmmc1_hclk: sdmmc1_hclk {
758 qspi0_clk: qspi0_clk {
763 qspi1_clk: qspi1_clk {
770 compatible = "atmel,sama5d2-clk-generated";
771 #address-cells = <1>;
773 interrupt-parent = <&pmc>;
774 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
776 sdmmc0_gclk: sdmmc0_gclk {
781 sdmmc1_gclk: sdmmc1_gclk {
786 tcb0_gclk: tcb0_gclk {
789 atmel,clk-output-range = <0 83000000>;
792 tcb1_gclk: tcb1_gclk {
795 atmel,clk-output-range = <0 83000000>;
801 atmel,clk-output-range = <0 83000000>;
804 pdmic_gclk: pdmic_gclk {
809 i2s0_gclk: i2s0_gclk {
814 i2s1_gclk: i2s1_gclk {
822 compatible = "atmel,at91sam9g46-sha";
823 reg = <0xf0028000 0x100>;
824 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
826 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
827 AT91_XDMAC_DT_PERID(30))>;
830 clock-names = "sha_clk";
835 compatible = "atmel,at91sam9g46-aes";
836 reg = <0xf002c000 0x100>;
837 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
839 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
840 AT91_XDMAC_DT_PERID(26))>,
842 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
843 AT91_XDMAC_DT_PERID(27))>;
844 dma-names = "tx", "rx";
846 clock-names = "aes_clk";
851 compatible = "atmel,at91rm9200-spi";
852 reg = <0xf8000000 0x100>;
853 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
855 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
856 AT91_XDMAC_DT_PERID(6))>,
858 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
859 AT91_XDMAC_DT_PERID(7))>;
860 dma-names = "tx", "rx";
861 clocks = <&spi0_clk>;
862 clock-names = "spi_clk";
863 atmel,fifo-size = <16>;
864 #address-cells = <1>;
869 macb0: ethernet@f8008000 {
870 compatible = "atmel,sama5d2-gem";
871 reg = <0xf8008000 0x1000>;
872 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
873 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
874 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
875 #address-cells = <1>;
877 clocks = <&macb0_clk>, <&macb0_clk>;
878 clock-names = "hclk", "pclk";
882 tcb0: timer@f800c000 {
883 compatible = "atmel,at91sam9x5-tcb";
884 reg = <0xf800c000 0x100>;
885 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
886 clocks = <&tcb0_clk>, <&clk32k>;
887 clock-names = "t0_clk", "slow_clk";
890 tcb1: timer@f8010000 {
891 compatible = "atmel,at91sam9x5-tcb";
892 reg = <0xf8010000 0x100>;
893 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
894 clocks = <&tcb1_clk>, <&clk32k>;
895 clock-names = "t0_clk", "slow_clk";
898 pdmic: pdmic@f8018000 {
899 compatible = "atmel,sama5d2-pdmic";
900 reg = <0xf8018000 0x124>;
901 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
903 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
904 | AT91_XDMAC_DT_PERID(50))>;
906 clocks = <&pdmic_clk>, <&pdmic_gclk>;
907 clock-names = "pclk", "gclk";
911 uart0: serial@f801c000 {
912 compatible = "atmel,at91sam9260-usart";
913 reg = <0xf801c000 0x100>;
914 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
916 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
917 AT91_XDMAC_DT_PERID(35))>,
919 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
920 AT91_XDMAC_DT_PERID(36))>;
921 dma-names = "tx", "rx";
922 clocks = <&uart0_clk>;
923 clock-names = "usart";
927 uart1: serial@f8020000 {
928 compatible = "atmel,at91sam9260-usart";
929 reg = <0xf8020000 0x100>;
930 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
932 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
933 AT91_XDMAC_DT_PERID(37))>,
935 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
936 AT91_XDMAC_DT_PERID(38))>;
937 dma-names = "tx", "rx";
938 clocks = <&uart1_clk>;
939 clock-names = "usart";
943 uart2: serial@f8024000 {
944 compatible = "atmel,at91sam9260-usart";
945 reg = <0xf8024000 0x100>;
946 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
948 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
949 AT91_XDMAC_DT_PERID(39))>,
951 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
952 AT91_XDMAC_DT_PERID(40))>;
953 dma-names = "tx", "rx";
954 clocks = <&uart2_clk>;
955 clock-names = "usart";
960 compatible = "atmel,sama5d2-i2c";
961 reg = <0xf8028000 0x100>;
962 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
964 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
965 AT91_XDMAC_DT_PERID(0))>,
967 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
968 AT91_XDMAC_DT_PERID(1))>;
969 dma-names = "tx", "rx";
970 #address-cells = <1>;
972 clocks = <&twi0_clk>;
976 flx0: flexcom@f8034000 {
977 compatible = "atmel,sama5d2-flexcom";
978 reg = <0xf8034000 0x200>;
979 clocks = <&flx0_clk>;
980 #address-cells = <1>;
982 ranges = <0x0 0xf8034000 0x800>;
986 flx1: flexcom@f8038000 {
987 compatible = "atmel,sama5d2-flexcom";
988 reg = <0xf8038000 0x200>;
989 clocks = <&flx1_clk>;
990 #address-cells = <1>;
992 ranges = <0x0 0xf8038000 0x800>;
997 compatible = "atmel,sama5d3-rstc";
998 reg = <0xf8048000 0x10>;
1002 pit: timer@f8048030 {
1003 compatible = "atmel,at91sam9260-pit";
1004 reg = <0xf8048030 0x10>;
1005 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1010 compatible = "atmel,sama5d4-wdt";
1011 reg = <0xf8048040 0x10>;
1012 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1013 status = "disabled";
1017 compatible = "atmel,at91sam9x5-sckc";
1018 reg = <0xf8048050 0x4>;
1020 slow_rc_osc: slow_rc_osc {
1021 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1023 clock-frequency = <32768>;
1024 clock-accuracy = <250000000>;
1025 atmel,startup-time-usec = <75>;
1028 slow_osc: slow_osc {
1029 compatible = "atmel,at91sam9x5-clk-slow-osc";
1031 clocks = <&slow_xtal>;
1032 atmel,startup-time-usec = <1200000>;
1036 compatible = "atmel,at91sam9x5-clk-slow";
1038 clocks = <&slow_rc_osc &slow_osc>;
1043 compatible = "atmel,at91rm9200-rtc";
1044 reg = <0xf80480b0 0x30>;
1045 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1049 spi1: spi@fc000000 {
1050 compatible = "atmel,at91rm9200-spi";
1051 reg = <0xfc000000 0x100>;
1052 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1054 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1055 AT91_XDMAC_DT_PERID(8))>,
1057 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1058 AT91_XDMAC_DT_PERID(9))>;
1059 dma-names = "tx", "rx";
1060 clocks = <&spi1_clk>;
1061 clock-names = "spi_clk";
1062 atmel,fifo-size = <16>;
1063 #address-cells = <1>;
1065 status = "disabled";
1068 uart3: serial@fc008000 {
1069 compatible = "atmel,at91sam9260-usart";
1070 reg = <0xfc008000 0x100>;
1071 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1073 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1074 AT91_XDMAC_DT_PERID(41))>,
1076 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1077 AT91_XDMAC_DT_PERID(42))>;
1078 dma-names = "tx", "rx";
1079 clocks = <&uart3_clk>;
1080 clock-names = "usart";
1081 status = "disabled";
1084 uart4: serial@fc00c000 {
1085 compatible = "atmel,at91sam9260-usart";
1086 reg = <0xfc00c000 0x100>;
1088 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1089 AT91_XDMAC_DT_PERID(43))>,
1091 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1092 AT91_XDMAC_DT_PERID(44))>;
1093 dma-names = "tx", "rx";
1094 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1095 clocks = <&uart4_clk>;
1096 clock-names = "usart";
1097 status = "disabled";
1100 flx2: flexcom@fc010000 {
1101 compatible = "atmel,sama5d2-flexcom";
1102 reg = <0xfc010000 0x200>;
1103 clocks = <&flx2_clk>;
1104 #address-cells = <1>;
1106 ranges = <0x0 0xfc010000 0x800>;
1107 status = "disabled";
1110 flx3: flexcom@fc014000 {
1111 compatible = "atmel,sama5d2-flexcom";
1112 reg = <0xfc014000 0x200>;
1113 clocks = <&flx3_clk>;
1114 #address-cells = <1>;
1116 ranges = <0x0 0xfc014000 0x800>;
1117 status = "disabled";
1120 flx4: flexcom@fc018000 {
1121 compatible = "atmel,sama5d2-flexcom";
1122 reg = <0xfc018000 0x200>;
1123 clocks = <&flx4_clk>;
1124 #address-cells = <1>;
1126 ranges = <0x0 0xfc018000 0x800>;
1127 status = "disabled";
1130 aic: interrupt-controller@fc020000 {
1131 #interrupt-cells = <3>;
1132 compatible = "atmel,sama5d2-aic";
1133 interrupt-controller;
1134 reg = <0xfc020000 0x200>;
1135 atmel,external-irqs = <49>;
1138 i2c1: i2c@fc028000 {
1139 compatible = "atmel,sama5d2-i2c";
1140 reg = <0xfc028000 0x100>;
1141 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1143 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1144 AT91_XDMAC_DT_PERID(2))>,
1146 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1147 AT91_XDMAC_DT_PERID(3))>;
1148 dma-names = "tx", "rx";
1149 #address-cells = <1>;
1151 clocks = <&twi1_clk>;
1152 status = "disabled";
1156 compatible = "atmel,sama5d2-adc";
1157 reg = <0xfc030000 0x100>;
1158 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1159 clocks = <&adc_clk>;
1160 clock-names = "adc_clk";
1161 atmel,min-sample-rate-hz = <200000>;
1162 atmel,max-sample-rate-hz = <20000000>;
1163 atmel,startup-time-ms = <4>;
1164 status = "disabled";
1167 pioA: pinctrl@fc038000 {
1168 compatible = "atmel,sama5d2-pinctrl";
1169 reg = <0xfc038000 0x600>;
1170 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1171 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1172 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1173 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1174 interrupt-controller;
1175 #interrupt-cells = <2>;
1178 clocks = <&pioA_clk>;
1182 compatible = "atmel,at91sam9g46-tdes";
1183 reg = <0xfc044000 0x100>;
1184 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1186 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1187 AT91_XDMAC_DT_PERID(28))>,
1189 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1190 AT91_XDMAC_DT_PERID(29))>;
1191 dma-names = "tx", "rx";
1192 clocks = <&tdes_clk>;
1193 clock-names = "tdes_clk";