arch/arm/boot/dts/sama5d2.dtsi

   1 /*
   2  * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
   3  *
   4  *  Copyright (C) 2015 Atmel,
   5  *                2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "skeleton.dtsi"
  47 #include <dt-bindings/dma/at91.h>
  48 #include <dt-bindings/interrupt-controller/irq.h>
  49 #include <dt-bindings/clock/at91.h>
  50
  51 / {
  52         model = "Atmel SAMA5D2 family SoC";
  53         compatible = "atmel,sama5d2";
  54         interrupt-parent = <&aic>;
  55
  56         aliases {
  57                 serial0 = &uart1;
  58                 serial1 = &uart3;
  59                 tcb0 = &tcb0;
  60                 tcb1 = &tcb1;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu@0 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a5";
  70                         reg = <0>;
  71                         next-level-cache = <&L2>;
  72                 };
  73         };
  74
  75         memory {
  76                 reg = <0x20000000 0x20000000>;
  77         };
  78
  79         clocks {
  80                 slow_xtal: slow_xtal {
  81                         compatible = "fixed-clock";
  82                         #clock-cells = <0>;
  83                         clock-frequency = <0>;
  84                 };
  85
  86                 main_xtal: main_xtal {
  87                         compatible = "fixed-clock";
  88                         #clock-cells = <0>;
  89                         clock-frequency = <0>;
  90                 };
  91
  92                 adc_op_clk: adc_op_clk{
  93                         compatible = "fixed-clock";
  94                         #clock-cells = <0>;
  95                         clock-frequency = <1000000>;
  96                 };
  97         };
  98
  99         ns_sram: sram@00200000 {
 100                 compatible = "mmio-sram";
 101                 reg = <0x00200000 0x20000>;
 102         };
 103
 104         ahb {
 105                 compatible = "simple-bus";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 usb0: gadget@00300000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         compatible = "atmel,sama5d3-udc";
 114                         reg = <0x00300000 0x100000
 115                                0xfc02c000 0x400>;
 116                         interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
 117                         clocks = <&udphs_clk>, <&utmi>;
 118                         clock-names = "pclk", "hclk";
 119                         status = "disabled";
 120
 121                         ep0 {
 122                                 reg = <0>;
 123                                 atmel,fifo-size = <64>;
 124                                 atmel,nb-banks = <1>;
 125                         };
 126
 127                         ep1 {
 128                                 reg = <1>;
 129                                 atmel,fifo-size = <1024>;
 130                                 atmel,nb-banks = <3>;
 131                                 atmel,can-dma;
 132                                 atmel,can-isoc;
 133                         };
 134
 135                         ep2 {
 136                                 reg = <2>;
 137                                 atmel,fifo-size = <1024>;
 138                                 atmel,nb-banks = <3>;
 139                                 atmel,can-dma;
 140                                 atmel,can-isoc;
 141                         };
 142
 143                         ep3 {
 144                                 reg = <3>;
 145                                 atmel,fifo-size = <1024>;
 146                                 atmel,nb-banks = <2>;
 147                                 atmel,can-dma;
 148                                 atmel,can-isoc;
 149                         };
 150
 151                         ep4 {
 152                                 reg = <4>;
 153                                 atmel,fifo-size = <1024>;
 154                                 atmel,nb-banks = <2>;
 155                                 atmel,can-dma;
 156                                 atmel,can-isoc;
 157                         };
 158
 159                         ep5 {
 160                                 reg = <5>;
 161                                 atmel,fifo-size = <1024>;
 162                                 atmel,nb-banks = <2>;
 163                                 atmel,can-dma;
 164                                 atmel,can-isoc;
 165                         };
 166
 167                         ep6 {
 168                                 reg = <6>;
 169                                 atmel,fifo-size = <1024>;
 170                                 atmel,nb-banks = <2>;
 171                                 atmel,can-dma;
 172                                 atmel,can-isoc;
 173                         };
 174
 175                         ep7 {
 176                                 reg = <7>;
 177                                 atmel,fifo-size = <1024>;
 178                                 atmel,nb-banks = <2>;
 179                                 atmel,can-dma;
 180                                 atmel,can-isoc;
 181                         };
 182
 183                         ep8 {
 184                                 reg = <8>;
 185                                 atmel,fifo-size = <1024>;
 186                                 atmel,nb-banks = <2>;
 187                                 atmel,can-isoc;
 188                         };
 189
 190                         ep9 {
 191                                 reg = <9>;
 192                                 atmel,fifo-size = <1024>;
 193                                 atmel,nb-banks = <2>;
 194                                 atmel,can-isoc;
 195                         };
 196
 197                         ep10 {
 198                                 reg = <10>;
 199                                 atmel,fifo-size = <1024>;
 200                                 atmel,nb-banks = <2>;
 201                                 atmel,can-isoc;
 202                         };
 203
 204                         ep11 {
 205                                 reg = <11>;
 206                                 atmel,fifo-size = <1024>;
 207                                 atmel,nb-banks = <2>;
 208                                 atmel,can-isoc;
 209                         };
 210
 211                         ep12 {
 212                                 reg = <12>;
 213                                 atmel,fifo-size = <1024>;
 214                                 atmel,nb-banks = <2>;
 215                                 atmel,can-isoc;
 216                         };
 217
 218                         ep13 {
 219                                 reg = <13>;
 220                                 atmel,fifo-size = <1024>;
 221                                 atmel,nb-banks = <2>;
 222                                 atmel,can-isoc;
 223                         };
 224
 225                         ep14 {
 226                                 reg = <14>;
 227                                 atmel,fifo-size = <1024>;
 228                                 atmel,nb-banks = <2>;
 229                                 atmel,can-isoc;
 230                         };
 231
 232                         ep15 {
 233                                 reg = <15>;
 234                                 atmel,fifo-size = <1024>;
 235                                 atmel,nb-banks = <2>;
 236                                 atmel,can-isoc;
 237                         };
 238                 };
 239
 240                 usb1: ohci@00400000 {
 241                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 242                         reg = <0x00400000 0x100000>;
 243                         interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
 244                         clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
 245                         clock-names = "ohci_clk", "hclk", "uhpck";
 246                         status = "disabled";
 247                 };
 248
 249                 usb2: ehci@00500000 {
 250                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 251                         reg = <0x00500000 0x100000>;
 252                         interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
 253                         clocks = <&utmi>, <&uhphs_clk>;
 254                         clock-names = "usb_clk", "ehci_clk";
 255                         status = "disabled";
 256                 };
 257
 258                 L2: cache-controller@00a00000 {
 259                         compatible = "arm,pl310-cache";
 260                         reg = <0x00a00000 0x1000>;
 261                         interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
 262                         cache-unified;
 263                         cache-level = <2>;
 264                 };
 265
 266                 nand0: nand@80000000 {
 267                         compatible = "atmel,sama5d2-nand";
 268                         #address-cells = <1>;
 269                         #size-cells = <1>;
 270                         ranges;
 271                         reg = < /* EBI CS3 */
 272                                 0x80000000 0x08000000
 273                                 /* SMC PMECC regs */
 274                                 0xf8014070 0x00000490
 275                                 /* SMC PMECC Error Location regs */
 276                                 0xf8014500 0x00000200
 277                                 /* ROM Galois tables */
 278                                 0x00040000 0x00018000
 279                                 >;
 280                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
 281                         atmel,nand-addr-offset = <21>;
 282                         atmel,nand-cmd-offset = <22>;
 283                         atmel,nand-has-dma;
 284                         atmel,has-pmecc;
 285                         atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
 286                         status = "disabled";
 287
 288                         nfc@c0000000 {
 289                                 compatible = "atmel,sama5d4-nfc";
 290                                 #address-cells = <1>;
 291                                 #size-cells = <1>;
 292                                 reg = < /* NFC Command Registers */
 293                                         0xc0000000 0x08000000
 294                                         /* NFC HSMC regs */
 295                                         0xf8014000 0x00000070
 296                                         /* NFC SRAM banks */
 297                                         0x00100000 0x00100000
 298                                         >;
 299                                 clocks = <&hsmc_clk>;
 300                                 atmel,write-by-sram;
 301                         };
 302                 };
 303
 304                 sdmmc0: sdio-host@a0000000 {
 305                         compatible = "atmel,sama5d2-sdhci";
 306                         reg = <0xa0000000 0x300>;
 307                         interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
 308                         clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
 309                         clock-names = "hclock", "multclk", "baseclk";
 310                         status = "disabled";
 311                 };
 312
 313                 sdmmc1: sdio-host@b0000000 {
 314                         compatible = "atmel,sama5d2-sdhci";
 315                         reg = <0xb0000000 0x300>;
 316                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
 317                         clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
 318                         clock-names = "hclock", "multclk", "baseclk";
 319                         status = "disabled";
 320                 };
 321
 322                 apb {
 323                         compatible = "simple-bus";
 324                         #address-cells = <1>;
 325                         #size-cells = <1>;
 326                         ranges;
 327
 328                         ramc0: ramc@f000c000 {
 329                                 compatible = "atmel,sama5d3-ddramc";
 330                                 reg = <0xf000c000 0x200>;
 331                                 clocks = <&ddrck>, <&mpddr_clk>;
 332                                 clock-names = "ddrck", "mpddr";
 333                         };
 334
 335                         dma0: dma-controller@f0010000 {
 336                                 compatible = "atmel,sama5d4-dma";
 337                                 reg = <0xf0010000 0x1000>;
 338                                 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
 339                                 #dma-cells = <1>;
 340                                 clocks = <&dma0_clk>;
 341                                 clock-names = "dma_clk";
 342                         };
 343
 344                         pmc: pmc@f0014000 {
 345                                 compatible = "atmel,sama5d2-pmc", "syscon";
 346                                 reg = <0xf0014000 0x160>;
 347                                 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
 348                                 interrupt-controller;
 349                                 #address-cells = <1>;
 350                                 #size-cells = <0>;
 351                                 #interrupt-cells = <1>;
 352
 353                                 main_rc_osc: main_rc_osc {
 354                                         compatible = "atmel,at91sam9x5-clk-main-rc-osc";
 355                                         #clock-cells = <0>;
 356                                         interrupt-parent = <&pmc>;
 357                                         interrupts = <AT91_PMC_MOSCRCS>;
 358                                         clock-frequency = <12000000>;
 359                                         clock-accuracy = <100000000>;
 360                                 };
 361
 362                                 main_osc: main_osc {
 363                                         compatible = "atmel,at91rm9200-clk-main-osc";
 364                                         #clock-cells = <0>;
 365                                         interrupt-parent = <&pmc>;
 366                                         interrupts = <AT91_PMC_MOSCS>;
 367                                         clocks = <&main_xtal>;
 368                                 };
 369
 370                                 main: mainck {
 371                                         compatible = "atmel,at91sam9x5-clk-main";
 372                                         #clock-cells = <0>;
 373                                         interrupt-parent = <&pmc>;
 374                                         interrupts = <AT91_PMC_MOSCSELS>;
 375                                         clocks = <&main_rc_osc &main_osc>;
 376                                 };
 377
 378                                 plla: pllack {
 379                                         compatible = "atmel,sama5d3-clk-pll";
 380                                         #clock-cells = <0>;
 381                                         interrupt-parent = <&pmc>;
 382                                         interrupts = <AT91_PMC_LOCKA>;
 383                                         clocks = <&main>;
 384                                         reg = <0>;
 385                                         atmel,clk-input-range = <12000000 12000000>;
 386                                         #atmel,pll-clk-output-range-cells = <4>;
 387                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 388                                 };
 389
 390                                 plladiv: plladivck {
 391                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 392                                         #clock-cells = <0>;
 393                                         clocks = <&plla>;
 394                                 };
 395
 396                                 utmi: utmick {
 397                                         compatible = "atmel,at91sam9x5-clk-utmi";
 398                                         #clock-cells = <0>;
 399                                         interrupt-parent = <&pmc>;
 400                                         interrupts = <AT91_PMC_LOCKU>;
 401                                         clocks = <&main>;
 402                                 };
 403
 404                                 mck: masterck {
 405                                         compatible = "atmel,at91sam9x5-clk-master";
 406                                         #clock-cells = <0>;
 407                                         interrupt-parent = <&pmc>;
 408                                         interrupts = <AT91_PMC_MCKRDY>;
 409                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
 410                                         atmel,clk-output-range = <124000000 166000000>;
 411                                         atmel,clk-divisors = <1 2 4 3>;
 412                                 };
 413
 414                                 h32ck: h32mxck {
 415                                         #clock-cells = <0>;
 416                                         compatible = "atmel,sama5d4-clk-h32mx";
 417                                         clocks = <&mck>;
 418                                 };
 419
 420                                 usb: usbck {
 421                                         compatible = "atmel,at91sam9x5-clk-usb";
 422                                         #clock-cells = <0>;
 423                                         clocks = <&plladiv>, <&utmi>;
 424                                 };
 425
 426                                 prog: progck {
 427                                         compatible = "atmel,at91sam9x5-clk-programmable";
 428                                         #address-cells = <1>;
 429                                         #size-cells = <0>;
 430                                         interrupt-parent = <&pmc>;
 431                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 432
 433                                         prog0: prog0 {
 434                                                 #clock-cells = <0>;
 435                                                 reg = <0>;
 436                                                 interrupts = <AT91_PMC_PCKRDY(0)>;
 437                                         };
 438
 439                                         prog1: prog1 {
 440                                                 #clock-cells = <0>;
 441                                                 reg = <1>;
 442                                                 interrupts = <AT91_PMC_PCKRDY(1)>;
 443                                         };
 444
 445                                         prog2: prog2 {
 446                                                 #clock-cells = <0>;
 447                                                 reg = <2>;
 448                                                 interrupts = <AT91_PMC_PCKRDY(2)>;
 449                                         };
 450                                 };
 451
 452                                 systemck {
 453                                         compatible = "atmel,at91rm9200-clk-system";
 454                                         #address-cells = <1>;
 455                                         #size-cells = <0>;
 456
 457                                         ddrck: ddrck {
 458                                                 #clock-cells = <0>;
 459                                                 reg = <2>;
 460                                                 clocks = <&mck>;
 461                                         };
 462
 463                                         lcdck: lcdck {
 464                                                 #clock-cells = <0>;
 465                                                 reg = <3>;
 466                                                 clocks = <&mck>;
 467                                         };
 468
 469                                         uhpck: uhpck {
 470                                                 #clock-cells = <0>;
 471                                                 reg = <6>;
 472                                                 clocks = <&usb>;
 473                                         };
 474
 475                                         udpck: udpck {
 476                                                 #clock-cells = <0>;
 477                                                 reg = <7>;
 478                                                 clocks = <&usb>;
 479                                         };
 480
 481                                         pck0: pck0 {
 482                                                 #clock-cells = <0>;
 483                                                 reg = <8>;
 484                                                 clocks = <&prog0>;
 485                                         };
 486
 487                                         pck1: pck1 {
 488                                                 #clock-cells = <0>;
 489                                                 reg = <9>;
 490                                                 clocks = <&prog1>;
 491                                         };
 492
 493                                         pck2: pck2 {
 494                                                 #clock-cells = <0>;
 495                                                 reg = <10>;
 496                                                 clocks = <&prog2>;
 497                                         };
 498
 499                                         iscck: iscck {
 500                                                 #clock-cells = <0>;
 501                                                 reg = <18>;
 502                                                 clocks = <&mck>;
 503                                         };
 504                                 };
 505
 506                                 periph32ck {
 507                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 508                                         #address-cells = <1>;
 509                                         #size-cells = <0>;
 510                                         clocks = <&h32ck>;
 511
 512                                         macb0_clk: macb0_clk {
 513                                                 #clock-cells = <0>;
 514                                                 reg = <5>;
 515                                                 atmel,clk-output-range = <0 83000000>;
 516                                         };
 517
 518                                         tdes_clk: tdes_clk {
 519                                                 #clock-cells = <0>;
 520                                                 reg = <11>;
 521                                                 atmel,clk-output-range = <0 83000000>;
 522                                         };
 523
 524                                         matrix1_clk: matrix1_clk {
 525                                                 #clock-cells = <0>;
 526                                                 reg = <14>;
 527                                         };
 528
 529                                         hsmc_clk: hsmc_clk {
 530                                                 #clock-cells = <0>;
 531                                                 reg = <17>;
 532                                         };
 533
 534                                         pioA_clk: pioA_clk {
 535                                                 #clock-cells = <0>;
 536                                                 reg = <18>;
 537                                                 atmel,clk-output-range = <0 83000000>;
 538                                         };
 539
 540                                         flx0_clk: flx0_clk {
 541                                                 #clock-cells = <0>;
 542                                                 reg = <19>;
 543                                                 atmel,clk-output-range = <0 83000000>;
 544                                         };
 545
 546                                         flx1_clk: flx1_clk {
 547                                                 #clock-cells = <0>;
 548                                                 reg = <20>;
 549                                                 atmel,clk-output-range = <0 83000000>;
 550                                         };
 551
 552                                         flx2_clk: flx2_clk {
 553                                                 #clock-cells = <0>;
 554                                                 reg = <21>;
 555                                                 atmel,clk-output-range = <0 83000000>;
 556                                         };
 557
 558                                         flx3_clk: flx3_clk {
 559                                                 #clock-cells = <0>;
 560                                                 reg = <22>;
 561                                                 atmel,clk-output-range = <0 83000000>;
 562                                         };
 563
 564                                         flx4_clk: flx4_clk {
 565                                                 #clock-cells = <0>;
 566                                                 reg = <23>;
 567                                                 atmel,clk-output-range = <0 83000000>;
 568                                         };
 569
 570                                         uart0_clk: uart0_clk {
 571                                                 #clock-cells = <0>;
 572                                                 reg = <24>;
 573                                                 atmel,clk-output-range = <0 83000000>;
 574                                         };
 575
 576                                         uart1_clk: uart1_clk {
 577                                                 #clock-cells = <0>;
 578                                                 reg = <25>;
 579                                                 atmel,clk-output-range = <0 83000000>;
 580                                         };
 581
 582                                         uart2_clk: uart2_clk {
 583                                                 #clock-cells = <0>;
 584                                                 reg = <26>;
 585                                                 atmel,clk-output-range = <0 83000000>;
 586                                         };
 587
 588                                         uart3_clk: uart3_clk {
 589                                                 #clock-cells = <0>;
 590                                                 reg = <27>;
 591                                                 atmel,clk-output-range = <0 83000000>;
 592                                         };
 593
 594                                         uart4_clk: uart4_clk {
 595                                                 #clock-cells = <0>;
 596                                                 reg = <28>;
 597                                                 atmel,clk-output-range = <0 83000000>;
 598                                         };
 599
 600                                         twi0_clk: twi0_clk {
 601                                                 reg = <29>;
 602                                                 #clock-cells = <0>;
 603                                                 atmel,clk-output-range = <0 83000000>;
 604                                         };
 605
 606                                         twi1_clk: twi1_clk {
 607                                                 #clock-cells = <0>;
 608                                                 reg = <30>;
 609                                                 atmel,clk-output-range = <0 83000000>;
 610                                         };
 611
 612                                         spi0_clk: spi0_clk {
 613                                                 #clock-cells = <0>;
 614                                                 reg = <33>;
 615                                                 atmel,clk-output-range = <0 83000000>;
 616                                         };
 617
 618                                         spi1_clk: spi1_clk {
 619                                                 #clock-cells = <0>;
 620                                                 reg = <34>;
 621                                                 atmel,clk-output-range = <0 83000000>;
 622                                         };
 623
 624                                         tcb0_clk: tcb0_clk {
 625                                                 #clock-cells = <0>;
 626                                                 reg = <35>;
 627                                                 atmel,clk-output-range = <0 83000000>;
 628                                         };
 629
 630                                         tcb1_clk: tcb1_clk {
 631                                                 #clock-cells = <0>;
 632                                                 reg = <36>;
 633                                                 atmel,clk-output-range = <0 83000000>;
 634                                         };
 635
 636                                         pwm_clk: pwm_clk {
 637                                                 #clock-cells = <0>;
 638                                                 reg = <38>;
 639                                                 atmel,clk-output-range = <0 83000000>;
 640                                         };
 641
 642                                         adc_clk: adc_clk {
 643                                                 #clock-cells = <0>;
 644                                                 reg = <40>;
 645                                                 atmel,clk-output-range = <0 83000000>;
 646                                         };
 647
 648                                         uhphs_clk: uhphs_clk {
 649                                                 #clock-cells = <0>;
 650                                                 reg = <41>;
 651                                                 atmel,clk-output-range = <0 83000000>;
 652                                         };
 653
 654                                         udphs_clk: udphs_clk {
 655                                                 #clock-cells = <0>;
 656                                                 reg = <42>;
 657                                                 atmel,clk-output-range = <0 83000000>;
 658                                         };
 659
 660                                         ssc0_clk: ssc0_clk {
 661                                                 #clock-cells = <0>;
 662                                                 reg = <43>;
 663                                                 atmel,clk-output-range = <0 83000000>;
 664                                         };
 665
 666                                         ssc1_clk: ssc1_clk {
 667                                                 #clock-cells = <0>;
 668                                                 reg = <44>;
 669                                                 atmel,clk-output-range = <0 83000000>;
 670                                         };
 671
 672                                         trng_clk: trng_clk {
 673                                                 #clock-cells = <0>;
 674                                                 reg = <47>;
 675                                                 atmel,clk-output-range = <0 83000000>;
 676                                         };
 677
 678                                         pdmic_clk: pdmic_clk {
 679                                                 #clock-cells = <0>;
 680                                                 reg = <48>;
 681                                                 atmel,clk-output-range = <0 83000000>;
 682                                         };
 683
 684                                         i2s0_clk: i2s0_clk {
 685                                                 #clock-cells = <0>;
 686                                                 reg = <54>;
 687                                                 atmel,clk-output-range = <0 83000000>;
 688                                         };
 689
 690                                         i2s1_clk: i2s1_clk {
 691                                                 #clock-cells = <0>;
 692                                                 reg = <55>;
 693                                                 atmel,clk-output-range = <0 83000000>;
 694                                         };
 695
 696                                         classd_clk: classd_clk {
 697                                                 #clock-cells = <0>;
 698                                                 reg = <59>;
 699                                                 atmel,clk-output-range = <0 83000000>;
 700                                         };
 701                                 };
 702
 703                                 periph64ck {
 704                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 705                                         #address-cells = <1>;
 706                                         #size-cells = <0>;
 707                                         clocks = <&mck>;
 708
 709                                         dma0_clk: dma0_clk {
 710                                                 #clock-cells = <0>;
 711                                                 reg = <6>;
 712                                         };
 713
 714                                         dma1_clk: dma1_clk {
 715                                                 #clock-cells = <0>;
 716                                                 reg = <7>;
 717                                         };
 718
 719                                         aes_clk: aes_clk {
 720                                                 #clock-cells = <0>;
 721                                                 reg = <9>;
 722                                         };
 723
 724                                         aesb_clk: aesb_clk {
 725                                                 #clock-cells = <0>;
 726                                                 reg = <10>;
 727                                         };
 728
 729                                         sha_clk: sha_clk {
 730                                                 #clock-cells = <0>;
 731                                                 reg = <12>;
 732                                         };
 733
 734                                         mpddr_clk: mpddr_clk {
 735                                                 #clock-cells = <0>;
 736                                                 reg = <13>;
 737                                         };
 738
 739                                         matrix0_clk: matrix0_clk {
 740                                                 #clock-cells = <0>;
 741                                                 reg = <15>;
 742                                         };
 743
 744                                         sdmmc0_hclk: sdmmc0_hclk {
 745                                                 #clock-cells = <0>;
 746                                                 reg = <31>;
 747                                         };
 748
 749                                         sdmmc1_hclk: sdmmc1_hclk {
 750                                                 #clock-cells = <0>;
 751                                                 reg = <32>;
 752                                         };
 753
 754                                         lcdc_clk: lcdc_clk {
 755                                                 #clock-cells = <0>;
 756                                                 reg = <45>;
 757                                         };
 758
 759                                         isc_clk: isc_clk {
 760                                                 #clock-cells = <0>;
 761                                                 reg = <46>;
 762                                         };
 763
 764                                         qspi0_clk: qspi0_clk {
 765                                                 #clock-cells = <0>;
 766                                                 reg = <52>;
 767                                         };
 768
 769                                         qspi1_clk: qspi1_clk {
 770                                                 #clock-cells = <0>;
 771                                                 reg = <53>;
 772                                         };
 773                                 };
 774
 775                                 gck {
 776                                         compatible = "atmel,sama5d2-clk-generated";
 777                                         #address-cells = <1>;
 778                                         #size-cells = <0>;
 779                                         interrupt-parent = <&pmc>;
 780                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 781
 782                                         sdmmc0_gclk: sdmmc0_gclk {
 783                                                 #clock-cells = <0>;
 784                                                 reg = <31>;
 785                                         };
 786
 787                                         sdmmc1_gclk: sdmmc1_gclk {
 788                                                 #clock-cells = <0>;
 789                                                 reg = <32>;
 790                                         };
 791
 792                                         tcb0_gclk: tcb0_gclk {
 793                                                 #clock-cells = <0>;
 794                                                 reg = <35>;
 795                                                 atmel,clk-output-range = <0 83000000>;
 796                                         };
 797
 798                                         tcb1_gclk: tcb1_gclk {
 799                                                 #clock-cells = <0>;
 800                                                 reg = <36>;
 801                                                 atmel,clk-output-range = <0 83000000>;
 802                                         };
 803
 804                                         pwm_gclk: pwm_gclk {
 805                                                 #clock-cells = <0>;
 806                                                 reg = <38>;
 807                                                 atmel,clk-output-range = <0 83000000>;
 808                                         };
 809
 810                                         pdmic_gclk: pdmic_gclk {
 811                                                 #clock-cells = <0>;
 812                                                 reg = <48>;
 813                                         };
 814
 815                                         i2s0_gclk: i2s0_gclk {
 816                                                 #clock-cells = <0>;
 817                                                 reg = <54>;
 818                                         };
 819
 820                                         i2s1_gclk: i2s1_gclk {
 821                                                 #clock-cells = <0>;
 822                                                 reg = <55>;
 823                                         };
 824                                 };
 825                         };
 826
 827                         sha@f0028000 {
 828                                 compatible = "atmel,at91sam9g46-sha";
 829                                 reg = <0xf0028000 0x100>;
 830                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 831                                 dmas = <&dma0
 832                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 833                                          AT91_XDMAC_DT_PERID(30))>;
 834                                 dma-names = "tx";
 835                                 clocks = <&sha_clk>;
 836                                 clock-names = "sha_clk";
 837                                 status = "okay";
 838                         };
 839
 840                         aes@f002c000 {
 841                                 compatible = "atmel,at91sam9g46-aes";
 842                                 reg = <0xf002c000 0x100>;
 843                                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
 844                                 dmas = <&dma0
 845                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 846                                          AT91_XDMAC_DT_PERID(26))>,
 847                                        <&dma0
 848                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 849                                          AT91_XDMAC_DT_PERID(27))>;
 850                                 dma-names = "tx", "rx";
 851                                 clocks = <&aes_clk>;
 852                                 clock-names = "aes_clk";
 853                                 status = "okay";
 854                         };
 855
 856                         spi0: spi@f8000000 {
 857                                 compatible = "atmel,at91rm9200-spi";
 858                                 reg = <0xf8000000 0x100>;
 859                                 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
 860                                 dmas = <&dma0
 861                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 862                                          AT91_XDMAC_DT_PERID(6))>,
 863                                        <&dma0
 864                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 865                                          AT91_XDMAC_DT_PERID(7))>;
 866                                 dma-names = "tx", "rx";
 867                                 clocks = <&spi0_clk>;
 868                                 clock-names = "spi_clk";
 869                                 atmel,fifo-size = <16>;
 870                                 #address-cells = <1>;
 871                                 #size-cells = <0>;
 872                                 status = "disabled";
 873                         };
 874
 875                         macb0: ethernet@f8008000 {
 876                                 compatible = "atmel,sama5d2-gem";
 877                                 reg = <0xf8008000 0x1000>;
 878                                 interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3          /* Queue 0 */
 879                                               66 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
 880                                               67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
 881                                 #address-cells = <1>;
 882                                 #size-cells = <0>;
 883                                 clocks = <&macb0_clk>, <&macb0_clk>;
 884                                 clock-names = "hclk", "pclk";
 885                                 status = "disabled";
 886                         };
 887
 888                         tcb0: timer@f800c000 {
 889                                 compatible = "atmel,at91sam9x5-tcb";
 890                                 reg = <0xf800c000 0x100>;
 891                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
 892                                 clocks = <&tcb0_clk>, <&clk32k>;
 893                                 clock-names = "t0_clk", "slow_clk";
 894                         };
 895
 896                         tcb1: timer@f8010000 {
 897                                 compatible = "atmel,at91sam9x5-tcb";
 898                                 reg = <0xf8010000 0x100>;
 899                                 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
 900                                 clocks = <&tcb1_clk>, <&clk32k>;
 901                                 clock-names = "t0_clk", "slow_clk";
 902                         };
 903
 904                         pdmic: pdmic@f8018000 {
 905                                 compatible = "atmel,sama5d2-pdmic";
 906                                 reg = <0xf8018000 0x124>;
 907                                 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
 908                                 dmas = <&dma0
 909                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 910                                         | AT91_XDMAC_DT_PERID(50))>;
 911                                 dma-names = "rx";
 912                                 clocks = <&pdmic_clk>, <&pdmic_gclk>;
 913                                 clock-names = "pclk", "gclk";
 914                                 status = "disabled";
 915                         };
 916
 917                         uart0: serial@f801c000 {
 918                                 compatible = "atmel,at91sam9260-usart";
 919                                 reg = <0xf801c000 0x100>;
 920                                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
 921                                 dmas = <&dma0
 922                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 923                                          AT91_XDMAC_DT_PERID(35))>,
 924                                        <&dma0
 925                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 926                                          AT91_XDMAC_DT_PERID(36))>;
 927                                 dma-names = "tx", "rx";
 928                                 clocks = <&uart0_clk>;
 929                                 clock-names = "usart";
 930                                 status = "disabled";
 931                         };
 932
 933                         uart1: serial@f8020000 {
 934                                 compatible = "atmel,at91sam9260-usart";
 935                                 reg = <0xf8020000 0x100>;
 936                                 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
 937                                 dmas = <&dma0
 938                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 939                                          AT91_XDMAC_DT_PERID(37))>,
 940                                        <&dma0
 941                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 942                                          AT91_XDMAC_DT_PERID(38))>;
 943                                 dma-names = "tx", "rx";
 944                                 clocks = <&uart1_clk>;
 945                                 clock-names = "usart";
 946                                 status = "disabled";
 947                         };
 948
 949                         uart2: serial@f8024000 {
 950                                 compatible = "atmel,at91sam9260-usart";
 951                                 reg = <0xf8024000 0x100>;
 952                                 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
 953                                 dmas = <&dma0
 954                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 955                                          AT91_XDMAC_DT_PERID(39))>,
 956                                        <&dma0
 957                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 958                                          AT91_XDMAC_DT_PERID(40))>;
 959                                 dma-names = "tx", "rx";
 960                                 clocks = <&uart2_clk>;
 961                                 clock-names = "usart";
 962                                 status = "disabled";
 963                         };
 964
 965                         i2c0: i2c@f8028000 {
 966                                 compatible = "atmel,sama5d2-i2c";
 967                                 reg = <0xf8028000 0x100>;
 968                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
 969                                 dmas = <&dma0
 970                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 971                                          AT91_XDMAC_DT_PERID(0))>,
 972                                        <&dma0
 973                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 974                                          AT91_XDMAC_DT_PERID(1))>;
 975                                 dma-names = "tx", "rx";
 976                                 #address-cells = <1>;
 977                                 #size-cells = <0>;
 978                                 clocks = <&twi0_clk>;
 979                                 status = "disabled";
 980                         };
 981
 982                         flx0: flexcom@f8034000 {
 983                                 compatible = "atmel,sama5d2-flexcom";
 984                                 reg = <0xf8034000 0x200>;
 985                                 clocks = <&flx0_clk>;
 986                                 #address-cells = <1>;
 987                                 #size-cells = <1>;
 988                                 ranges = <0x0 0xf8034000 0x800>;
 989                                 status = "disabled";
 990                         };
 991
 992                         flx1: flexcom@f8038000 {
 993                                 compatible = "atmel,sama5d2-flexcom";
 994                                 reg = <0xf8038000 0x200>;
 995                                 clocks = <&flx1_clk>;
 996                                 #address-cells = <1>;
 997                                 #size-cells = <1>;
 998                                 ranges = <0x0 0xf8038000 0x800>;
 999                                 status = "disabled";
1000                         };
1001
1002                         rstc@f8048000 {
1003                                 compatible = "atmel,sama5d3-rstc";
1004                                 reg = <0xf8048000 0x10>;
1005                                 clocks = <&clk32k>;
1006                         };
1007
1008                         pit: timer@f8048030 {
1009                                 compatible = "atmel,at91sam9260-pit";
1010                                 reg = <0xf8048030 0x10>;
1011                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1012                                 clocks = <&h32ck>;
1013                         };
1014
1015                         watchdog@f8048040 {
1016                                 compatible = "atmel,sama5d4-wdt";
1017                                 reg = <0xf8048040 0x10>;
1018                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1019                                 status = "disabled";
1020                         };
1021
1022                         sckc@f8048050 {
1023                                 compatible = "atmel,at91sam9x5-sckc";
1024                                 reg = <0xf8048050 0x4>;
1025
1026                                 slow_rc_osc: slow_rc_osc {
1027                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1028                                         #clock-cells = <0>;
1029                                         clock-frequency = <32768>;
1030                                         clock-accuracy = <250000000>;
1031                                         atmel,startup-time-usec = <75>;
1032                                 };
1033
1034                                 slow_osc: slow_osc {
1035                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
1036                                         #clock-cells = <0>;
1037                                         clocks = <&slow_xtal>;
1038                                         atmel,startup-time-usec = <1200000>;
1039                                 };
1040
1041                                 clk32k: slowck {
1042                                         compatible = "atmel,at91sam9x5-clk-slow";
1043                                         #clock-cells = <0>;
1044                                         clocks = <&slow_rc_osc &slow_osc>;
1045                                 };
1046                         };
1047
1048                         rtc@f80480b0 {
1049                                 compatible = "atmel,at91rm9200-rtc";
1050                                 reg = <0xf80480b0 0x30>;
1051                                 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1052                                 clocks = <&clk32k>;
1053                         };
1054
1055                         spi1: spi@fc000000 {
1056                                 compatible = "atmel,at91rm9200-spi";
1057                                 reg = <0xfc000000 0x100>;
1058                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1059                                 dmas = <&dma0
1060                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1061                                          AT91_XDMAC_DT_PERID(8))>,
1062                                        <&dma0
1063                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1064                                          AT91_XDMAC_DT_PERID(9))>;
1065                                 dma-names = "tx", "rx";
1066                                 clocks = <&spi1_clk>;
1067                                 clock-names = "spi_clk";
1068                                 atmel,fifo-size = <16>;
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071                                 status = "disabled";
1072                         };
1073
1074                         uart3: serial@fc008000 {
1075                                 compatible = "atmel,at91sam9260-usart";
1076                                 reg = <0xfc008000 0x100>;
1077                                 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1078                                 dmas = <&dma0
1079                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1080                                          AT91_XDMAC_DT_PERID(41))>,
1081                                        <&dma0
1082                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1083                                          AT91_XDMAC_DT_PERID(42))>;
1084                                 dma-names = "tx", "rx";
1085                                 clocks = <&uart3_clk>;
1086                                 clock-names = "usart";
1087                                 status = "disabled";
1088                         };
1089
1090                         uart4: serial@fc00c000 {
1091                                 compatible = "atmel,at91sam9260-usart";
1092                                 reg = <0xfc00c000 0x100>;
1093                                 dmas = <&dma0
1094                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1095                                          AT91_XDMAC_DT_PERID(43))>,
1096                                        <&dma0
1097                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1098                                          AT91_XDMAC_DT_PERID(44))>;
1099                                 dma-names = "tx", "rx";
1100                                 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1101                                 clocks = <&uart4_clk>;
1102                                 clock-names = "usart";
1103                                 status = "disabled";
1104                         };
1105
1106                         flx2: flexcom@fc010000 {
1107                                 compatible = "atmel,sama5d2-flexcom";
1108                                 reg = <0xfc010000 0x200>;
1109                                 clocks = <&flx2_clk>;
1110                                 #address-cells = <1>;
1111                                 #size-cells = <1>;
1112                                 ranges = <0x0 0xfc010000 0x800>;
1113                                 status = "disabled";
1114                         };
1115
1116                         flx3: flexcom@fc014000 {
1117                                 compatible = "atmel,sama5d2-flexcom";
1118                                 reg = <0xfc014000 0x200>;
1119                                 clocks = <&flx3_clk>;
1120                                 #address-cells = <1>;
1121                                 #size-cells = <1>;
1122                                 ranges = <0x0 0xfc014000 0x800>;
1123                                 status = "disabled";
1124                         };
1125
1126                         flx4: flexcom@fc018000 {
1127                                 compatible = "atmel,sama5d2-flexcom";
1128                                 reg = <0xfc018000 0x200>;
1129                                 clocks = <&flx4_clk>;
1130                                 #address-cells = <1>;
1131                                 #size-cells = <1>;
1132                                 ranges = <0x0 0xfc018000 0x800>;
1133                                 status = "disabled";
1134                         };
1135
1136                         aic: interrupt-controller@fc020000 {
1137                                 #interrupt-cells = <3>;
1138                                 compatible = "atmel,sama5d2-aic";
1139                                 interrupt-controller;
1140                                 reg = <0xfc020000 0x200>;
1141                                 atmel,external-irqs = <49>;
1142                         };
1143
1144                         i2c1: i2c@fc028000 {
1145                                 compatible = "atmel,sama5d2-i2c";
1146                                 reg = <0xfc028000 0x100>;
1147                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1148                                 dmas = <&dma0
1149                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1150                                          AT91_XDMAC_DT_PERID(2))>,
1151                                        <&dma0
1152                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1153                                          AT91_XDMAC_DT_PERID(3))>;
1154                                 dma-names = "tx", "rx";
1155                                 #address-cells = <1>;
1156                                 #size-cells = <0>;
1157                                 clocks = <&twi1_clk>;
1158                                 status = "disabled";
1159                         };
1160
1161                         pioA: pinctrl@fc038000 {
1162                                 compatible = "atmel,sama5d2-pinctrl";
1163                                 reg = <0xfc038000 0x600>;
1164                                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1165                                              <68 IRQ_TYPE_LEVEL_HIGH 7>,
1166                                              <69 IRQ_TYPE_LEVEL_HIGH 7>,
1167                                              <70 IRQ_TYPE_LEVEL_HIGH 7>;
1168                                 interrupt-controller;
1169                                 #interrupt-cells = <2>;
1170                                 gpio-controller;
1171                                 #gpio-cells = <2>;
1172                                 clocks = <&pioA_clk>;
1173                         };
1174
1175                         tdes@fc044000 {
1176                                 compatible = "atmel,at91sam9g46-tdes";
1177                                 reg = <0xfc044000 0x100>;
1178                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1179                                 dmas = <&dma0
1180                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1181                                          AT91_XDMAC_DT_PERID(28))>,
1182                                        <&dma0
1183                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1184                                          AT91_XDMAC_DT_PERID(29))>;
1185                                 dma-names = "tx", "rx";
1186                                 clocks = <&tdes_clk>;
1187                                 clock-names = "tdes_clk";
1188                                 status = "okay";
1189                         };
1190                 };
1191         };
1192 };