arch/arm/boot/dts/sama5d4.dtsi

   1 /*
   2  * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
   3  *
   4  *  Copyright (C) 2014 Atmel,
   5  *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "skeleton.dtsi"
  47 #include <dt-bindings/clock/at91.h>
  48 #include <dt-bindings/dma/at91.h>
  49 #include <dt-bindings/pinctrl/at91.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/gpio/gpio.h>
  52
  53 / {
  54         model = "Atmel SAMA5D4 family SoC";
  55         compatible = "atmel,sama5d4";
  56         interrupt-parent = <&aic>;
  57
  58         aliases {
  59                 serial0 = &usart3;
  60                 serial1 = &usart4;
  61                 serial2 = &usart2;
  62                 gpio0 = &pioA;
  63                 gpio1 = &pioB;
  64                 gpio2 = &pioC;
  65                 gpio3 = &pioD;
  66                 gpio4 = &pioE;
  67                 pwm0 = &pwm0;
  68                 ssc0 = &ssc0;
  69                 ssc1 = &ssc1;
  70                 tcb0 = &tcb0;
  71                 tcb1 = &tcb1;
  72                 i2c0 = &i2c0;
  73                 i2c1 = &i2c1;
  74                 i2c2 = &i2c2;
  75                 spi0 = &spi0;
  76                 spi1 = &spi1;
  77         };
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a5";
  85                         reg = <0>;
  86                         next-level-cache = <&L2>;
  87                 };
  88         };
  89
  90         memory {
  91                 reg = <0x20000000 0x20000000>;
  92         };
  93
  94         clocks {
  95                 slow_xtal: slow_xtal {
  96                         compatible = "fixed-clock";
  97                         #clock-cells = <0>;
  98                         clock-frequency = <0>;
  99                 };
 100
 101                 main_xtal: main_xtal {
 102                         compatible = "fixed-clock";
 103                         #clock-cells = <0>;
 104                         clock-frequency = <0>;
 105                 };
 106
 107                 adc_op_clk: adc_op_clk{
 108                         compatible = "fixed-clock";
 109                         #clock-cells = <0>;
 110                         clock-frequency = <1000000>;
 111                 };
 112         };
 113
 114         ns_sram: sram@00210000 {
 115                 compatible = "mmio-sram";
 116                 reg = <0x00210000 0x10000>;
 117         };
 118
 119         ahb {
 120                 compatible = "simple-bus";
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 ranges;
 124
 125                 usb0: gadget@00400000 {
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         compatible = "atmel,at91sam9rl-udc";
 129                         reg = <0x00400000 0x100000
 130                                0xfc02c000 0x4000>;
 131                         interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
 132                         clocks = <&udphs_clk>, <&utmi>;
 133                         clock-names = "pclk", "hclk";
 134                         status = "disabled";
 135
 136                         ep0 {
 137                                 reg = <0>;
 138                                 atmel,fifo-size = <64>;
 139                                 atmel,nb-banks = <1>;
 140                         };
 141
 142                         ep1 {
 143                                 reg = <1>;
 144                                 atmel,fifo-size = <1024>;
 145                                 atmel,nb-banks = <3>;
 146                                 atmel,can-dma;
 147                                 atmel,can-isoc;
 148                         };
 149
 150                         ep2 {
 151                                 reg = <2>;
 152                                 atmel,fifo-size = <1024>;
 153                                 atmel,nb-banks = <3>;
 154                                 atmel,can-dma;
 155                                 atmel,can-isoc;
 156                         };
 157
 158                         ep3 {
 159                                 reg = <3>;
 160                                 atmel,fifo-size = <1024>;
 161                                 atmel,nb-banks = <2>;
 162                                 atmel,can-dma;
 163                                 atmel,can-isoc;
 164                         };
 165
 166                         ep4 {
 167                                 reg = <4>;
 168                                 atmel,fifo-size = <1024>;
 169                                 atmel,nb-banks = <2>;
 170                                 atmel,can-dma;
 171                                 atmel,can-isoc;
 172                         };
 173
 174                         ep5 {
 175                                 reg = <5>;
 176                                 atmel,fifo-size = <1024>;
 177                                 atmel,nb-banks = <2>;
 178                                 atmel,can-dma;
 179                                 atmel,can-isoc;
 180                         };
 181
 182                         ep6 {
 183                                 reg = <6>;
 184                                 atmel,fifo-size = <1024>;
 185                                 atmel,nb-banks = <2>;
 186                                 atmel,can-dma;
 187                                 atmel,can-isoc;
 188                         };
 189
 190                         ep7 {
 191                                 reg = <7>;
 192                                 atmel,fifo-size = <1024>;
 193                                 atmel,nb-banks = <2>;
 194                                 atmel,can-dma;
 195                                 atmel,can-isoc;
 196                         };
 197
 198                         ep8 {
 199                                 reg = <8>;
 200                                 atmel,fifo-size = <1024>;
 201                                 atmel,nb-banks = <2>;
 202                                 atmel,can-isoc;
 203                         };
 204
 205                         ep9 {
 206                                 reg = <9>;
 207                                 atmel,fifo-size = <1024>;
 208                                 atmel,nb-banks = <2>;
 209                                 atmel,can-isoc;
 210                         };
 211
 212                         ep10 {
 213                                 reg = <10>;
 214                                 atmel,fifo-size = <1024>;
 215                                 atmel,nb-banks = <2>;
 216                                 atmel,can-isoc;
 217                         };
 218
 219                         ep11 {
 220                                 reg = <11>;
 221                                 atmel,fifo-size = <1024>;
 222                                 atmel,nb-banks = <2>;
 223                                 atmel,can-isoc;
 224                         };
 225
 226                         ep12 {
 227                                 reg = <12>;
 228                                 atmel,fifo-size = <1024>;
 229                                 atmel,nb-banks = <2>;
 230                                 atmel,can-isoc;
 231                         };
 232
 233                         ep13 {
 234                                 reg = <13>;
 235                                 atmel,fifo-size = <1024>;
 236                                 atmel,nb-banks = <2>;
 237                                 atmel,can-isoc;
 238                         };
 239
 240                         ep14 {
 241                                 reg = <14>;
 242                                 atmel,fifo-size = <1024>;
 243                                 atmel,nb-banks = <2>;
 244                                 atmel,can-isoc;
 245                         };
 246
 247                         ep15 {
 248                                 reg = <15>;
 249                                 atmel,fifo-size = <1024>;
 250                                 atmel,nb-banks = <2>;
 251                                 atmel,can-isoc;
 252                         };
 253                 };
 254
 255                 usb1: ohci@00500000 {
 256                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 257                         reg = <0x00500000 0x100000>;
 258                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 259                         clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
 260                                  <&uhpck>;
 261                         clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
 262                         status = "disabled";
 263                 };
 264
 265                 usb2: ehci@00600000 {
 266                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 267                         reg = <0x00600000 0x100000>;
 268                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 269                         clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
 270                         clock-names = "usb_clk", "ehci_clk", "uhpck";
 271                         status = "disabled";
 272                 };
 273
 274                 L2: cache-controller@00a00000 {
 275                         compatible = "arm,pl310-cache";
 276                         reg = <0x00a00000 0x1000>;
 277                         interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
 278                         cache-unified;
 279                         cache-level = <2>;
 280                 };
 281
 282                 nand0: nand@80000000 {
 283                         compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         ranges;
 287                         reg = < 0x80000000 0x08000000   /* EBI CS3 */
 288                                 0xfc05c070 0x00000490   /* SMC PMECC regs */
 289                                 0xfc05c500 0x00000100   /* SMC PMECC Error Location regs */
 290                                 >;
 291                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
 292                         atmel,nand-addr-offset = <21>;
 293                         atmel,nand-cmd-offset = <22>;
 294                         atmel,nand-has-dma;
 295                         pinctrl-names = "default";
 296                         pinctrl-0 = <&pinctrl_nand>;
 297                         status = "disabled";
 298
 299                         nfc@90000000 {
 300                                 compatible = "atmel,sama5d3-nfc";
 301                                 #address-cells = <1>;
 302                                 #size-cells = <1>;
 303                                 reg = <
 304                                         0x90000000 0x10000000   /* NFC Command Registers */
 305                                         0xfc05c000 0x00000070   /* NFC HSMC regs */
 306                                         0x00100000 0x00100000   /* NFC SRAM banks */
 307                                          >;
 308                                 clocks = <&hsmc_clk>;
 309                                 atmel,write-by-sram;
 310                         };
 311                 };
 312
 313                 apb {
 314                         compatible = "simple-bus";
 315                         #address-cells = <1>;
 316                         #size-cells = <1>;
 317                         ranges;
 318
 319                         hlcdc: hlcdc@f0000000 {
 320                                 compatible = "atmel,sama5d4-hlcdc";
 321                                 reg = <0xf0000000 0x4000>;
 322                                 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
 323                                 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
 324                                 clock-names = "periph_clk","sys_clk", "slow_clk";
 325                                 status = "disabled";
 326
 327                                 hlcdc-display-controller {
 328                                         compatible = "atmel,hlcdc-display-controller";
 329                                         #address-cells = <1>;
 330                                         #size-cells = <0>;
 331
 332                                         port@0 {
 333                                                 #address-cells = <1>;
 334                                                 #size-cells = <0>;
 335                                                 reg = <0>;
 336                                         };
 337                                 };
 338
 339                                 hlcdc_pwm: hlcdc-pwm {
 340                                         compatible = "atmel,hlcdc-pwm";
 341                                         pinctrl-names = "default";
 342                                         pinctrl-0 = <&pinctrl_lcd_pwm>;
 343                                         #pwm-cells = <3>;
 344                                 };
 345                         };
 346
 347                         dma1: dma-controller@f0004000 {
 348                                 compatible = "atmel,sama5d4-dma";
 349                                 reg = <0xf0004000 0x200>;
 350                                 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
 351                                 #dma-cells = <1>;
 352                                 clocks = <&dma1_clk>;
 353                                 clock-names = "dma_clk";
 354                         };
 355
 356                         isi: isi@f0008000 {
 357                                 compatible = "atmel,at91sam9g45-isi";
 358                                 reg = <0xf0008000 0x4000>;
 359                                 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
 360                                 pinctrl-names = "default";
 361                                 pinctrl-0 = <&pinctrl_isi_data_0_7>;
 362                                 clocks = <&isi_clk>;
 363                                 clock-names = "isi_clk";
 364                                 status = "disabled";
 365                                 port {
 366                                         #address-cells = <1>;
 367                                         #size-cells = <0>;
 368                                 };
 369                         };
 370
 371                         ramc0: ramc@f0010000 {
 372                                 compatible = "atmel,sama5d3-ddramc";
 373                                 reg = <0xf0010000 0x200>;
 374                                 clocks = <&ddrck>, <&mpddr_clk>;
 375                                 clock-names = "ddrck", "mpddr";
 376                         };
 377
 378                         dma0: dma-controller@f0014000 {
 379                                 compatible = "atmel,sama5d4-dma";
 380                                 reg = <0xf0014000 0x200>;
 381                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
 382                                 #dma-cells = <1>;
 383                                 clocks = <&dma0_clk>;
 384                                 clock-names = "dma_clk";
 385                         };
 386
 387                         pmc: pmc@f0018000 {
 388                                 compatible = "atmel,sama5d3-pmc";
 389                                 reg = <0xf0018000 0x120>;
 390                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 391                                 interrupt-controller;
 392                                 #address-cells = <1>;
 393                                 #size-cells = <0>;
 394                                 #interrupt-cells = <1>;
 395
 396                                 main_rc_osc: main_rc_osc {
 397                                         compatible = "atmel,at91sam9x5-clk-main-rc-osc";
 398                                         #clock-cells = <0>;
 399                                         interrupt-parent = <&pmc>;
 400                                         interrupts = <AT91_PMC_MOSCRCS>;
 401                                         clock-frequency = <12000000>;
 402                                         clock-accuracy = <100000000>;
 403                                 };
 404
 405                                 main_osc: main_osc {
 406                                         compatible = "atmel,at91rm9200-clk-main-osc";
 407                                         #clock-cells = <0>;
 408                                         interrupt-parent = <&pmc>;
 409                                         interrupts = <AT91_PMC_MOSCS>;
 410                                         clocks = <&main_xtal>;
 411                                 };
 412
 413                                 main: mainck {
 414                                         compatible = "atmel,at91sam9x5-clk-main";
 415                                         #clock-cells = <0>;
 416                                         interrupt-parent = <&pmc>;
 417                                         interrupts = <AT91_PMC_MOSCSELS>;
 418                                         clocks = <&main_rc_osc &main_osc>;
 419                                 };
 420
 421                                 plla: pllack {
 422                                         compatible = "atmel,sama5d3-clk-pll";
 423                                         #clock-cells = <0>;
 424                                         interrupt-parent = <&pmc>;
 425                                         interrupts = <AT91_PMC_LOCKA>;
 426                                         clocks = <&main>;
 427                                         reg = <0>;
 428                                         atmel,clk-input-range = <12000000 12000000>;
 429                                         #atmel,pll-clk-output-range-cells = <4>;
 430                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 431                                 };
 432
 433                                 plladiv: plladivck {
 434                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 435                                         #clock-cells = <0>;
 436                                         clocks = <&plla>;
 437                                 };
 438
 439                                 utmi: utmick {
 440                                         compatible = "atmel,at91sam9x5-clk-utmi";
 441                                         #clock-cells = <0>;
 442                                         interrupt-parent = <&pmc>;
 443                                         interrupts = <AT91_PMC_LOCKU>;
 444                                         clocks = <&main>;
 445                                 };
 446
 447                                 mck: masterck {
 448                                         compatible = "atmel,at91sam9x5-clk-master";
 449                                         #clock-cells = <0>;
 450                                         interrupt-parent = <&pmc>;
 451                                         interrupts = <AT91_PMC_MCKRDY>;
 452                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
 453                                         atmel,clk-output-range = <125000000 177000000>;
 454                                         atmel,clk-divisors = <1 2 4 3>;
 455                                 };
 456
 457                                 h32ck: h32mxck {
 458                                         #clock-cells = <0>;
 459                                         compatible = "atmel,sama5d4-clk-h32mx";
 460                                         clocks = <&mck>;
 461                                 };
 462
 463                                 usb: usbck {
 464                                         compatible = "atmel,at91sam9x5-clk-usb";
 465                                         #clock-cells = <0>;
 466                                         clocks = <&plladiv>, <&utmi>;
 467                                 };
 468
 469                                 prog: progck {
 470                                         compatible = "atmel,at91sam9x5-clk-programmable";
 471                                         #address-cells = <1>;
 472                                         #size-cells = <0>;
 473                                         interrupt-parent = <&pmc>;
 474                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 475
 476                                         prog0: prog0 {
 477                                                 #clock-cells = <0>;
 478                                                 reg = <0>;
 479                                                 interrupts = <AT91_PMC_PCKRDY(0)>;
 480                                         };
 481
 482                                         prog1: prog1 {
 483                                                 #clock-cells = <0>;
 484                                                 reg = <1>;
 485                                                 interrupts = <AT91_PMC_PCKRDY(1)>;
 486                                         };
 487
 488                                         prog2: prog2 {
 489                                                 #clock-cells = <0>;
 490                                                 reg = <2>;
 491                                                 interrupts = <AT91_PMC_PCKRDY(2)>;
 492                                         };
 493                                 };
 494
 495                                 smd: smdclk {
 496                                         compatible = "atmel,at91sam9x5-clk-smd";
 497                                         #clock-cells = <0>;
 498                                         clocks = <&plladiv>, <&utmi>;
 499                                 };
 500
 501                                 systemck {
 502                                         compatible = "atmel,at91rm9200-clk-system";
 503                                         #address-cells = <1>;
 504                                         #size-cells = <0>;
 505
 506                                         ddrck: ddrck {
 507                                                 #clock-cells = <0>;
 508                                                 reg = <2>;
 509                                                 clocks = <&mck>;
 510                                         };
 511
 512                                         lcdck: lcdck {
 513                                                 #clock-cells = <0>;
 514                                                 reg = <3>;
 515                                                 clocks = <&mck>;
 516                                         };
 517
 518                                         smdck: smdck {
 519                                                 #clock-cells = <0>;
 520                                                 reg = <4>;
 521                                                 clocks = <&smd>;
 522                                         };
 523
 524                                         uhpck: uhpck {
 525                                                 #clock-cells = <0>;
 526                                                 reg = <6>;
 527                                                 clocks = <&usb>;
 528                                         };
 529
 530                                         udpck: udpck {
 531                                                 #clock-cells = <0>;
 532                                                 reg = <7>;
 533                                                 clocks = <&usb>;
 534                                         };
 535
 536                                         pck0: pck0 {
 537                                                 #clock-cells = <0>;
 538                                                 reg = <8>;
 539                                                 clocks = <&prog0>;
 540                                         };
 541
 542                                         pck1: pck1 {
 543                                                 #clock-cells = <0>;
 544                                                 reg = <9>;
 545                                                 clocks = <&prog1>;
 546                                         };
 547
 548                                         pck2: pck2 {
 549                                                 #clock-cells = <0>;
 550                                                 reg = <10>;
 551                                                 clocks = <&prog2>;
 552                                         };
 553                                 };
 554
 555                                 periph32ck {
 556                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 557                                         #address-cells = <1>;
 558                                         #size-cells = <0>;
 559                                         clocks = <&h32ck>;
 560
 561                                         pioD_clk: pioD_clk {
 562                                                 #clock-cells = <0>;
 563                                                 reg = <5>;
 564                                         };
 565
 566                                         usart0_clk: usart0_clk {
 567                                                 #clock-cells = <0>;
 568                                                 reg = <6>;
 569                                         };
 570
 571                                         usart1_clk: usart1_clk {
 572                                                 #clock-cells = <0>;
 573                                                 reg = <7>;
 574                                         };
 575
 576                                         icm_clk: icm_clk {
 577                                                 #clock-cells = <0>;
 578                                                 reg = <9>;
 579                                         };
 580
 581                                         aes_clk: aes_clk {
 582                                                 #clock-cells = <0>;
 583                                                 reg = <12>;
 584                                         };
 585
 586                                         tdes_clk: tdes_clk {
 587                                                 #clock-cells = <0>;
 588                                                 reg = <14>;
 589                                         };
 590
 591                                         sha_clk: sha_clk {
 592                                                 #clock-cells = <0>;
 593                                                 reg = <15>;
 594                                         };
 595
 596                                         matrix1_clk: matrix1_clk {
 597                                                 #clock-cells = <0>;
 598                                                 reg = <17>;
 599                                         };
 600
 601                                         hsmc_clk: hsmc_clk {
 602                                                 #clock-cells = <0>;
 603                                                 reg = <22>;
 604                                         };
 605
 606                                         pioA_clk: pioA_clk {
 607                                                 #clock-cells = <0>;
 608                                                 reg = <23>;
 609                                         };
 610
 611                                         pioB_clk: pioB_clk {
 612                                                 #clock-cells = <0>;
 613                                                 reg = <24>;
 614                                         };
 615
 616                                         pioC_clk: pioC_clk {
 617                                                 #clock-cells = <0>;
 618                                                 reg = <25>;
 619                                         };
 620
 621                                         pioE_clk: pioE_clk {
 622                                                 #clock-cells = <0>;
 623                                                 reg = <26>;
 624                                         };
 625
 626                                         uart0_clk: uart0_clk {
 627                                                 #clock-cells = <0>;
 628                                                 reg = <27>;
 629                                         };
 630
 631                                         uart1_clk: uart1_clk {
 632                                                 #clock-cells = <0>;
 633                                                 reg = <28>;
 634                                         };
 635
 636                                         usart2_clk: usart2_clk {
 637                                                 #clock-cells = <0>;
 638                                                 reg = <29>;
 639                                         };
 640
 641                                         usart3_clk: usart3_clk {
 642                                                 #clock-cells = <0>;
 643                                                 reg = <30>;
 644                                         };
 645
 646                                         usart4_clk: usart4_clk {
 647                                                 #clock-cells = <0>;
 648                                                 reg = <31>;
 649                                         };
 650
 651                                         twi0_clk: twi0_clk {
 652                                                 reg = <32>;
 653                                                 #clock-cells = <0>;
 654                                         };
 655
 656                                         twi1_clk: twi1_clk {
 657                                                 #clock-cells = <0>;
 658                                                 reg = <33>;
 659                                         };
 660
 661                                         twi2_clk: twi2_clk {
 662                                                 #clock-cells = <0>;
 663                                                 reg = <34>;
 664                                         };
 665
 666                                         mci0_clk: mci0_clk {
 667                                                 #clock-cells = <0>;
 668                                                 reg = <35>;
 669                                         };
 670
 671                                         mci1_clk: mci1_clk {
 672                                                 #clock-cells = <0>;
 673                                                 reg = <36>;
 674                                         };
 675
 676                                         spi0_clk: spi0_clk {
 677                                                 #clock-cells = <0>;
 678                                                 reg = <37>;
 679                                         };
 680
 681                                         spi1_clk: spi1_clk {
 682                                                 #clock-cells = <0>;
 683                                                 reg = <38>;
 684                                         };
 685
 686                                         spi2_clk: spi2_clk {
 687                                                 #clock-cells = <0>;
 688                                                 reg = <39>;
 689                                         };
 690
 691                                         tcb0_clk: tcb0_clk {
 692                                                 #clock-cells = <0>;
 693                                                 reg = <40>;
 694                                         };
 695
 696                                         tcb1_clk: tcb1_clk {
 697                                                 #clock-cells = <0>;
 698                                                 reg = <41>;
 699                                         };
 700
 701                                         tcb2_clk: tcb2_clk {
 702                                                 #clock-cells = <0>;
 703                                                 reg = <42>;
 704                                         };
 705
 706                                         pwm_clk: pwm_clk {
 707                                                 #clock-cells = <0>;
 708                                                 reg = <43>;
 709                                         };
 710
 711                                         adc_clk: adc_clk {
 712                                                 #clock-cells = <0>;
 713                                                 reg = <44>;
 714                                         };
 715
 716                                         dbgu_clk: dbgu_clk {
 717                                                 #clock-cells = <0>;
 718                                                 reg = <45>;
 719                                         };
 720
 721                                         uhphs_clk: uhphs_clk {
 722                                                 #clock-cells = <0>;
 723                                                 reg = <46>;
 724                                         };
 725
 726                                         udphs_clk: udphs_clk {
 727                                                 #clock-cells = <0>;
 728                                                 reg = <47>;
 729                                         };
 730
 731                                         ssc0_clk: ssc0_clk {
 732                                                 #clock-cells = <0>;
 733                                                 reg = <48>;
 734                                         };
 735
 736                                         ssc1_clk: ssc1_clk {
 737                                                 #clock-cells = <0>;
 738                                                 reg = <49>;
 739                                         };
 740
 741                                         trng_clk: trng_clk {
 742                                                 #clock-cells = <0>;
 743                                                 reg = <53>;
 744                                         };
 745
 746                                         macb0_clk: macb0_clk {
 747                                                 #clock-cells = <0>;
 748                                                 reg = <54>;
 749                                         };
 750
 751                                         macb1_clk: macb1_clk {
 752                                                 #clock-cells = <0>;
 753                                                 reg = <55>;
 754                                         };
 755
 756                                         fuse_clk: fuse_clk {
 757                                                 #clock-cells = <0>;
 758                                                 reg = <57>;
 759                                         };
 760
 761                                         securam_clk: securam_clk {
 762                                                 #clock-cells = <0>;
 763                                                 reg = <59>;
 764                                         };
 765
 766                                         smd_clk: smd_clk {
 767                                                 #clock-cells = <0>;
 768                                                 reg = <61>;
 769                                         };
 770
 771                                         twi3_clk: twi3_clk {
 772                                                 #clock-cells = <0>;
 773                                                 reg = <62>;
 774                                         };
 775
 776                                         catb_clk: catb_clk {
 777                                                 #clock-cells = <0>;
 778                                                 reg = <63>;
 779                                         };
 780                                 };
 781
 782                                 periph64ck {
 783                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 784                                         #address-cells = <1>;
 785                                         #size-cells = <0>;
 786                                         clocks = <&mck>;
 787
 788                                         dma0_clk: dma0_clk {
 789                                                 #clock-cells = <0>;
 790                                                 reg = <8>;
 791                                         };
 792
 793                                         cpkcc_clk: cpkcc_clk {
 794                                                 #clock-cells = <0>;
 795                                                 reg = <10>;
 796                                         };
 797
 798                                         aesb_clk: aesb_clk {
 799                                                 #clock-cells = <0>;
 800                                                 reg = <13>;
 801                                         };
 802
 803                                         mpddr_clk: mpddr_clk {
 804                                                 #clock-cells = <0>;
 805                                                 reg = <16>;
 806                                         };
 807
 808                                         matrix0_clk: matrix0_clk {
 809                                                 #clock-cells = <0>;
 810                                                 reg = <18>;
 811                                         };
 812
 813                                         vdec_clk: vdec_clk {
 814                                                 #clock-cells = <0>;
 815                                                 reg = <19>;
 816                                         };
 817
 818                                         dma1_clk: dma1_clk {
 819                                                 #clock-cells = <0>;
 820                                                 reg = <50>;
 821                                         };
 822
 823                                         lcdc_clk: lcdc_clk {
 824                                                 #clock-cells = <0>;
 825                                                 reg = <51>;
 826                                         };
 827
 828                                         isi_clk: isi_clk {
 829                                                 #clock-cells = <0>;
 830                                                 reg = <52>;
 831                                         };
 832                                 };
 833                         };
 834
 835                         mmc0: mmc@f8000000 {
 836                                 compatible = "atmel,hsmci";
 837                                 reg = <0xf8000000 0x600>;
 838                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
 839                                 dmas = <&dma1
 840                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 841                                         | AT91_XDMAC_DT_PERID(0))>;
 842                                 dma-names = "rxtx";
 843                                 pinctrl-names = "default";
 844                                 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
 845                                 status = "disabled";
 846                                 #address-cells = <1>;
 847                                 #size-cells = <0>;
 848                                 clocks = <&mci0_clk>;
 849                                 clock-names = "mci_clk";
 850                         };
 851
 852                         ssc0: ssc@f8008000 {
 853                                 compatible = "atmel,at91sam9g45-ssc";
 854                                 reg = <0xf8008000 0x4000>;
 855                                 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
 856                                 pinctrl-names = "default";
 857                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 858                                 dmas = <&dma1
 859                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 860                                         | AT91_XDMAC_DT_PERID(26))>,
 861                                        <&dma1
 862                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 863                                         | AT91_XDMAC_DT_PERID(27))>;
 864                                 dma-names = "tx", "rx";
 865                                 clocks = <&ssc0_clk>;
 866                                 clock-names = "pclk";
 867                                 status = "disabled";
 868                         };
 869
 870                         pwm0: pwm@f800c000 {
 871                                 compatible = "atmel,sama5d3-pwm";
 872                                 reg = <0xf800c000 0x300>;
 873                                 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
 874                                 #pwm-cells = <3>;
 875                                 clocks = <&pwm_clk>;
 876                                 status = "disabled";
 877                         };
 878
 879                         spi0: spi@f8010000 {
 880                                 #address-cells = <1>;
 881                                 #size-cells = <0>;
 882                                 compatible = "atmel,at91rm9200-spi";
 883                                 reg = <0xf8010000 0x100>;
 884                                 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
 885                                 dmas = <&dma1
 886                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 887                                         | AT91_XDMAC_DT_PERID(10))>,
 888                                        <&dma1
 889                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 890                                         | AT91_XDMAC_DT_PERID(11))>;
 891                                 dma-names = "tx", "rx";
 892                                 pinctrl-names = "default";
 893                                 pinctrl-0 = <&pinctrl_spi0>;
 894                                 clocks = <&spi0_clk>;
 895                                 clock-names = "spi_clk";
 896                                 status = "disabled";
 897                         };
 898
 899                         spi1: spi@fc018000 {
 900                                 #address-cells = <1>;
 901                                 #size-cells = <0>;
 902                                 compatible = "atmel,at91rm9200-spi";
 903                                 reg = <0xfc018000 0x100>;
 904                                 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
 905                                 dmas = <&dma1
 906                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 907                                         | AT91_XDMAC_DT_PERID(12))>,
 908                                        <&dma1
 909                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 910                                         | AT91_XDMAC_DT_PERID(13))>;
 911                                 dma-names = "tx", "rx";
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&pinctrl_spi1>;
 914                                 clocks = <&spi1_clk>;
 915                                 clock-names = "spi_clk";
 916                                 status = "disabled";
 917                         };
 918
 919                         i2c0: i2c@f8014000 {
 920                                 compatible = "atmel,at91sam9x5-i2c";
 921                                 reg = <0xf8014000 0x4000>;
 922                                 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
 923                                 dmas = <&dma1
 924                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 925                                         | AT91_XDMAC_DT_PERID(2))>,
 926                                        <&dma1
 927                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 928                                         | AT91_XDMAC_DT_PERID(3))>;
 929                                 dma-names = "tx", "rx";
 930                                 pinctrl-names = "default";
 931                                 pinctrl-0 = <&pinctrl_i2c0>;
 932                                 #address-cells = <1>;
 933                                 #size-cells = <0>;
 934                                 clocks = <&twi0_clk>;
 935                                 status = "disabled";
 936                         };
 937
 938                         i2c1: i2c@f8018000 {
 939                                 compatible = "atmel,at91sam9x5-i2c";
 940                                 reg = <0xf8018000 0x4000>;
 941                                 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
 942                                 dmas = <&dma1
 943                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 944                                         AT91_XDMAC_DT_PERID(4)>,
 945                                        <&dma1
 946                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 947                                         AT91_XDMAC_DT_PERID(5)>;
 948                                 dma-names = "tx", "rx";
 949                                 pinctrl-names = "default";
 950                                 pinctrl-0 = <&pinctrl_i2c1>;
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953                                 clocks = <&twi1_clk>;
 954                                 status = "disabled";
 955                         };
 956
 957                         tcb0: timer@f801c000 {
 958                                 compatible = "atmel,at91sam9x5-tcb";
 959                                 reg = <0xf801c000 0x100>;
 960                                 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
 961                                 clocks = <&tcb0_clk>;
 962                                 clock-names = "t0_clk";
 963                         };
 964
 965                         macb0: ethernet@f8020000 {
 966                                 compatible = "atmel,sama5d4-gem";
 967                                 reg = <0xf8020000 0x100>;
 968                                 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
 969                                 pinctrl-names = "default";
 970                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 clocks = <&macb0_clk>, <&macb0_clk>;
 974                                 clock-names = "hclk", "pclk";
 975                                 status = "disabled";
 976                         };
 977
 978                         i2c2: i2c@f8024000 {
 979                                 compatible = "atmel,at91sam9x5-i2c";
 980                                 reg = <0xf8024000 0x4000>;
 981                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
 982                                 dmas = <&dma1
 983                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 984                                         | AT91_XDMAC_DT_PERID(6))>,
 985                                        <&dma1
 986                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 987                                         | AT91_XDMAC_DT_PERID(7))>;
 988                                 dma-names = "tx", "rx";
 989                                 pinctrl-names = "default";
 990                                 pinctrl-0 = <&pinctrl_i2c2>;
 991                                 #address-cells = <1>;
 992                                 #size-cells = <0>;
 993                                 clocks = <&twi2_clk>;
 994                                 status = "disabled";
 995                         };
 996
 997                         sfr: sfr@f8028000 {
 998                                 compatible = "atmel,sama5d4-sfr", "syscon";
 999                                 reg = <0xf8028000 0x60>;
1000                         };
1001
1002                         usart0: serial@f802c000 {
1003                                 compatible = "atmel,at91sam9260-usart";
1004                                 reg = <0xf802c000 0x100>;
1005                                 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
1006                                 dmas = <&dma1
1007                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1008                                          AT91_XDMAC_DT_PERID(36))>,
1009                                        <&dma1
1010                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1011                                          AT91_XDMAC_DT_PERID(37))>;
1012                                 dma-names = "tx", "rx";
1013                                 pinctrl-names = "default";
1014                                 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
1015                                 clocks = <&usart0_clk>;
1016                                 clock-names = "usart";
1017                                 status = "disabled";
1018                         };
1019
1020                         usart1: serial@f8030000 {
1021                                 compatible = "atmel,at91sam9260-usart";
1022                                 reg = <0xf8030000 0x100>;
1023                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1024                                 dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1025                                         AT91_XDMAC_DT_PERID(38))>,
1026                                        <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1027                                         AT91_XDMAC_DT_PERID(39))>;
1028                                 dma-names = "tx", "rx";
1029                                 pinctrl-names = "default";
1030                                 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1031                                 clocks = <&usart1_clk>;
1032                                 clock-names = "usart";
1033                                 status = "disabled";
1034                         };
1035
1036                         mmc1: mmc@fc000000 {
1037                                 compatible = "atmel,hsmci";
1038                                 reg = <0xfc000000 0x600>;
1039                                 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1040                                 dmas = <&dma1
1041                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1042                                         | AT91_XDMAC_DT_PERID(1))>;
1043                                 dma-names = "rxtx";
1044                                 pinctrl-names = "default";
1045                                 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1046                                 status = "disabled";
1047                                 #address-cells = <1>;
1048                                 #size-cells = <0>;
1049                                 clocks = <&mci1_clk>;
1050                                 clock-names = "mci_clk";
1051                         };
1052
1053                         usart2: serial@fc008000 {
1054                                 compatible = "atmel,at91sam9260-usart";
1055                                 reg = <0xfc008000 0x100>;
1056                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1057                                 dmas = <&dma1
1058                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1059                                         | AT91_XDMAC_DT_PERID(16))>,
1060                                        <&dma1
1061                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1062                                         | AT91_XDMAC_DT_PERID(17))>;
1063                                 dma-names = "tx", "rx";
1064                                 pinctrl-names = "default";
1065                                 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1066                                 clocks = <&usart2_clk>;
1067                                 clock-names = "usart";
1068                                 status = "disabled";
1069                         };
1070
1071                         usart3: serial@fc00c000 {
1072                                 compatible = "atmel,at91sam9260-usart";
1073                                 reg = <0xfc00c000 0x100>;
1074                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1075                                 dmas = <&dma1
1076                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1077                                         | AT91_XDMAC_DT_PERID(18))>,
1078                                        <&dma1
1079                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1080                                         | AT91_XDMAC_DT_PERID(19))>;
1081                                 dma-names = "tx", "rx";
1082                                 pinctrl-names = "default";
1083                                 pinctrl-0 = <&pinctrl_usart3>;
1084                                 clocks = <&usart3_clk>;
1085                                 clock-names = "usart";
1086                                 status = "disabled";
1087                         };
1088
1089                         usart4: serial@fc010000 {
1090                                 compatible = "atmel,at91sam9260-usart";
1091                                 reg = <0xfc010000 0x100>;
1092                                 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1093                                 dmas = <&dma1
1094                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1095                                         | AT91_XDMAC_DT_PERID(20))>,
1096                                        <&dma1
1097                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1098                                         | AT91_XDMAC_DT_PERID(21))>;
1099                                 dma-names = "tx", "rx";
1100                                 pinctrl-names = "default";
1101                                 pinctrl-0 = <&pinctrl_usart4>;
1102                                 clocks = <&usart4_clk>;
1103                                 clock-names = "usart";
1104                                 status = "disabled";
1105                         };
1106
1107                         ssc1: ssc@fc014000 {
1108                                 compatible = "atmel,at91sam9g45-ssc";
1109                                 reg = <0xfc014000 0x4000>;
1110                                 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1111                                 pinctrl-names = "default";
1112                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1113                                 dmas = <&dma1
1114                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1115                                         | AT91_XDMAC_DT_PERID(28))>,
1116                                        <&dma1
1117                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1118                                         | AT91_XDMAC_DT_PERID(29))>;
1119                                 dma-names = "tx", "rx";
1120                                 clocks = <&ssc1_clk>;
1121                                 clock-names = "pclk";
1122                                 status = "disabled";
1123                         };
1124
1125                         tcb1: timer@fc020000 {
1126                                 compatible = "atmel,at91sam9x5-tcb";
1127                                 reg = <0xfc020000 0x100>;
1128                                 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1129                                 clocks = <&tcb1_clk>;
1130                                 clock-names = "t0_clk";
1131                         };
1132
1133                         adc0: adc@fc034000 {
1134                                 compatible = "atmel,at91sam9x5-adc";
1135                                 reg = <0xfc034000 0x100>;
1136                                 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1137                                 pinctrl-names = "default";
1138                                 pinctrl-0 = <
1139                                         /* external trigger is conflict with USBA_VBUS */
1140                                         &pinctrl_adc0_ad0
1141                                         &pinctrl_adc0_ad1
1142                                         &pinctrl_adc0_ad2
1143                                         &pinctrl_adc0_ad3
1144                                         &pinctrl_adc0_ad4
1145                                         >;
1146                                 clocks = <&adc_clk>,
1147                                          <&adc_op_clk>;
1148                                 clock-names = "adc_clk", "adc_op_clk";
1149                                 atmel,adc-channels-used = <0x01f>;
1150                                 atmel,adc-startup-time = <40>;
1151                                 atmel,adc-use-external;
1152                                 atmel,adc-vref = <3000>;
1153                                 atmel,adc-res = <8 10>;
1154                                 atmel,adc-sample-hold-time = <11>;
1155                                 atmel,adc-res-names = "lowres", "highres";
1156                                 atmel,adc-ts-pressure-threshold = <10000>;
1157                                 status = "disabled";
1158
1159                                 trigger@0 {
1160                                         trigger-name = "external-rising";
1161                                         trigger-value = <0x1>;
1162                                         trigger-external;
1163                                 };
1164                                 trigger@1 {
1165                                         trigger-name = "external-falling";
1166                                         trigger-value = <0x2>;
1167                                         trigger-external;
1168                                 };
1169                                 trigger@2 {
1170                                         trigger-name = "external-any";
1171                                         trigger-value = <0x3>;
1172                                         trigger-external;
1173                                 };
1174                                 trigger@3 {
1175                                         trigger-name = "continuous";
1176                                         trigger-value = <0x6>;
1177                                 };
1178                         };
1179
1180                         aes@fc044000 {
1181                                 compatible = "atmel,at91sam9g46-aes";
1182                                 reg = <0xfc044000 0x100>;
1183                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1184                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1185                                         AT91_XDMAC_DT_PERID(41)>,
1186                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1187                                         AT91_XDMAC_DT_PERID(40)>;
1188                                 dma-names = "tx", "rx";
1189                                 clocks = <&aes_clk>;
1190                                 clock-names = "aes_clk";
1191                                 status = "disabled";
1192                         };
1193
1194                         tdes@fc04c000 {
1195                                 compatible = "atmel,at91sam9g46-tdes";
1196                                 reg = <0xfc04c000 0x100>;
1197                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1198                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1199                                         AT91_XDMAC_DT_PERID(42)>,
1200                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1201                                         AT91_XDMAC_DT_PERID(43)>;
1202                                 dma-names = "tx", "rx";
1203                                 clocks = <&tdes_clk>;
1204                                 clock-names = "tdes_clk";
1205                                 status = "disabled";
1206                         };
1207
1208                         sha@fc050000 {
1209                                 compatible = "atmel,at91sam9g46-sha";
1210                                 reg = <0xfc050000 0x100>;
1211                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1212                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1213                                         AT91_XDMAC_DT_PERID(44)>;
1214                                 dma-names = "tx";
1215                                 clocks = <&sha_clk>;
1216                                 clock-names = "sha_clk";
1217                                 status = "disabled";
1218                         };
1219
1220                         rstc@fc068600 {
1221                                 compatible = "atmel,at91sam9g45-rstc";
1222                                 reg = <0xfc068600 0x10>;
1223                         };
1224
1225                         shdwc@fc068610 {
1226                                 compatible = "atmel,at91sam9x5-shdwc";
1227                                 reg = <0xfc068610 0x10>;
1228                         };
1229
1230                         pit: timer@fc068630 {
1231                                 compatible = "atmel,at91sam9260-pit";
1232                                 reg = <0xfc068630 0x10>;
1233                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1234                                 clocks = <&h32ck>;
1235                         };
1236
1237                         watchdog@fc068640 {
1238                                 compatible = "atmel,at91sam9260-wdt";
1239                                 reg = <0xfc068640 0x10>;
1240                                 status = "disabled";
1241                         };
1242
1243                         sckc@fc068650 {
1244                                 compatible = "atmel,at91sam9x5-sckc";
1245                                 reg = <0xfc068650 0x4>;
1246
1247                                 slow_rc_osc: slow_rc_osc {
1248                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1249                                         #clock-cells = <0>;
1250                                         clock-frequency = <32768>;
1251                                         clock-accuracy = <250000000>;
1252                                         atmel,startup-time-usec = <75>;
1253                                 };
1254
1255                                 slow_osc: slow_osc {
1256                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
1257                                         #clock-cells = <0>;
1258                                         clocks = <&slow_xtal>;
1259                                         atmel,startup-time-usec = <1200000>;
1260                                 };
1261
1262                                 clk32k: slowck {
1263                                         compatible = "atmel,at91sam9x5-clk-slow";
1264                                         #clock-cells = <0>;
1265                                         clocks = <&slow_rc_osc &slow_osc>;
1266                                 };
1267                         };
1268
1269                         rtc@fc0686b0 {
1270                                 compatible = "atmel,at91rm9200-rtc";
1271                                 reg = <0xfc0686b0 0x30>;
1272                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1273                         };
1274
1275                         dbgu: serial@fc069000 {
1276                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1277                                 reg = <0xfc069000 0x200>;
1278                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1279                                 pinctrl-names = "default";
1280                                 pinctrl-0 = <&pinctrl_dbgu>;
1281                                 clocks = <&dbgu_clk>;
1282                                 clock-names = "usart";
1283                                 status = "disabled";
1284                         };
1285
1286
1287                         pinctrl@fc06a000 {
1288                                 #address-cells = <1>;
1289                                 #size-cells = <1>;
1290                                 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1291                                 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1292                                 /* WARNING: revisit as pin spec has changed */
1293                                 atmel,mux-mask = <
1294                                         /*   A          B          C  */
1295                                         0xffffffff 0x3ffcfe7c 0x1c010101        /* pioA */
1296                                         0x7fffffff 0xfffccc3a 0x3f00cc3a        /* pioB */
1297                                         0xffffffff 0x3ff83fff 0xff00ffff        /* pioC */
1298                                         0x00000000 0x00000000 0x00000000        /* pioD */
1299                                         0xffffffff 0x7fffffff 0x76fff1bf        /* pioE */
1300                                         >;
1301
1302                                 pioA: gpio@fc06a000 {
1303                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1304                                         reg = <0xfc06a000 0x100>;
1305                                         interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1306                                         #gpio-cells = <2>;
1307                                         gpio-controller;
1308                                         interrupt-controller;
1309                                         #interrupt-cells = <2>;
1310                                         clocks = <&pioA_clk>;
1311                                 };
1312
1313                                 pioB: gpio@fc06b000 {
1314                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1315                                         reg = <0xfc06b000 0x100>;
1316                                         interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1317                                         #gpio-cells = <2>;
1318                                         gpio-controller;
1319                                         interrupt-controller;
1320                                         #interrupt-cells = <2>;
1321                                         clocks = <&pioB_clk>;
1322                                 };
1323
1324                                 pioC: gpio@fc06c000 {
1325                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1326                                         reg = <0xfc06c000 0x100>;
1327                                         interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1328                                         #gpio-cells = <2>;
1329                                         gpio-controller;
1330                                         interrupt-controller;
1331                                         #interrupt-cells = <2>;
1332                                         clocks = <&pioC_clk>;
1333                                 };
1334
1335                                 pioD: gpio@fc068000 {
1336                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1337                                         reg = <0xfc068000 0x100>;
1338                                         interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1339                                         #gpio-cells = <2>;
1340                                         gpio-controller;
1341                                         interrupt-controller;
1342                                         #interrupt-cells = <2>;
1343                                         clocks = <&pioD_clk>;
1344                                         status = "disabled";
1345                                 };
1346
1347                                 pioE: gpio@fc06d000 {
1348                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1349                                         reg = <0xfc06d000 0x100>;
1350                                         interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1351                                         #gpio-cells = <2>;
1352                                         gpio-controller;
1353                                         interrupt-controller;
1354                                         #interrupt-cells = <2>;
1355                                         clocks = <&pioE_clk>;
1356                                 };
1357
1358                                 /* pinctrl pin settings */
1359                                 adc0 {
1360                                         pinctrl_adc0_adtrg: adc0_adtrg {
1361                                                 atmel,pins =
1362                                                         <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1363                                         };
1364
1365                                         pinctrl_adc0_ad0: adc0_ad0 {
1366                                                 atmel,pins =
1367                                                         <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1368                                         };
1369
1370                                         pinctrl_adc0_ad1: adc0_ad1 {
1371                                                 atmel,pins =
1372                                                         <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1373                                         };
1374
1375                                         pinctrl_adc0_ad2: adc0_ad2 {
1376                                                 atmel,pins =
1377                                                         <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1378                                         };
1379
1380                                         pinctrl_adc0_ad3: adc0_ad3 {
1381                                                 atmel,pins =
1382                                                         <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1383                                         };
1384
1385                                         pinctrl_adc0_ad4: adc0_ad4 {
1386                                                 atmel,pins =
1387                                                         <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1388                                         };
1389                                 };
1390
1391                                 dbgu {
1392                                         pinctrl_dbgu: dbgu-0 {
1393                                                 atmel,pins =
1394                                                         <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,     /* conflicts with D14 and TDI */
1395                                                         <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;  /* conflicts with D15 and TDO */
1396                                         };
1397                                 };
1398
1399                                 i2c0 {
1400                                         pinctrl_i2c0: i2c0-0 {
1401                                                 atmel,pins =
1402                                                         <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1403                                                          AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1404                                         };
1405                                 };
1406
1407                                 i2c1 {
1408                                         pinctrl_i2c1: i2c1-0 {
1409                                                 atmel,pins =
1410                                                         <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* TWD1, conflicts with UART0 RX and DIBP */
1411                                                          AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1412                                         };
1413                                 };
1414
1415                                 i2c2 {
1416                                         pinctrl_i2c2: i2c2-0 {
1417                                                 atmel,pins =
1418                                                         <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* TWD2, conflicts with RD0 and PWML1 */
1419                                                          AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1420                                         };
1421                                 };
1422
1423                                 isi {
1424                                         pinctrl_isi_data_0_7: isi-0-data-0-7 {
1425                                                 atmel,pins =
1426                                                         <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D0 */
1427                                                          AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D1 */
1428                                                          AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D2 */
1429                                                          AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D3 */
1430                                                          AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D4 */
1431                                                          AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D5 */
1432                                                          AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D6 */
1433                                                          AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D7 */
1434                                                          AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_PCK, conflict with G0_RXCK */
1435                                                          AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_VSYNC */
1436                                                          AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1437                                         };
1438
1439                                         pinctrl_isi_data_8_9: isi-0-data-8-9 {
1440                                                 atmel,pins =
1441                                                         <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1442                                                          AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1443                                         };
1444
1445                                         pinctrl_isi_data_10_11: isi-0-data-10-11 {
1446                                                 atmel,pins =
1447                                                         <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1448                                                          AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1449                                         };
1450                                 };
1451
1452                                 lcd {
1453                                         pinctrl_lcd_base: lcd-base-0 {
1454                                                 atmel,pins =
1455                                                         <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
1456                                                          AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
1457                                                          AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
1458                                                          AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1459                                         };
1460
1461                                         pinctrl_lcd_pwm: lcd-pwm-0 {
1462                                                 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
1463                                         };
1464
1465                                         pinctrl_lcd_rgb444: lcd-rgb-0 {
1466                                                 atmel,pins =
1467                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1468                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1469                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1470                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1471                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1472                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1473                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1474                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1475                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1476                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1477                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1478                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1479                                         };
1480
1481                                         pinctrl_lcd_rgb565: lcd-rgb-1 {
1482                                                 atmel,pins =
1483                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1484                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1485                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1486                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1487                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1488                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1489                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1490                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1491                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1492                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1493                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1494                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1495                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1496                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1497                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1498                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1499                                         };
1500
1501                                         pinctrl_lcd_rgb666: lcd-rgb-2 {
1502                                                 atmel,pins =
1503                                                         <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1504                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1505                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1506                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1507                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1508                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1509                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1510                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1511                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1512                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1513                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1514                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1515                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1516                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1517                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1518                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1519                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1520                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1521                                         };
1522
1523                                         pinctrl_lcd_rgb777: lcd-rgb-3 {
1524                                                 atmel,pins =
1525                                                          /* LCDDAT0 conflicts with TMS */
1526                                                         <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1527                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1528                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1529                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1530                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1531                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1532                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1533                                                          /* LCDDAT8 conflicts with TCK */
1534                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1535                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1536                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1537                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1538                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1539                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1540                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1541                                                          /* LCDDAT16 conflicts with NTRST */
1542                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
1543                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1544                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1545                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1546                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1547                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1548                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1549                                         };
1550
1551                                         pinctrl_lcd_rgb888: lcd-rgb-4 {
1552                                                 atmel,pins =
1553                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1554                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1555                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1556                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1557                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1558                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1559                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1560                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1561                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1562                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1563                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1564                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1565                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1566                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1567                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1568                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1569                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
1570                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
1571                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1572                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1573                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1574                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1575                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1576                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1577                                         };
1578                                 };
1579
1580                                 macb0 {
1581                                         pinctrl_macb0_rmii: macb0_rmii-0 {
1582                                                 atmel,pins =
1583                                                         <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX0 */
1584                                                          AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX1 */
1585                                                          AT91_PIOB  8 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX0 */
1586                                                          AT91_PIOB  9 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX1 */
1587                                                          AT91_PIOB  6 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXDV */
1588                                                          AT91_PIOB  7 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXER */
1589                                                          AT91_PIOB  2 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXEN */
1590                                                          AT91_PIOB  0 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXCK */
1591                                                          AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDC */
1592                                                          AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDIO */
1593                                                         >;
1594                                         };
1595                                 };
1596
1597                                 mmc0 {
1598                                         pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1599                                                 atmel,pins =
1600                                                         <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1601                                                          AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1602                                                          AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1603                                                         >;
1604                                         };
1605
1606                                         pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1607                                                 atmel,pins =
1608                                                         <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1609                                                          AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1610                                                          AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1611                                                         >;
1612                                         };
1613                                 };
1614
1615                                 mmc1 {
1616                                         pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1617                                                 atmel,pins =
1618                                                         <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE           /* MCI1_CK */
1619                                                          AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_CDA */
1620                                                          AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA0 */
1621                                                         >;
1622                                         };
1623
1624                                         pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1625                                                 atmel,pins =
1626                                                         <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA1 */
1627                                                          AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA2 */
1628                                                          AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA3 */
1629                                                         >;
1630                                         };
1631                                 };
1632
1633                                 nand0 {
1634                                         pinctrl_nand: nand-0 {
1635                                                 atmel,pins =
1636                                                         <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC13 periph A Read Enable */
1637                                                          AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC14 periph A Write Enable */
1638
1639                                                          AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC17 ALE */
1640                                                          AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC18 CLE */
1641
1642                                                          AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC15 NCS3/Chip Enable */
1643                                                          AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC16 NANDRDY */
1644                                                          AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC5 Data bit 0 */
1645                                                          AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 Data bit 1 */
1646                                                          AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 Data bit 2 */
1647                                                          AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 Data bit 3 */
1648                                                          AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC9 Data bit 4 */
1649                                                          AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC10 Data bit 5 */
1650                                                          AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC11 periph A Data bit 6 */
1651                                                          AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1652                                         };
1653                                 };
1654
1655                                 spi0 {
1656                                         pinctrl_spi0: spi0-0 {
1657                                                 atmel,pins =
1658                                                         <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MISO */
1659                                                          AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MOSI */
1660                                                          AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_SPCK */
1661                                                         >;
1662                                         };
1663                                 };
1664
1665                                 spi1 {
1666                                         pinctrl_spi1: spi1-0 {
1667                                                 atmel,pins = <
1668                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MISO */
1669                                                         AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MOSI */
1670                                                         AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_SPCK */
1671                                                 >;
1672                                         };
1673                                 };
1674
1675                                 ssc0 {
1676                                         pinctrl_ssc0_tx: ssc0_tx {
1677                                                 atmel,pins =
1678                                                         <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK0 */
1679                                                          AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF0 */
1680                                                          AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1681                                         };
1682
1683                                         pinctrl_ssc0_rx: ssc0_rx {
1684                                                 atmel,pins =
1685                                                         <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK0 */
1686                                                          AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF0 */
1687                                                          AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1688                                         };
1689                                 };
1690
1691                                 ssc1 {
1692                                         pinctrl_ssc1_tx: ssc1_tx {
1693                                                 atmel,pins =
1694                                                         <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK1 */
1695                                                          AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF1 */
1696                                                          AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1697                                         };
1698
1699                                         pinctrl_ssc1_rx: ssc1_rx {
1700                                                 atmel,pins =
1701                                                         <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK1 */
1702                                                          AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF1 */
1703                                                          AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1704                                         };
1705                                 };
1706
1707                                 usart2 {
1708                                         pinctrl_usart2: usart2-0 {
1709                                                 atmel,pins =
1710                                                         <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE            /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1711                                                          AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP         /* TXD - conflicts with G0_COL, PCK2 */
1712                                                         >;
1713                                         };
1714
1715                                         pinctrl_usart2_rts: usart2_rts-0 {
1716                                                 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with G0_RX3, PWMH1 */
1717                                         };
1718
1719                                         pinctrl_usart2_cts: usart2_cts-0 {
1720                                                 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;     /* conflicts with G0_TXER, ISI_VSYNC */
1721                                         };
1722                                 };
1723
1724                                 usart0 {
1725                                         pinctrl_usart0: usart0-0 {
1726                                                 atmel,pins = <
1727                                                         AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP         /* RXD */
1728                                                         AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE            /* TXD */
1729                                                 >;
1730                                         };
1731
1732                                         pinctrl_usart0_rts: usart0_rts-0 {
1733                                                 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1734                                         };
1735
1736                                         pinctrl_usart0_cts: usart0_cts-0 {
1737                                                 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1738                                         };
1739                                 };
1740
1741                                 usart1 {
1742                                         pinctrl_usart1: usart1-0 {
1743                                                 atmel,pins = <
1744                                                         AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP         /* RXD */
1745                                                         AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE            /* TXD */
1746                                                 >;
1747                                         };
1748
1749                                         pinctrl_usart1_rts: usart1_rts-0 {
1750                                                 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1751                                         };
1752
1753                                         pinctrl_usart1_cts: usart1_cts-0 {
1754                                                 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1755                                         };
1756                                 };
1757
1758                                 usart3 {
1759                                         pinctrl_usart3: usart3-0 {
1760                                                 atmel,pins =
1761                                                         <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1762                                                          AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1763                                                         >;
1764                                         };
1765                                 };
1766
1767                                 usart4 {
1768                                         pinctrl_usart4: usart4-0 {
1769                                                 atmel,pins =
1770                                                         <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1771                                                          AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1772                                                         >;
1773                                         };
1774
1775                                         pinctrl_usart4_rts: usart4_rts-0 {
1776                                                 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with NWAIT, A19 */
1777                                         };
1778
1779                                         pinctrl_usart4_cts: usart4_cts-0 {
1780                                                 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>;     /* conflicts with A0/NBS0, MCI0_CDB */
1781                                         };
1782                                 };
1783                         };
1784
1785                         aic: interrupt-controller@fc06e000 {
1786                                 #interrupt-cells = <3>;
1787                                 compatible = "atmel,sama5d4-aic";
1788                                 interrupt-controller;
1789                                 reg = <0xfc06e000 0x200>;
1790                                 atmel,external-irqs = <56>;
1791                         };
1792                 };
1793         };
1794 };