2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/clock/at91.h>
48 #include <dt-bindings/dma/at91.h>
49 #include <dt-bindings/pinctrl/at91.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/gpio/gpio.h>
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
86 compatible = "arm,cortex-a5";
88 next-level-cache = <&L2>;
93 reg = <0x20000000 0x20000000>;
97 slow_xtal: slow_xtal {
98 compatible = "fixed-clock";
100 clock-frequency = <0>;
103 main_xtal: main_xtal {
104 compatible = "fixed-clock";
106 clock-frequency = <0>;
109 adc_op_clk: adc_op_clk{
110 compatible = "fixed-clock";
112 clock-frequency = <1000000>;
116 ns_sram: sram@00210000 {
117 compatible = "mmio-sram";
118 reg = <0x00210000 0x10000>;
122 compatible = "simple-bus";
123 #address-cells = <1>;
127 usb0: gadget@00400000 {
128 #address-cells = <1>;
130 compatible = "atmel,sama5d3-udc";
131 reg = <0x00400000 0x100000
133 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
134 clocks = <&udphs_clk>, <&utmi>;
135 clock-names = "pclk", "hclk";
140 atmel,fifo-size = <64>;
141 atmel,nb-banks = <1>;
146 atmel,fifo-size = <1024>;
147 atmel,nb-banks = <3>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <3>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <2>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
194 atmel,fifo-size = <1024>;
195 atmel,nb-banks = <2>;
202 atmel,fifo-size = <1024>;
203 atmel,nb-banks = <2>;
209 atmel,fifo-size = <1024>;
210 atmel,nb-banks = <2>;
216 atmel,fifo-size = <1024>;
217 atmel,nb-banks = <2>;
223 atmel,fifo-size = <1024>;
224 atmel,nb-banks = <2>;
230 atmel,fifo-size = <1024>;
231 atmel,nb-banks = <2>;
237 atmel,fifo-size = <1024>;
238 atmel,nb-banks = <2>;
244 atmel,fifo-size = <1024>;
245 atmel,nb-banks = <2>;
251 atmel,fifo-size = <1024>;
252 atmel,nb-banks = <2>;
257 usb1: ohci@00500000 {
258 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
259 reg = <0x00500000 0x100000>;
260 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
261 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
262 clock-names = "ohci_clk", "hclk", "uhpck";
266 usb2: ehci@00600000 {
267 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
268 reg = <0x00600000 0x100000>;
269 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
270 clocks = <&utmi>, <&uhphs_clk>;
271 clock-names = "usb_clk", "ehci_clk";
275 L2: cache-controller@00a00000 {
276 compatible = "arm,pl310-cache";
277 reg = <0x00a00000 0x1000>;
278 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
283 nand0: nand@80000000 {
284 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
285 #address-cells = <1>;
288 reg = < 0x80000000 0x08000000 /* EBI CS3 */
289 0xfc05c070 0x00000490 /* SMC PMECC regs */
290 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
292 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
293 atmel,nand-addr-offset = <21>;
294 atmel,nand-cmd-offset = <22>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_nand>;
301 compatible = "atmel,sama5d3-nfc";
302 #address-cells = <1>;
305 0x90000000 0x08000000 /* NFC Command Registers */
306 0xfc05c000 0x00000070 /* NFC HSMC regs */
307 0x00100000 0x00100000 /* NFC SRAM banks */
309 clocks = <&hsmc_clk>;
315 compatible = "simple-bus";
316 #address-cells = <1>;
320 hlcdc: hlcdc@f0000000 {
321 compatible = "atmel,sama5d4-hlcdc";
322 reg = <0xf0000000 0x4000>;
323 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
324 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
325 clock-names = "periph_clk","sys_clk", "slow_clk";
328 hlcdc-display-controller {
329 compatible = "atmel,hlcdc-display-controller";
330 #address-cells = <1>;
334 #address-cells = <1>;
340 hlcdc_pwm: hlcdc-pwm {
341 compatible = "atmel,hlcdc-pwm";
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_lcd_pwm>;
348 dma1: dma-controller@f0004000 {
349 compatible = "atmel,sama5d4-dma";
350 reg = <0xf0004000 0x200>;
351 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
353 clocks = <&dma1_clk>;
354 clock-names = "dma_clk";
358 compatible = "atmel,at91sam9g45-isi";
359 reg = <0xf0008000 0x4000>;
360 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_isi_data_0_7>;
364 clock-names = "isi_clk";
367 #address-cells = <1>;
372 ramc0: ramc@f0010000 {
373 compatible = "atmel,sama5d3-ddramc";
374 reg = <0xf0010000 0x200>;
375 clocks = <&ddrck>, <&mpddr_clk>;
376 clock-names = "ddrck", "mpddr";
379 dma0: dma-controller@f0014000 {
380 compatible = "atmel,sama5d4-dma";
381 reg = <0xf0014000 0x200>;
382 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
384 clocks = <&dma0_clk>;
385 clock-names = "dma_clk";
389 compatible = "atmel,sama5d3-pmc";
390 reg = <0xf0018000 0x120>;
391 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
392 interrupt-controller;
393 #address-cells = <1>;
395 #interrupt-cells = <1>;
397 main_rc_osc: main_rc_osc {
398 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
400 interrupt-parent = <&pmc>;
401 interrupts = <AT91_PMC_MOSCRCS>;
402 clock-frequency = <12000000>;
403 clock-accuracy = <100000000>;
407 compatible = "atmel,at91rm9200-clk-main-osc";
409 interrupt-parent = <&pmc>;
410 interrupts = <AT91_PMC_MOSCS>;
411 clocks = <&main_xtal>;
415 compatible = "atmel,at91sam9x5-clk-main";
417 interrupt-parent = <&pmc>;
418 interrupts = <AT91_PMC_MOSCSELS>;
419 clocks = <&main_rc_osc &main_osc>;
423 compatible = "atmel,sama5d3-clk-pll";
425 interrupt-parent = <&pmc>;
426 interrupts = <AT91_PMC_LOCKA>;
429 atmel,clk-input-range = <12000000 12000000>;
430 #atmel,pll-clk-output-range-cells = <4>;
431 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
435 compatible = "atmel,at91sam9x5-clk-plldiv";
441 compatible = "atmel,at91sam9x5-clk-utmi";
443 interrupt-parent = <&pmc>;
444 interrupts = <AT91_PMC_LOCKU>;
449 compatible = "atmel,at91sam9x5-clk-master";
451 interrupt-parent = <&pmc>;
452 interrupts = <AT91_PMC_MCKRDY>;
453 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
454 atmel,clk-output-range = <125000000 177000000>;
455 atmel,clk-divisors = <1 2 4 3>;
460 compatible = "atmel,sama5d4-clk-h32mx";
465 compatible = "atmel,at91sam9x5-clk-usb";
467 clocks = <&plladiv>, <&utmi>;
471 compatible = "atmel,at91sam9x5-clk-programmable";
472 #address-cells = <1>;
474 interrupt-parent = <&pmc>;
475 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
480 interrupts = <AT91_PMC_PCKRDY(0)>;
486 interrupts = <AT91_PMC_PCKRDY(1)>;
492 interrupts = <AT91_PMC_PCKRDY(2)>;
497 compatible = "atmel,at91sam9x5-clk-smd";
499 clocks = <&plladiv>, <&utmi>;
503 compatible = "atmel,at91rm9200-clk-system";
504 #address-cells = <1>;
557 compatible = "atmel,at91sam9x5-clk-peripheral";
558 #address-cells = <1>;
567 usart0_clk: usart0_clk {
572 usart1_clk: usart1_clk {
597 matrix1_clk: matrix1_clk {
627 uart0_clk: uart0_clk {
632 uart1_clk: uart1_clk {
637 usart2_clk: usart2_clk {
642 usart3_clk: usart3_clk {
647 usart4_clk: usart4_clk {
722 uhphs_clk: uhphs_clk {
727 udphs_clk: udphs_clk {
747 macb0_clk: macb0_clk {
752 macb1_clk: macb1_clk {
762 securam_clk: securam_clk {
784 compatible = "atmel,at91sam9x5-clk-peripheral";
785 #address-cells = <1>;
794 cpkcc_clk: cpkcc_clk {
804 mpddr_clk: mpddr_clk {
809 matrix0_clk: matrix0_clk {
837 compatible = "atmel,hsmci";
838 reg = <0xf8000000 0x600>;
839 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
841 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
842 | AT91_XDMAC_DT_PERID(0))>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
847 #address-cells = <1>;
849 clocks = <&mci0_clk>;
850 clock-names = "mci_clk";
853 uart0: serial@f8004000 {
854 compatible = "atmel,at91sam9260-usart";
855 reg = <0xf8004000 0x100>;
856 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
858 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
859 | AT91_XDMAC_DT_PERID(22))>,
861 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
862 | AT91_XDMAC_DT_PERID(23))>;
863 dma-names = "tx", "rx";
864 pinctrl-names = "default";
865 pinctrl-0 = <&pinctrl_uart0>;
866 clocks = <&uart0_clk>;
867 clock-names = "usart";
872 compatible = "atmel,at91sam9g45-ssc";
873 reg = <0xf8008000 0x4000>;
874 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
875 pinctrl-names = "default";
876 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
878 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
879 | AT91_XDMAC_DT_PERID(26))>,
881 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
882 | AT91_XDMAC_DT_PERID(27))>;
883 dma-names = "tx", "rx";
884 clocks = <&ssc0_clk>;
885 clock-names = "pclk";
890 compatible = "atmel,sama5d3-pwm";
891 reg = <0xf800c000 0x300>;
892 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
899 #address-cells = <1>;
901 compatible = "atmel,at91rm9200-spi";
902 reg = <0xf8010000 0x100>;
903 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
905 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
906 | AT91_XDMAC_DT_PERID(10))>,
908 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
909 | AT91_XDMAC_DT_PERID(11))>;
910 dma-names = "tx", "rx";
911 pinctrl-names = "default";
912 pinctrl-0 = <&pinctrl_spi0>;
913 clocks = <&spi0_clk>;
914 clock-names = "spi_clk";
919 compatible = "atmel,at91sam9x5-i2c";
920 reg = <0xf8014000 0x4000>;
921 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
923 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
924 | AT91_XDMAC_DT_PERID(2))>,
926 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
927 | AT91_XDMAC_DT_PERID(3))>;
928 dma-names = "tx", "rx";
929 pinctrl-names = "default";
930 pinctrl-0 = <&pinctrl_i2c0>;
931 #address-cells = <1>;
933 clocks = <&twi0_clk>;
938 compatible = "atmel,at91sam9x5-i2c";
939 reg = <0xf8018000 0x4000>;
940 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
942 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
943 AT91_XDMAC_DT_PERID(4)>,
945 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
946 AT91_XDMAC_DT_PERID(5)>;
947 dma-names = "tx", "rx";
948 pinctrl-names = "default";
949 pinctrl-0 = <&pinctrl_i2c1>;
950 #address-cells = <1>;
952 clocks = <&twi1_clk>;
956 tcb0: timer@f801c000 {
957 compatible = "atmel,at91sam9x5-tcb";
958 reg = <0xf801c000 0x100>;
959 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
960 clocks = <&tcb0_clk>;
961 clock-names = "t0_clk";
964 macb0: ethernet@f8020000 {
965 compatible = "atmel,sama5d4-gem";
966 reg = <0xf8020000 0x100>;
967 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&pinctrl_macb0_rmii>;
970 #address-cells = <1>;
972 clocks = <&macb0_clk>, <&macb0_clk>;
973 clock-names = "hclk", "pclk";
978 compatible = "atmel,at91sam9x5-i2c";
979 reg = <0xf8024000 0x4000>;
980 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
982 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
983 | AT91_XDMAC_DT_PERID(6))>,
985 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
986 | AT91_XDMAC_DT_PERID(7))>;
987 dma-names = "tx", "rx";
988 pinctrl-names = "default";
989 pinctrl-0 = <&pinctrl_i2c2>;
990 #address-cells = <1>;
992 clocks = <&twi2_clk>;
997 compatible = "atmel,sama5d4-sfr", "syscon";
998 reg = <0xf8028000 0x60>;
1001 usart0: serial@f802c000 {
1002 compatible = "atmel,at91sam9260-usart";
1003 reg = <0xf802c000 0x100>;
1004 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
1006 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1007 | AT91_XDMAC_DT_PERID(36))>,
1009 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1010 | AT91_XDMAC_DT_PERID(37))>;
1011 dma-names = "tx", "rx";
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
1014 clocks = <&usart0_clk>;
1015 clock-names = "usart";
1016 status = "disabled";
1019 usart1: serial@f8030000 {
1020 compatible = "atmel,at91sam9260-usart";
1021 reg = <0xf8030000 0x100>;
1022 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1024 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1025 | AT91_XDMAC_DT_PERID(38))>,
1027 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1028 | AT91_XDMAC_DT_PERID(39))>;
1029 dma-names = "tx", "rx";
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1032 clocks = <&usart1_clk>;
1033 clock-names = "usart";
1034 status = "disabled";
1037 mmc1: mmc@fc000000 {
1038 compatible = "atmel,hsmci";
1039 reg = <0xfc000000 0x600>;
1040 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1042 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1043 | AT91_XDMAC_DT_PERID(1))>;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1047 status = "disabled";
1048 #address-cells = <1>;
1050 clocks = <&mci1_clk>;
1051 clock-names = "mci_clk";
1054 uart1: serial@fc004000 {
1055 compatible = "atmel,at91sam9260-usart";
1056 reg = <0xfc004000 0x100>;
1057 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
1059 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1060 | AT91_XDMAC_DT_PERID(24))>,
1062 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1063 | AT91_XDMAC_DT_PERID(25))>;
1064 dma-names = "tx", "rx";
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&pinctrl_uart1>;
1067 clocks = <&uart1_clk>;
1068 clock-names = "usart";
1069 status = "disabled";
1072 usart2: serial@fc008000 {
1073 compatible = "atmel,at91sam9260-usart";
1074 reg = <0xfc008000 0x100>;
1075 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1077 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1078 | AT91_XDMAC_DT_PERID(16))>,
1080 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1081 | AT91_XDMAC_DT_PERID(17))>;
1082 dma-names = "tx", "rx";
1083 pinctrl-names = "default";
1084 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1085 clocks = <&usart2_clk>;
1086 clock-names = "usart";
1087 status = "disabled";
1090 usart3: serial@fc00c000 {
1091 compatible = "atmel,at91sam9260-usart";
1092 reg = <0xfc00c000 0x100>;
1093 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1095 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1096 | AT91_XDMAC_DT_PERID(18))>,
1098 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1099 | AT91_XDMAC_DT_PERID(19))>;
1100 dma-names = "tx", "rx";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&pinctrl_usart3>;
1103 clocks = <&usart3_clk>;
1104 clock-names = "usart";
1105 status = "disabled";
1108 usart4: serial@fc010000 {
1109 compatible = "atmel,at91sam9260-usart";
1110 reg = <0xfc010000 0x100>;
1111 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1113 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1114 | AT91_XDMAC_DT_PERID(20))>,
1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1117 | AT91_XDMAC_DT_PERID(21))>;
1118 dma-names = "tx", "rx";
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&pinctrl_usart4>;
1121 clocks = <&usart4_clk>;
1122 clock-names = "usart";
1123 status = "disabled";
1126 ssc1: ssc@fc014000 {
1127 compatible = "atmel,at91sam9g45-ssc";
1128 reg = <0xfc014000 0x4000>;
1129 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1133 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1134 | AT91_XDMAC_DT_PERID(28))>,
1136 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1137 | AT91_XDMAC_DT_PERID(29))>;
1138 dma-names = "tx", "rx";
1139 clocks = <&ssc1_clk>;
1140 clock-names = "pclk";
1141 status = "disabled";
1144 spi1: spi@fc018000 {
1145 #address-cells = <1>;
1147 compatible = "atmel,at91rm9200-spi";
1148 reg = <0xfc018000 0x100>;
1149 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
1151 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1152 | AT91_XDMAC_DT_PERID(12))>,
1154 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1155 | AT91_XDMAC_DT_PERID(13))>;
1156 dma-names = "tx", "rx";
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&pinctrl_spi1>;
1159 clocks = <&spi1_clk>;
1160 clock-names = "spi_clk";
1161 status = "disabled";
1164 spi2: spi@fc01c000 {
1165 #address-cells = <1>;
1167 compatible = "atmel,at91rm9200-spi";
1168 reg = <0xfc01c000 0x100>;
1169 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
1171 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1172 | AT91_XDMAC_DT_PERID(14))>,
1174 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1175 | AT91_XDMAC_DT_PERID(15))>;
1176 dma-names = "tx", "rx";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&pinctrl_spi2>;
1179 clocks = <&spi2_clk>;
1180 clock-names = "spi_clk";
1181 status = "disabled";
1184 tcb1: timer@fc020000 {
1185 compatible = "atmel,at91sam9x5-tcb";
1186 reg = <0xfc020000 0x100>;
1187 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1188 clocks = <&tcb1_clk>;
1189 clock-names = "t0_clk";
1192 adc0: adc@fc034000 {
1193 compatible = "atmel,at91sam9x5-adc";
1194 reg = <0xfc034000 0x100>;
1195 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1196 clocks = <&adc_clk>,
1198 clock-names = "adc_clk", "adc_op_clk";
1199 atmel,adc-channels-used = <0x01f>;
1200 atmel,adc-startup-time = <40>;
1201 atmel,adc-use-external-triggers;
1202 atmel,adc-vref = <3000>;
1203 atmel,adc-res = <8 10>;
1204 atmel,adc-sample-hold-time = <11>;
1205 atmel,adc-res-names = "lowres", "highres";
1206 atmel,adc-ts-pressure-threshold = <10000>;
1207 status = "disabled";
1210 trigger-name = "external-rising";
1211 trigger-value = <0x1>;
1215 trigger-name = "external-falling";
1216 trigger-value = <0x2>;
1220 trigger-name = "external-any";
1221 trigger-value = <0x3>;
1225 trigger-name = "continuous";
1226 trigger-value = <0x6>;
1231 compatible = "atmel,at91sam9g46-aes";
1232 reg = <0xfc044000 0x100>;
1233 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1234 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1235 | AT91_XDMAC_DT_PERID(41))>,
1236 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1237 | AT91_XDMAC_DT_PERID(40))>;
1238 dma-names = "tx", "rx";
1239 clocks = <&aes_clk>;
1240 clock-names = "aes_clk";
1241 status = "disabled";
1245 compatible = "atmel,at91sam9g46-tdes";
1246 reg = <0xfc04c000 0x100>;
1247 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1248 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1249 | AT91_XDMAC_DT_PERID(42))>,
1250 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1251 | AT91_XDMAC_DT_PERID(43))>;
1252 dma-names = "tx", "rx";
1253 clocks = <&tdes_clk>;
1254 clock-names = "tdes_clk";
1255 status = "disabled";
1259 compatible = "atmel,at91sam9g46-sha";
1260 reg = <0xfc050000 0x100>;
1261 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1262 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1263 | AT91_XDMAC_DT_PERID(44))>;
1265 clocks = <&sha_clk>;
1266 clock-names = "sha_clk";
1267 status = "disabled";
1271 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1272 reg = <0xfc068600 0x10>;
1276 compatible = "atmel,at91sam9x5-shdwc";
1277 reg = <0xfc068610 0x10>;
1280 pit: timer@fc068630 {
1281 compatible = "atmel,at91sam9260-pit";
1282 reg = <0xfc068630 0x10>;
1283 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1288 compatible = "atmel,at91sam9260-wdt";
1289 reg = <0xfc068640 0x10>;
1290 status = "disabled";
1294 compatible = "atmel,at91sam9x5-sckc";
1295 reg = <0xfc068650 0x4>;
1297 slow_rc_osc: slow_rc_osc {
1298 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1300 clock-frequency = <32768>;
1301 clock-accuracy = <250000000>;
1302 atmel,startup-time-usec = <75>;
1305 slow_osc: slow_osc {
1306 compatible = "atmel,at91sam9x5-clk-slow-osc";
1308 clocks = <&slow_xtal>;
1309 atmel,startup-time-usec = <1200000>;
1313 compatible = "atmel,at91sam9x5-clk-slow";
1315 clocks = <&slow_rc_osc &slow_osc>;
1320 compatible = "atmel,at91rm9200-rtc";
1321 reg = <0xfc0686b0 0x30>;
1322 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1325 dbgu: serial@fc069000 {
1326 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1327 reg = <0xfc069000 0x200>;
1328 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&pinctrl_dbgu>;
1331 clocks = <&dbgu_clk>;
1332 clock-names = "usart";
1333 status = "disabled";
1338 #address-cells = <1>;
1340 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1341 ranges = <0xfc068000 0xfc068000 0x100
1342 0xfc06a000 0xfc06a000 0x4000>;
1343 /* WARNING: revisit as pin spec has changed */
1346 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1347 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1348 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1349 0x00000000 0x00000000 0x00000000 /* pioD */
1350 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1353 pioA: gpio@fc06a000 {
1354 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1355 reg = <0xfc06a000 0x100>;
1356 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1359 interrupt-controller;
1360 #interrupt-cells = <2>;
1361 clocks = <&pioA_clk>;
1364 pioB: gpio@fc06b000 {
1365 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1366 reg = <0xfc06b000 0x100>;
1367 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1370 interrupt-controller;
1371 #interrupt-cells = <2>;
1372 clocks = <&pioB_clk>;
1375 pioC: gpio@fc06c000 {
1376 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1377 reg = <0xfc06c000 0x100>;
1378 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1381 interrupt-controller;
1382 #interrupt-cells = <2>;
1383 clocks = <&pioC_clk>;
1386 pioD: gpio@fc068000 {
1387 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1388 reg = <0xfc068000 0x100>;
1389 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1392 interrupt-controller;
1393 #interrupt-cells = <2>;
1394 clocks = <&pioD_clk>;
1395 status = "disabled";
1398 pioE: gpio@fc06d000 {
1399 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1400 reg = <0xfc06d000 0x100>;
1401 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1404 interrupt-controller;
1405 #interrupt-cells = <2>;
1406 clocks = <&pioE_clk>;
1409 /* pinctrl pin settings */
1411 pinctrl_adc0_adtrg: adc0_adtrg {
1413 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1415 pinctrl_adc0_ad0: adc0_ad0 {
1417 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1419 pinctrl_adc0_ad1: adc0_ad1 {
1421 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1423 pinctrl_adc0_ad2: adc0_ad2 {
1425 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1427 pinctrl_adc0_ad3: adc0_ad3 {
1429 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1431 pinctrl_adc0_ad4: adc0_ad4 {
1433 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1438 pinctrl_dbgu: dbgu-0 {
1440 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1441 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1446 pinctrl_i2c0: i2c0-0 {
1448 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1449 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1454 pinctrl_i2c1: i2c1-0 {
1456 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1457 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1462 pinctrl_i2c2: i2c2-0 {
1464 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1465 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1470 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1472 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1473 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1474 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1475 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1476 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1477 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1478 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1479 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1480 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1481 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1482 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1484 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1486 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1487 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1489 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1491 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1492 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1497 pinctrl_lcd_base: lcd-base-0 {
1499 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1500 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1501 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1502 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1504 pinctrl_lcd_pwm: lcd-pwm-0 {
1505 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1507 pinctrl_lcd_rgb444: lcd-rgb-0 {
1509 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1510 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1511 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1512 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1513 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1514 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1515 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1516 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1517 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1518 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1519 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1520 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1522 pinctrl_lcd_rgb565: lcd-rgb-1 {
1524 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1525 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1526 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1527 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1528 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1529 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1530 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1531 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1532 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1533 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1534 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1535 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1536 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1537 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1538 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1539 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1541 pinctrl_lcd_rgb666: lcd-rgb-2 {
1543 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1544 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1545 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1546 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1547 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1548 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1549 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1550 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1551 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1552 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1553 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1554 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1555 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1556 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1557 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1558 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1559 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1560 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1562 pinctrl_lcd_rgb777: lcd-rgb-3 {
1564 /* LCDDAT0 conflicts with TMS */
1565 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1566 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1567 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1568 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1569 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1570 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1571 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1572 /* LCDDAT8 conflicts with TCK */
1573 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1574 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1575 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1576 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1577 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1578 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1579 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1580 /* LCDDAT16 conflicts with NTRST */
1581 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1582 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1583 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1584 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1585 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1586 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1587 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1589 pinctrl_lcd_rgb888: lcd-rgb-4 {
1591 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1592 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1593 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1594 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1595 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1596 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1597 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1598 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1599 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1600 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1601 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1602 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1603 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1604 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1605 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1606 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1607 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1608 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1609 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1610 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1611 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1612 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1613 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1614 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1619 pinctrl_macb0_rmii: macb0_rmii-0 {
1621 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1622 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1623 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1624 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1625 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1626 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1627 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1628 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1629 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1630 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1636 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1638 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1639 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1640 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1643 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1645 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1646 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1647 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1653 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1655 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1656 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1657 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1660 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1662 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1663 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1664 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1670 pinctrl_nand: nand-0 {
1672 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1673 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1675 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1676 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1678 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1679 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1680 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1681 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1682 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1683 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1684 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1685 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1686 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1687 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1692 pinctrl_spi0: spi0-0 {
1694 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1695 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1696 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1702 pinctrl_ssc0_tx: ssc0_tx {
1704 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1705 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1706 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1709 pinctrl_ssc0_rx: ssc0_rx {
1711 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1712 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1713 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1718 pinctrl_ssc1_tx: ssc1_tx {
1720 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1721 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1722 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1725 pinctrl_ssc1_rx: ssc1_rx {
1727 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1728 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1729 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1734 pinctrl_spi1: spi1-0 {
1736 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1737 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1738 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1744 pinctrl_spi2: spi2-0 {
1746 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1747 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1748 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1754 pinctrl_uart0: uart0-0 {
1756 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1757 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1763 pinctrl_uart1: uart1-0 {
1765 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */
1766 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */
1772 pinctrl_usart0: usart0-0 {
1774 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1775 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1778 pinctrl_usart0_rts: usart0_rts-0 {
1779 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1781 pinctrl_usart0_cts: usart0_cts-0 {
1782 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1787 pinctrl_usart1: usart1-0 {
1789 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1790 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1793 pinctrl_usart1_rts: usart1_rts-0 {
1794 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1796 pinctrl_usart1_cts: usart1_cts-0 {
1797 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1802 pinctrl_usart2: usart2-0 {
1804 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1805 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1808 pinctrl_usart2_rts: usart2_rts-0 {
1809 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1811 pinctrl_usart2_cts: usart2_cts-0 {
1812 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1817 pinctrl_usart3: usart3-0 {
1819 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1820 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1826 pinctrl_usart4: usart4-0 {
1828 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1829 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1832 pinctrl_usart4_rts: usart4_rts-0 {
1833 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1835 pinctrl_usart4_cts: usart4_cts-0 {
1836 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1841 aic: interrupt-controller@fc06e000 {
1842 #interrupt-cells = <3>;
1843 compatible = "atmel,sama5d4-aic";
1844 interrupt-controller;
1845 reg = <0xfc06e000 0x200>;
1846 atmel,external-irqs = <56>;