2 * Copyright (C) 2012 Altera <www.altera.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /include/ "skeleton.dtsi"
39 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
45 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 compatible = "arm,cortex-a9-gic";
54 #interrupt-cells = <3>;
56 reg = <0xfffed000 0x1000>,
63 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
69 compatible = "arm,amba-bus";
75 compatible = "arm,pl330", "arm,primecell";
76 reg = <0xffe01000 0x1000>;
77 interrupts = <0 180 4>;
84 gmac0: stmmac@ff700000 {
85 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
86 reg = <0xff700000 0x2000>;
87 interrupts = <0 115 4>;
88 interrupt-names = "macirq";
89 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
93 L2: l2-cache@fffef000 {
94 compatible = "arm,pl310-cache";
95 reg = <0xfffef000 0x1000>;
96 interrupts = <0 38 0x04>;
103 compatible = "arm,cortex-a9-twd-timer";
104 reg = <0xfffec600 0x100>;
105 interrupts = <1 13 0xf04>;
108 timer0: timer0@ffc08000 {
109 compatible = "snps,dw-apb-timer-sp";
110 interrupts = <0 167 4>;
111 reg = <0xffc08000 0x1000>;
114 timer1: timer1@ffc09000 {
115 compatible = "snps,dw-apb-timer-sp";
116 interrupts = <0 168 4>;
117 reg = <0xffc09000 0x1000>;
120 timer2: timer2@ffd00000 {
121 compatible = "snps,dw-apb-timer-osc";
122 interrupts = <0 169 4>;
123 reg = <0xffd00000 0x1000>;
126 timer3: timer3@ffd01000 {
127 compatible = "snps,dw-apb-timer-osc";
128 interrupts = <0 170 4>;
129 reg = <0xffd01000 0x1000>;
132 uart0: serial0@ffc02000 {
133 compatible = "snps,dw-apb-uart";
134 reg = <0xffc02000 0x1000>;
135 interrupts = <0 162 4>;
140 uart1: serial1@ffc03000 {
141 compatible = "snps,dw-apb-uart";
142 reg = <0xffc03000 0x1000>;
143 interrupts = <0 163 4>;
149 compatible = "altr,rst-mgr";
150 reg = <0xffd05000 0x1000>;
154 compatible = "altr,sys-mgr";
155 reg = <0xffd08000 0x4000>;