2 * Copyright (C) 2012 Altera <www.altera.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /include/ "skeleton.dtsi"
40 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
46 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
57 reg = <0xfffed000 0x1000>,
64 compatible = "simple-bus";
66 interrupt-parent = <&intc>;
70 compatible = "arm,amba-bus";
76 compatible = "arm,pl330", "arm,primecell";
77 reg = <0xffe01000 0x1000>;
78 interrupts = <0 180 4>;
82 clocks = <&l4_main_clk>;
83 clock-names = "apb_pclk";
88 compatible = "altr,clk-mgr";
89 reg = <0xffd04000 0x1000>;
97 compatible = "fixed-clock";
100 f2s_periph_ref_clk: f2s_periph_ref_clk {
102 compatible = "fixed-clock";
103 clock-frequency = <10000000>;
107 #address-cells = <1>;
110 compatible = "altr,socfpga-pll-clock";
116 compatible = "altr,socfpga-perip-clk";
117 clocks = <&main_pll>;
124 compatible = "altr,socfpga-perip-clk";
125 clocks = <&main_pll>;
130 dbg_base_clk: dbg_base_clk {
132 compatible = "altr,socfpga-perip-clk";
133 clocks = <&main_pll>;
138 main_qspi_clk: main_qspi_clk {
140 compatible = "altr,socfpga-perip-clk";
141 clocks = <&main_pll>;
145 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
147 compatible = "altr,socfpga-perip-clk";
148 clocks = <&main_pll>;
152 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
154 compatible = "altr,socfpga-perip-clk";
155 clocks = <&main_pll>;
160 periph_pll: periph_pll {
161 #address-cells = <1>;
164 compatible = "altr,socfpga-pll-clock";
168 emac0_clk: emac0_clk {
170 compatible = "altr,socfpga-perip-clk";
171 clocks = <&periph_pll>;
175 emac1_clk: emac1_clk {
177 compatible = "altr,socfpga-perip-clk";
178 clocks = <&periph_pll>;
182 per_qspi_clk: per_qsi_clk {
184 compatible = "altr,socfpga-perip-clk";
185 clocks = <&periph_pll>;
189 per_nand_mmc_clk: per_nand_mmc_clk {
191 compatible = "altr,socfpga-perip-clk";
192 clocks = <&periph_pll>;
196 per_base_clk: per_base_clk {
198 compatible = "altr,socfpga-perip-clk";
199 clocks = <&periph_pll>;
203 h2f_usr1_clk: h2f_usr1_clk {
205 compatible = "altr,socfpga-perip-clk";
206 clocks = <&periph_pll>;
211 sdram_pll: sdram_pll {
212 #address-cells = <1>;
215 compatible = "altr,socfpga-pll-clock";
219 ddr_dqs_clk: ddr_dqs_clk {
221 compatible = "altr,socfpga-perip-clk";
222 clocks = <&sdram_pll>;
226 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
228 compatible = "altr,socfpga-perip-clk";
229 clocks = <&sdram_pll>;
233 ddr_dq_clk: ddr_dq_clk {
235 compatible = "altr,socfpga-perip-clk";
236 clocks = <&sdram_pll>;
240 h2f_usr2_clk: h2f_usr2_clk {
242 compatible = "altr,socfpga-perip-clk";
243 clocks = <&sdram_pll>;
248 mpu_periph_clk: mpu_periph_clk {
250 compatible = "altr,socfpga-perip-clk";
255 mpu_l2_ram_clk: mpu_l2_ram_clk {
257 compatible = "altr,socfpga-perip-clk";
262 l4_main_clk: l4_main_clk {
264 compatible = "altr,socfpga-gate-clk";
269 l3_main_clk: l3_main_clk {
271 compatible = "altr,socfpga-perip-clk";
276 l3_mp_clk: l3_mp_clk {
278 compatible = "altr,socfpga-gate-clk";
280 div-reg = <0x64 0 2>;
284 l3_sp_clk: l3_sp_clk {
286 compatible = "altr,socfpga-gate-clk";
288 div-reg = <0x64 2 2>;
291 l4_mp_clk: l4_mp_clk {
293 compatible = "altr,socfpga-gate-clk";
294 clocks = <&mainclk>, <&per_base_clk>;
295 div-reg = <0x64 4 3>;
299 l4_sp_clk: l4_sp_clk {
301 compatible = "altr,socfpga-gate-clk";
302 clocks = <&mainclk>, <&per_base_clk>;
303 div-reg = <0x64 7 3>;
307 dbg_at_clk: dbg_at_clk {
309 compatible = "altr,socfpga-gate-clk";
310 clocks = <&dbg_base_clk>;
311 div-reg = <0x68 0 2>;
317 compatible = "altr,socfpga-gate-clk";
318 clocks = <&dbg_base_clk>;
319 div-reg = <0x68 2 2>;
323 dbg_trace_clk: dbg_trace_clk {
325 compatible = "altr,socfpga-gate-clk";
326 clocks = <&dbg_base_clk>;
327 div-reg = <0x6C 0 3>;
331 dbg_timer_clk: dbg_timer_clk {
333 compatible = "altr,socfpga-gate-clk";
334 clocks = <&dbg_base_clk>;
340 compatible = "altr,socfpga-gate-clk";
341 clocks = <&cfg_h2f_usr0_clk>;
345 h2f_user0_clk: h2f_user0_clk {
347 compatible = "altr,socfpga-gate-clk";
348 clocks = <&cfg_h2f_usr0_clk>;
352 emac_0_clk: emac_0_clk {
354 compatible = "altr,socfpga-gate-clk";
355 clocks = <&emac0_clk>;
359 emac_1_clk: emac_1_clk {
361 compatible = "altr,socfpga-gate-clk";
362 clocks = <&emac1_clk>;
366 usb_mp_clk: usb_mp_clk {
368 compatible = "altr,socfpga-gate-clk";
369 clocks = <&per_base_clk>;
371 div-reg = <0xa4 0 3>;
374 spi_m_clk: spi_m_clk {
376 compatible = "altr,socfpga-gate-clk";
377 clocks = <&per_base_clk>;
379 div-reg = <0xa4 3 3>;
384 compatible = "altr,socfpga-gate-clk";
385 clocks = <&per_base_clk>;
387 div-reg = <0xa4 6 3>;
392 compatible = "altr,socfpga-gate-clk";
393 clocks = <&per_base_clk>;
395 div-reg = <0xa4 9 3>;
398 gpio_db_clk: gpio_db_clk {
400 compatible = "altr,socfpga-gate-clk";
401 clocks = <&per_base_clk>;
403 div-reg = <0xa8 0 24>;
406 h2f_user1_clk: h2f_user1_clk {
408 compatible = "altr,socfpga-gate-clk";
409 clocks = <&h2f_usr1_clk>;
413 sdmmc_clk: sdmmc_clk {
415 compatible = "altr,socfpga-gate-clk";
416 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
420 nand_x_clk: nand_x_clk {
422 compatible = "altr,socfpga-gate-clk";
423 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
429 compatible = "altr,socfpga-gate-clk";
430 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
431 clk-gate = <0xa0 10>;
437 compatible = "altr,socfpga-gate-clk";
438 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
439 clk-gate = <0xa0 11>;
444 gmac0: ethernet@ff700000 {
445 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
446 reg = <0xff700000 0x2000>;
447 interrupts = <0 115 4>;
448 interrupt-names = "macirq";
449 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
450 clocks = <&emac0_clk>;
451 clock-names = "stmmaceth";
455 gmac1: ethernet@ff702000 {
456 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
457 reg = <0xff702000 0x2000>;
458 interrupts = <0 120 4>;
459 interrupt-names = "macirq";
460 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
461 clocks = <&emac1_clk>;
462 clock-names = "stmmaceth";
466 L2: l2-cache@fffef000 {
467 compatible = "arm,pl310-cache";
468 reg = <0xfffef000 0x1000>;
469 interrupts = <0 38 0x04>;
472 arm,tag-latency = <1 1 1>;
473 arm,data-latency = <2 1 1>;
478 compatible = "arm,cortex-a9-twd-timer";
479 reg = <0xfffec600 0x100>;
480 interrupts = <1 13 0xf04>;
481 clocks = <&mpu_periph_clk>;
484 timer0: timer0@ffc08000 {
485 compatible = "snps,dw-apb-timer";
486 interrupts = <0 167 4>;
487 reg = <0xffc08000 0x1000>;
490 timer1: timer1@ffc09000 {
491 compatible = "snps,dw-apb-timer";
492 interrupts = <0 168 4>;
493 reg = <0xffc09000 0x1000>;
496 timer2: timer2@ffd00000 {
497 compatible = "snps,dw-apb-timer";
498 interrupts = <0 169 4>;
499 reg = <0xffd00000 0x1000>;
502 timer3: timer3@ffd01000 {
503 compatible = "snps,dw-apb-timer";
504 interrupts = <0 170 4>;
505 reg = <0xffd01000 0x1000>;
508 uart0: serial0@ffc02000 {
509 compatible = "snps,dw-apb-uart";
510 reg = <0xffc02000 0x1000>;
511 interrupts = <0 162 4>;
516 uart1: serial1@ffc03000 {
517 compatible = "snps,dw-apb-uart";
518 reg = <0xffc03000 0x1000>;
519 interrupts = <0 163 4>;
525 compatible = "altr,rst-mgr";
526 reg = <0xffd05000 0x1000>;
530 compatible = "altr,sys-mgr";
531 reg = <0xffd08000 0x4000>;