2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include "skeleton.dtsi"
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
28 enable-method = "altr,socfpga-a10-smp";
31 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
48 reg = <0xffffd000 0x1000>,
55 compatible = "simple-bus";
57 interrupt-parent = <&intc>;
61 compatible = "simple-bus";
67 compatible = "arm,pl330", "arm,primecell";
68 reg = <0xffda1000 0x1000>;
69 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
70 <0 84 IRQ_TYPE_LEVEL_HIGH>,
71 <0 85 IRQ_TYPE_LEVEL_HIGH>,
72 <0 86 IRQ_TYPE_LEVEL_HIGH>,
73 <0 87 IRQ_TYPE_LEVEL_HIGH>,
74 <0 88 IRQ_TYPE_LEVEL_HIGH>,
75 <0 89 IRQ_TYPE_LEVEL_HIGH>,
76 <0 90 IRQ_TYPE_LEVEL_HIGH>,
77 <0 91 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&l4_main_clk>;
82 clock-names = "apb_pclk";
87 #address-cells = <0x1>;
90 compatible = "fpga-region";
91 fpga-mgr = <&fpga_mgr>;
95 compatible = "altr,clk-mgr";
96 reg = <0xffd04000 0x1000>;
102 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
104 compatible = "fixed-clock";
107 cb_intosc_ls_clk: cb_intosc_ls_clk {
109 compatible = "fixed-clock";
112 f2s_free_clk: f2s_free_clk {
114 compatible = "fixed-clock";
119 compatible = "fixed-clock";
123 #address-cells = <1>;
126 compatible = "altr,socfpga-a10-pll-clock";
127 clocks = <&osc1>, <&cb_intosc_ls_clk>,
131 main_mpu_base_clk: main_mpu_base_clk {
133 compatible = "altr,socfpga-a10-perip-clk";
134 clocks = <&main_pll>;
135 div-reg = <0x140 0 11>;
138 main_noc_base_clk: main_noc_base_clk {
140 compatible = "altr,socfpga-a10-perip-clk";
141 clocks = <&main_pll>;
142 div-reg = <0x144 0 11>;
145 main_emaca_clk: main_emaca_clk {
147 compatible = "altr,socfpga-a10-perip-clk";
148 clocks = <&main_pll>;
152 main_emacb_clk: main_emacb_clk {
154 compatible = "altr,socfpga-a10-perip-clk";
155 clocks = <&main_pll>;
159 main_emac_ptp_clk: main_emac_ptp_clk {
161 compatible = "altr,socfpga-a10-perip-clk";
162 clocks = <&main_pll>;
166 main_gpio_db_clk: main_gpio_db_clk {
168 compatible = "altr,socfpga-a10-perip-clk";
169 clocks = <&main_pll>;
173 main_sdmmc_clk: main_sdmmc_clk {
175 compatible = "altr,socfpga-a10-perip-clk"
177 clocks = <&main_pll>;
181 main_s2f_usr0_clk: main_s2f_usr0_clk {
183 compatible = "altr,socfpga-a10-perip-clk";
184 clocks = <&main_pll>;
188 main_s2f_usr1_clk: main_s2f_usr1_clk {
190 compatible = "altr,socfpga-a10-perip-clk";
191 clocks = <&main_pll>;
195 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
197 compatible = "altr,socfpga-a10-perip-clk";
198 clocks = <&main_pll>;
202 main_periph_ref_clk: main_periph_ref_clk {
204 compatible = "altr,socfpga-a10-perip-clk";
205 clocks = <&main_pll>;
210 periph_pll: periph_pll {
211 #address-cells = <1>;
214 compatible = "altr,socfpga-a10-pll-clock";
215 clocks = <&osc1>, <&cb_intosc_ls_clk>,
216 <&f2s_free_clk>, <&main_periph_ref_clk>;
219 peri_mpu_base_clk: peri_mpu_base_clk {
221 compatible = "altr,socfpga-a10-perip-clk";
222 clocks = <&periph_pll>;
223 div-reg = <0x140 16 11>;
226 peri_noc_base_clk: peri_noc_base_clk {
228 compatible = "altr,socfpga-a10-perip-clk";
229 clocks = <&periph_pll>;
230 div-reg = <0x144 16 11>;
233 peri_emaca_clk: peri_emaca_clk {
235 compatible = "altr,socfpga-a10-perip-clk";
236 clocks = <&periph_pll>;
240 peri_emacb_clk: peri_emacb_clk {
242 compatible = "altr,socfpga-a10-perip-clk";
243 clocks = <&periph_pll>;
247 peri_emac_ptp_clk: peri_emac_ptp_clk {
249 compatible = "altr,socfpga-a10-perip-clk";
250 clocks = <&periph_pll>;
254 peri_gpio_db_clk: peri_gpio_db_clk {
256 compatible = "altr,socfpga-a10-perip-clk";
257 clocks = <&periph_pll>;
261 peri_sdmmc_clk: peri_sdmmc_clk {
263 compatible = "altr,socfpga-a10-perip-clk";
264 clocks = <&periph_pll>;
268 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
270 compatible = "altr,socfpga-a10-perip-clk";
271 clocks = <&periph_pll>;
275 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
277 compatible = "altr,socfpga-a10-perip-clk";
278 clocks = <&periph_pll>;
282 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
284 compatible = "altr,socfpga-a10-perip-clk";
285 clocks = <&periph_pll>;
290 mpu_free_clk: mpu_free_clk {
292 compatible = "altr,socfpga-a10-perip-clk";
293 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
294 <&osc1>, <&cb_intosc_hs_div2_clk>,
299 noc_free_clk: noc_free_clk {
301 compatible = "altr,socfpga-a10-perip-clk";
302 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
303 <&osc1>, <&cb_intosc_hs_div2_clk>,
308 s2f_user1_free_clk: s2f_user1_free_clk {
310 compatible = "altr,socfpga-a10-perip-clk";
311 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
312 <&osc1>, <&cb_intosc_hs_div2_clk>,
317 sdmmc_free_clk: sdmmc_free_clk {
319 compatible = "altr,socfpga-a10-perip-clk";
320 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
321 <&osc1>, <&cb_intosc_hs_div2_clk>,
327 l4_sys_free_clk: l4_sys_free_clk {
329 compatible = "altr,socfpga-a10-perip-clk";
330 clocks = <&noc_free_clk>;
334 l4_main_clk: l4_main_clk {
336 compatible = "altr,socfpga-a10-gate-clk";
337 clocks = <&noc_free_clk>;
338 div-reg = <0xA8 0 2>;
342 l4_mp_clk: l4_mp_clk {
344 compatible = "altr,socfpga-a10-gate-clk";
345 clocks = <&noc_free_clk>;
346 div-reg = <0xA8 8 2>;
350 l4_sp_clk: l4_sp_clk {
352 compatible = "altr,socfpga-a10-gate-clk";
353 clocks = <&noc_free_clk>;
354 div-reg = <0xA8 16 2>;
358 mpu_periph_clk: mpu_periph_clk {
360 compatible = "altr,socfpga-a10-gate-clk";
361 clocks = <&mpu_free_clk>;
366 sdmmc_clk: sdmmc_clk {
368 compatible = "altr,socfpga-a10-gate-clk";
369 clocks = <&sdmmc_free_clk>;
376 compatible = "altr,socfpga-a10-gate-clk";
377 clocks = <&l4_main_clk>;
378 clk-gate = <0xC8 11>;
383 compatible = "altr,socfpga-a10-gate-clk";
384 clocks = <&l4_mp_clk>;
385 clk-gate = <0xC8 10>;
388 spi_m_clk: spi_m_clk {
390 compatible = "altr,socfpga-a10-gate-clk";
391 clocks = <&l4_main_clk>;
397 compatible = "altr,socfpga-a10-gate-clk";
398 clocks = <&l4_mp_clk>;
402 s2f_usr1_clk: s2f_usr1_clk {
404 compatible = "altr,socfpga-a10-gate-clk";
405 clocks = <&peri_s2f_usr1_clk>;
411 socfpga_axi_setup: stmmac-axi-config {
412 snps,wr_osr_lmt = <0xf>;
413 snps,rd_osr_lmt = <0xf>;
414 snps,blen = <0 0 0 0 16 0 0>;
417 gmac0: ethernet@ff800000 {
418 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
419 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
420 reg = <0xff800000 0x2000>;
421 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-names = "macirq";
423 /* Filled in by bootloader */
424 mac-address = [00 00 00 00 00 00];
425 snps,multicast-filter-bins = <256>;
426 snps,perfect-filter-entries = <128>;
427 tx-fifo-depth = <4096>;
428 rx-fifo-depth = <16384>;
429 clocks = <&l4_mp_clk>;
430 clock-names = "stmmaceth";
431 resets = <&rst EMAC0_RESET>;
432 reset-names = "stmmaceth";
433 snps,axi-config = <&socfpga_axi_setup>;
437 gmac1: ethernet@ff802000 {
438 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
439 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
440 reg = <0xff802000 0x2000>;
441 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-names = "macirq";
443 /* Filled in by bootloader */
444 mac-address = [00 00 00 00 00 00];
445 snps,multicast-filter-bins = <256>;
446 snps,perfect-filter-entries = <128>;
447 tx-fifo-depth = <4096>;
448 rx-fifo-depth = <16384>;
449 clocks = <&l4_mp_clk>;
450 clock-names = "stmmaceth";
451 resets = <&rst EMAC1_RESET>;
452 reset-names = "stmmaceth";
453 snps,axi-config = <&socfpga_axi_setup>;
457 gmac2: ethernet@ff804000 {
458 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
459 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
460 reg = <0xff804000 0x2000>;
461 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "macirq";
463 /* Filled in by bootloader */
464 mac-address = [00 00 00 00 00 00];
465 snps,multicast-filter-bins = <256>;
466 snps,perfect-filter-entries = <128>;
467 tx-fifo-depth = <4096>;
468 rx-fifo-depth = <16384>;
469 clocks = <&l4_mp_clk>;
470 clock-names = "stmmaceth";
471 snps,axi-config = <&socfpga_axi_setup>;
475 gpio0: gpio@ffc02900 {
476 #address-cells = <1>;
478 compatible = "snps,dw-apb-gpio";
479 reg = <0xffc02900 0x100>;
482 porta: gpio-controller@0 {
483 compatible = "snps,dw-apb-gpio-port";
486 snps,nr-gpios = <29>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
494 gpio1: gpio@ffc02a00 {
495 #address-cells = <1>;
497 compatible = "snps,dw-apb-gpio";
498 reg = <0xffc02a00 0x100>;
501 portb: gpio-controller@0 {
502 compatible = "snps,dw-apb-gpio-port";
505 snps,nr-gpios = <29>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
509 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
513 gpio2: gpio@ffc02b00 {
514 #address-cells = <1>;
516 compatible = "snps,dw-apb-gpio";
517 reg = <0xffc02b00 0x100>;
520 portc: gpio-controller@0 {
521 compatible = "snps,dw-apb-gpio-port";
524 snps,nr-gpios = <27>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
532 fpga_mgr: fpga-mgr@ffd03000 {
533 compatible = "altr,socfpga-a10-fpga-mgr";
534 reg = <0xffd03000 0x100
536 clocks = <&l4_mp_clk>;
537 resets = <&rst FPGAMGR_RESET>;
538 reset-names = "fpgamgr";
542 #address-cells = <1>;
544 compatible = "snps,designware-i2c";
545 reg = <0xffc02200 0x100>;
546 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&l4_sp_clk>;
552 #address-cells = <1>;
554 compatible = "snps,designware-i2c";
555 reg = <0xffc02300 0x100>;
556 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&l4_sp_clk>;
562 #address-cells = <1>;
564 compatible = "snps,designware-i2c";
565 reg = <0xffc02400 0x100>;
566 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&l4_sp_clk>;
572 #address-cells = <1>;
574 compatible = "snps,designware-i2c";
575 reg = <0xffc02500 0x100>;
576 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&l4_sp_clk>;
582 #address-cells = <1>;
584 compatible = "snps,designware-i2c";
585 reg = <0xffc02600 0x100>;
586 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&l4_sp_clk>;
592 compatible = "snps,dw-apb-ssi";
593 #address-cells = <1>;
595 reg = <0xffda5000 0x100>;
596 interrupts = <0 102 4>;
597 num-chipselect = <4>;
600 tx-dma-channel = <&pdma 16>;
601 rx-dma-channel = <&pdma 17>;
602 clocks = <&spi_m_clk>;
607 compatible = "altr,sdr-ctl", "syscon";
608 reg = <0xffcfb100 0x80>;
611 L2: l2-cache@fffff000 {
612 compatible = "arm,pl310-cache";
613 reg = <0xfffff000 0x1000>;
614 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
618 prefetch-instr = <1>;
622 mmc: dwmmc0@ff808000 {
623 #address-cells = <1>;
625 compatible = "altr,socfpga-dw-mshc";
626 reg = <0xff808000 0x1000>;
627 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
628 fifo-depth = <0x400>;
629 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
630 clock-names = "biu", "ciu";
634 nand: nand@ffb90000 {
635 #address-cells = <1>;
637 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
638 reg = <0xffb90000 0x72000>,
639 <0xffb80000 0x10000>;
640 reg-names = "nand_data", "denali_reg";
641 interrupts = <0 99 4>;
642 dma-mask = <0xffffffff>;
643 clocks = <&nand_clk>;
647 ocram: sram@ffe00000 {
648 compatible = "mmio-sram";
649 reg = <0xffe00000 0x40000>;
652 eccmgr: eccmgr@ffd06000 {
653 compatible = "altr,socfpga-a10-ecc-manager";
654 altr,sysmgr-syscon = <&sysmgr>;
655 #address-cells = <1>;
657 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
658 <0 0 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-controller;
660 #interrupt-cells = <2>;
664 compatible = "altr,sdram-edac-a10";
665 altr,sdr-syscon = <&sdr>;
666 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
667 <49 IRQ_TYPE_LEVEL_HIGH>;
671 compatible = "altr,socfpga-a10-l2-ecc";
672 reg = <0xffd06010 0x4>;
673 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
674 <32 IRQ_TYPE_LEVEL_HIGH>;
678 compatible = "altr,socfpga-a10-ocram-ecc";
679 reg = <0xff8c3000 0x400>;
680 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
681 <33 IRQ_TYPE_LEVEL_HIGH>;
684 emac0-rx-ecc@ff8c0800 {
685 compatible = "altr,socfpga-eth-mac-ecc";
686 reg = <0xff8c0800 0x400>;
687 altr,ecc-parent = <&gmac0>;
688 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
689 <36 IRQ_TYPE_LEVEL_HIGH>;
692 emac0-tx-ecc@ff8c0c00 {
693 compatible = "altr,socfpga-eth-mac-ecc";
694 reg = <0xff8c0c00 0x400>;
695 altr,ecc-parent = <&gmac0>;
696 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
697 <37 IRQ_TYPE_LEVEL_HIGH>;
701 compatible = "altr,socfpga-dma-ecc";
702 reg = <0xff8c8000 0x400>;
703 altr,ecc-parent = <&pdma>;
704 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
705 <42 IRQ_TYPE_LEVEL_HIGH>;
709 compatible = "altr,socfpga-usb-ecc";
710 reg = <0xff8c8800 0x400>;
711 altr,ecc-parent = <&usb0>;
712 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
713 <34 IRQ_TYPE_LEVEL_HIGH>;
718 compatible = "cdns,qspi-nor";
719 #address-cells = <1>;
721 reg = <0xff809000 0x100>,
722 <0xffa00000 0x100000>;
723 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
724 cdns,fifo-depth = <128>;
725 cdns,fifo-width = <4>;
726 cdns,trigger-address = <0x00000000>;
727 clocks = <&qspi_clk>;
731 rst: rstmgr@ffd05000 {
733 compatible = "altr,rst-mgr";
734 reg = <0xffd05000 0x100>;
735 altr,modrst-offset = <0x20>;
738 scu: snoop-control-unit@ffffc000 {
739 compatible = "arm,cortex-a9-scu";
740 reg = <0xffffc000 0x100>;
743 sysmgr: sysmgr@ffd06000 {
744 compatible = "altr,sys-mgr", "syscon";
745 reg = <0xffd06000 0x300>;
746 cpu1-start-addr = <0xffd06230>;
751 compatible = "arm,cortex-a9-twd-timer";
752 reg = <0xffffc600 0x100>;
753 interrupts = <1 13 0xf04>;
754 clocks = <&mpu_periph_clk>;
757 timer0: timer0@ffc02700 {
758 compatible = "snps,dw-apb-timer";
759 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
760 reg = <0xffc02700 0x100>;
761 clocks = <&l4_sp_clk>;
762 clock-names = "timer";
765 timer1: timer1@ffc02800 {
766 compatible = "snps,dw-apb-timer";
767 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
768 reg = <0xffc02800 0x100>;
769 clocks = <&l4_sp_clk>;
770 clock-names = "timer";
773 timer2: timer2@ffd00000 {
774 compatible = "snps,dw-apb-timer";
775 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
776 reg = <0xffd00000 0x100>;
777 clocks = <&l4_sys_free_clk>;
778 clock-names = "timer";
781 timer3: timer3@ffd00100 {
782 compatible = "snps,dw-apb-timer";
783 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
784 reg = <0xffd01000 0x100>;
785 clocks = <&l4_sys_free_clk>;
786 clock-names = "timer";
789 uart0: serial0@ffc02000 {
790 compatible = "snps,dw-apb-uart";
791 reg = <0xffc02000 0x100>;
792 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&l4_sp_clk>;
799 uart1: serial1@ffc02100 {
800 compatible = "snps,dw-apb-uart";
801 reg = <0xffc02100 0x100>;
802 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&l4_sp_clk>;
811 compatible = "usb-nop-xceiv";
816 compatible = "snps,dwc2";
817 reg = <0xffb00000 0xffff>;
818 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
821 resets = <&rst USB0_RESET>;
822 reset-names = "dwc2";
824 phy-names = "usb2-phy";
829 compatible = "snps,dwc2";
830 reg = <0xffb40000 0xffff>;
831 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
834 resets = <&rst USB1_RESET>;
835 reset-names = "dwc2";
837 phy-names = "usb2-phy";
841 watchdog0: watchdog@ffd00200 {
842 compatible = "snps,dw-wdt";
843 reg = <0xffd00200 0x100>;
844 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&l4_sys_free_clk>;
849 watchdog1: watchdog@ffd00300 {
850 compatible = "snps,dw-wdt";
851 reg = <0xffd00300 0x100>;
852 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&l4_sys_free_clk>;