2 * DTS file for all SPEAr13xx SoCs
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
30 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
36 gic: interrupt-controller@ec801000 {
37 compatible = "arm,cortex-a9-gic";
39 #interrupt-cells = <3>;
40 reg = < 0xec801000 0x1000 >,
41 < 0xec800100 0x0100 >;
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 6 0x04
51 compatible = "arm,pl310-cache";
52 reg = <0xed000000 0x1000>;
59 device_type = "memory";
64 bootargs = "console=ttyAMA0,115200";
68 compatible = "st,cpufreq-spear";
69 cpufreq_tbl = < 166000
82 compatible = "simple-bus";
83 ranges = <0x50000000 0x50000000 0x10000000
84 0xb0000000 0xb0000000 0x10000000
85 0xd0000000 0xd0000000 0x02000000
86 0xd8000000 0xd8000000 0x01000000
87 0xe0000000 0xe0000000 0x10000000>;
90 compatible = "st,sdhci-spear";
91 reg = <0xb3000000 0x100>;
92 interrupts = <0 28 0x4>;
97 compatible = "arasan,cf-spear1340";
98 reg = <0xb2800000 0x1000>;
99 interrupts = <0 29 0x4>;
101 dmas = <&dwdma0 0 0 0 0>;
105 dwdma0: dma@ea800000 {
106 compatible = "snps,dma-spear1340";
107 reg = <0xea800000 0x1000>;
108 interrupts = <0 19 0x4>;
114 chan_allocation_order = <1>;
116 block_size = <0xfff>;
118 data_width = <3 3 0 0>;
122 compatible = "snps,dma-spear1340";
123 reg = <0xeb000000 0x1000>;
124 interrupts = <0 59 0x4>;
131 chan_allocation_order = <1>;
133 block_size = <0xfff>;
134 data_width = <3 3 0 0>;
137 fsmc: flash@b0000000 {
138 compatible = "st,spear600-fsmc-nand";
139 #address-cells = <1>;
141 reg = <0xb0000000 0x1000 /* FSMC Register*/
142 0xb0800000 0x0010 /* NAND Base DATA */
143 0xb0820000 0x0010 /* NAND Base ADDR */
144 0xb0810000 0x0010>; /* NAND Base CMD */
145 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
146 interrupts = <0 20 0x4
154 gmac0: eth@e2000000 {
155 compatible = "st,spear600-gmac";
156 reg = <0xe2000000 0x8000>;
157 interrupts = <0 33 0x4
159 interrupt-names = "macirq", "eth_wake_irq";
164 compatible = "st,pcm-audio";
165 #address-cells = <0>;
170 smi: flash@ea000000 {
171 compatible = "st,spear600-smi";
172 #address-cells = <1>;
174 reg = <0xea000000 0x1000>;
175 interrupts = <0 30 0x4>;
180 compatible = "st,spear600-ehci", "usb-ehci";
181 reg = <0xe4800000 0x1000>;
182 interrupts = <0 64 0x4>;
188 compatible = "st,spear600-ehci", "usb-ehci";
189 reg = <0xe5800000 0x1000>;
190 interrupts = <0 66 0x4>;
196 compatible = "st,spear600-ohci", "usb-ohci";
197 reg = <0xe4000000 0x1000>;
198 interrupts = <0 65 0x4>;
204 compatible = "st,spear600-ohci", "usb-ohci";
205 reg = <0xe5000000 0x1000>;
206 interrupts = <0 67 0x4>;
212 #address-cells = <1>;
214 compatible = "simple-bus";
215 ranges = <0x50000000 0x50000000 0x10000000
216 0xb0000000 0xb0000000 0x10000000
217 0xd0000000 0xd0000000 0x02000000
218 0xd8000000 0xd8000000 0x01000000
219 0xe0000000 0xe0000000 0x10000000>;
221 gpio0: gpio@e0600000 {
222 compatible = "arm,pl061", "arm,primecell";
223 reg = <0xe0600000 0x1000>;
224 interrupts = <0 24 0x4>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
232 gpio1: gpio@e0680000 {
233 compatible = "arm,pl061", "arm,primecell";
234 reg = <0xe0680000 0x1000>;
235 interrupts = <0 25 0x4>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
244 compatible = "st,spear300-kbd";
245 reg = <0xe0300000 0x1000>;
246 interrupts = <0 52 0x4>;
251 #address-cells = <1>;
253 compatible = "snps,designware-i2c";
254 reg = <0xe0280000 0x1000>;
255 interrupts = <0 41 0x4>;
260 compatible = "st,designware-i2s";
261 reg = <0xe0180000 0x1000>;
262 interrupt-names = "play_irq", "record_irq";
263 interrupts = <0 10 0x4
269 compatible = "st,designware-i2s";
270 reg = <0xe0200000 0x1000>;
271 interrupt-names = "play_irq", "record_irq";
272 interrupts = <0 26 0x4
278 compatible = "arm,pl022", "arm,primecell";
279 reg = <0xe0100000 0x1000>;
280 #address-cells = <1>;
282 interrupts = <0 31 0x4>;
284 dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */
285 <&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */
286 dma-names = "tx", "rx";
290 compatible = "st,spear600-rtc";
291 reg = <0xe0580000 0x1000>;
292 interrupts = <0 36 0x4>;
297 compatible = "arm,pl011", "arm,primecell";
298 reg = <0xe0000000 0x1000>;
299 interrupts = <0 35 0x4>;
304 compatible = "st,spear600-adc";
305 reg = <0xe0080000 0x1000>;
306 interrupts = <0 12 0x4>;
311 compatible = "st,spear-timer";
312 reg = <0xe0380000 0x400>;
313 interrupts = <0 37 0x4>;
317 compatible = "arm,cortex-a9-twd-timer";
318 reg = <0xec800600 0x20>;
319 interrupts = <1 13 0x4>;
324 compatible = "arm,cortex-a9-twd-wdt";
325 reg = <0xec800620 0x20>;
330 compatible = "st,thermal-spear1340";
331 reg = <0xe07008c4 0x4>;
332 thermal_flags = <0x7000>;