2 * Copyright 2012 Linaro Ltd
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/mfd/dbx500-prcmu.h>
15 #include <dt-bindings/arm/ux500_pm_domains.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/ste-ab8500.h>
18 #include "skeleton.dtsi"
24 enable-method = "ste,dbx500-smp";
38 compatible = "arm,cortex-a9";
43 compatible = "arm,cortex-a9";
51 compatible = "stericsson,db8500";
52 interrupt-parent = <&intc>;
56 compatible = "arm,coresight-etm3x", "arm,primecell";
57 reg = <0x801ae000 0x1000>;
59 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
60 clock-names = "apb_pclk", "atclk";
63 ptm0_out_port: endpoint {
64 remote-endpoint = <&funnel_in_port0>;
70 compatible = "arm,coresight-etm3x", "arm,primecell";
71 reg = <0x801af000 0x1000>;
73 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
74 clock-names = "apb_pclk", "atclk";
77 ptm1_out_port: endpoint {
78 remote-endpoint = <&funnel_in_port1>;
84 compatible = "arm,coresight-funnel", "arm,primecell";
85 reg = <0x801a6000 0x1000>;
87 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
88 clock-names = "apb_pclk", "atclk";
93 /* funnel output ports */
96 funnel_out_port: endpoint {
98 <&replicator_in_port0>;
102 /* funnel input ports */
105 funnel_in_port0: endpoint {
107 remote-endpoint = <&ptm0_out_port>;
113 funnel_in_port1: endpoint {
115 remote-endpoint = <&ptm1_out_port>;
122 compatible = "arm,coresight-replicator";
123 clocks = <&prcmu_clk PRCMU_APEATCLK>;
124 clock-names = "atclk";
127 #address-cells = <1>;
130 /* replicator output ports */
133 replicator_out_port0: endpoint {
134 remote-endpoint = <&tpiu_in_port>;
139 replicator_out_port1: endpoint {
140 remote-endpoint = <&etb_in_port>;
144 /* replicator input port */
147 replicator_in_port0: endpoint {
149 remote-endpoint = <&funnel_out_port>;
156 compatible = "arm,coresight-tpiu", "arm,primecell";
157 reg = <0x80190000 0x1000>;
159 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
160 clock-names = "apb_pclk", "atclk";
162 tpiu_in_port: endpoint {
164 remote-endpoint = <&replicator_out_port0>;
170 compatible = "arm,coresight-etb10", "arm,primecell";
171 reg = <0x801a4000 0x1000>;
173 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
174 clock-names = "apb_pclk", "atclk";
176 etb_in_port: endpoint {
178 remote-endpoint = <&replicator_out_port1>;
183 intc: interrupt-controller@a0411000 {
184 compatible = "arm,cortex-a9-gic";
185 #interrupt-cells = <3>;
186 #address-cells = <1>;
187 interrupt-controller;
188 reg = <0xa0411000 0x1000>,
193 compatible = "arm,cortex-a9-scu";
194 reg = <0xa0410000 0x100>;
198 * The backup RAM is used for retention during sleep
199 * and various things like spin tables
202 compatible = "ste,dbx500-backupram";
203 reg = <0x80150000 0x2000>;
207 compatible = "arm,pl310-cache";
208 reg = <0xa0412000 0x1000>;
209 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
215 compatible = "arm,cortex-a9-pmu";
216 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
219 pm_domains: pm_domains0 {
220 compatible = "stericsson,ux500-pm-domains";
221 #power-domain-cells = <1>;
225 compatible = "stericsson,u8500-clks";
227 * Registers for the CLKRST block on peripheral
228 * groups 1, 2, 3, 5, 6,
230 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
231 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
234 prcmu_clk: prcmu-clock {
238 prcc_pclk: prcc-periph-clock {
242 prcc_kclk: prcc-kernel-clock {
246 rtc_clk: rtc32k-clock {
250 smp_twd_clk: smp-twd-clock {
256 /* Nomadik System Timer */
257 compatible = "st,nomadik-mtu";
258 reg = <0xa03c6000 0x1000>;
259 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
262 clock-names = "timclk", "apb_pclk";
266 compatible = "arm,cortex-a9-twd-timer";
267 reg = <0xa0410600 0x20>;
268 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
270 clocks = <&smp_twd_clk>;
274 compatible = "arm,cortex-a9-twd-wdt";
275 reg = <0xa0410620 0x20>;
276 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
277 clocks = <&smp_twd_clk>;
281 compatible = "arm,rtc-pl031", "arm,primecell";
282 reg = <0x80154000 0x1000>;
283 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
286 clock-names = "apb_pclk";
289 gpio0: gpio@8012e000 {
290 compatible = "stericsson,db8500-gpio",
292 reg = <0x8012e000 0x80>;
293 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 st,supports-sleepmode;
300 gpio-ranges = <&pinctrl 0 0 32>;
301 clocks = <&prcc_pclk 1 9>;
304 gpio1: gpio@8012e080 {
305 compatible = "stericsson,db8500-gpio",
307 reg = <0x8012e080 0x80>;
308 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 st,supports-sleepmode;
315 gpio-ranges = <&pinctrl 0 32 5>;
316 clocks = <&prcc_pclk 1 9>;
319 gpio2: gpio@8000e000 {
320 compatible = "stericsson,db8500-gpio",
322 reg = <0x8000e000 0x80>;
323 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 st,supports-sleepmode;
330 gpio-ranges = <&pinctrl 0 64 32>;
331 clocks = <&prcc_pclk 3 8>;
334 gpio3: gpio@8000e080 {
335 compatible = "stericsson,db8500-gpio",
337 reg = <0x8000e080 0x80>;
338 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 st,supports-sleepmode;
345 gpio-ranges = <&pinctrl 0 96 2>;
346 clocks = <&prcc_pclk 3 8>;
349 gpio4: gpio@8000e100 {
350 compatible = "stericsson,db8500-gpio",
352 reg = <0x8000e100 0x80>;
353 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 st,supports-sleepmode;
360 gpio-ranges = <&pinctrl 0 128 32>;
361 clocks = <&prcc_pclk 3 8>;
364 gpio5: gpio@8000e180 {
365 compatible = "stericsson,db8500-gpio",
367 reg = <0x8000e180 0x80>;
368 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
371 st,supports-sleepmode;
375 gpio-ranges = <&pinctrl 0 160 12>;
376 clocks = <&prcc_pclk 3 8>;
379 gpio6: gpio@8011e000 {
380 compatible = "stericsson,db8500-gpio",
382 reg = <0x8011e000 0x80>;
383 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 st,supports-sleepmode;
390 gpio-ranges = <&pinctrl 0 192 32>;
391 clocks = <&prcc_pclk 2 11>;
394 gpio7: gpio@8011e080 {
395 compatible = "stericsson,db8500-gpio",
397 reg = <0x8011e080 0x80>;
398 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-controller;
400 #interrupt-cells = <2>;
401 st,supports-sleepmode;
405 gpio-ranges = <&pinctrl 0 224 7>;
406 clocks = <&prcc_pclk 2 11>;
409 gpio8: gpio@a03fe000 {
410 compatible = "stericsson,db8500-gpio",
412 reg = <0xa03fe000 0x80>;
413 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
414 interrupt-controller;
415 #interrupt-cells = <2>;
416 st,supports-sleepmode;
420 gpio-ranges = <&pinctrl 0 256 12>;
421 clocks = <&prcc_pclk 5 1>;
425 compatible = "stericsson,db8500-pinctrl";
426 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
427 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
433 compatible = "stericsson,db8500-musb";
434 reg = <0xa03e0000 0x10000>;
435 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-names = "mc";
440 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
441 <&dma 38 0 0x0>, /* Logical - MemToDev */
442 <&dma 37 0 0x2>, /* Logical - DevToMem */
443 <&dma 37 0 0x0>, /* Logical - MemToDev */
444 <&dma 36 0 0x2>, /* Logical - DevToMem */
445 <&dma 36 0 0x0>, /* Logical - MemToDev */
446 <&dma 19 0 0x2>, /* Logical - DevToMem */
447 <&dma 19 0 0x0>, /* Logical - MemToDev */
448 <&dma 18 0 0x2>, /* Logical - DevToMem */
449 <&dma 18 0 0x0>, /* Logical - MemToDev */
450 <&dma 17 0 0x2>, /* Logical - DevToMem */
451 <&dma 17 0 0x0>, /* Logical - MemToDev */
452 <&dma 16 0 0x2>, /* Logical - DevToMem */
453 <&dma 16 0 0x0>, /* Logical - MemToDev */
454 <&dma 39 0 0x2>, /* Logical - DevToMem */
455 <&dma 39 0 0x0>; /* Logical - MemToDev */
457 dma-names = "iep_1_9", "oep_1_9",
458 "iep_2_10", "oep_2_10",
459 "iep_3_11", "oep_3_11",
460 "iep_4_12", "oep_4_12",
461 "iep_5_13", "oep_5_13",
462 "iep_6_14", "oep_6_14",
463 "iep_7_15", "oep_7_15",
466 clocks = <&prcc_pclk 5 0>;
469 dma: dma-controller@801C0000 {
470 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
471 reg = <0x801C0000 0x1000 0x40010000 0x800>;
472 reg-names = "base", "lcpa";
473 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
476 memcpy-channels = <56 57 58 59 60>;
478 clocks = <&prcmu_clk PRCMU_DMACLK>;
481 prcmu: prcmu@80157000 {
482 compatible = "stericsson,db8500-prcmu";
483 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
484 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
485 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
492 prcmu-timer-4@80157450 {
493 compatible = "stericsson,db8500-prcmu-timer-4";
494 reg = <0x80157450 0xC>;
498 compatible = "stericsson,cpufreq-ux500";
499 clocks = <&prcmu_clk PRCMU_ARMSS>;
500 clock-names = "armss";
505 compatible = "stericsson,db8500-thermal";
506 reg = <0x801573c0 0x40>;
507 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
508 <22 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
513 db8500-prcmu-regulators {
514 compatible = "stericsson,db8500-prcmu-regulator";
516 // DB8500_REGULATOR_VAPE
517 db8500_vape_reg: db8500_vape {
521 // DB8500_REGULATOR_VARM
522 db8500_varm_reg: db8500_varm {
525 // DB8500_REGULATOR_VMODEM
526 db8500_vmodem_reg: db8500_vmodem {
529 // DB8500_REGULATOR_VPLL
530 db8500_vpll_reg: db8500_vpll {
533 // DB8500_REGULATOR_VSMPS1
534 db8500_vsmps1_reg: db8500_vsmps1 {
537 // DB8500_REGULATOR_VSMPS2
538 db8500_vsmps2_reg: db8500_vsmps2 {
541 // DB8500_REGULATOR_VSMPS3
542 db8500_vsmps3_reg: db8500_vsmps3 {
545 // DB8500_REGULATOR_VRF1
546 db8500_vrf1_reg: db8500_vrf1 {
549 // DB8500_REGULATOR_SWITCH_SVAMMDSP
550 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
553 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
554 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
557 // DB8500_REGULATOR_SWITCH_SVAPIPE
558 db8500_sva_pipe_reg: db8500_sva_pipe {
561 // DB8500_REGULATOR_SWITCH_SIAMMDSP
562 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
565 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
566 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
569 // DB8500_REGULATOR_SWITCH_SIAPIPE
570 db8500_sia_pipe_reg: db8500_sia_pipe {
573 // DB8500_REGULATOR_SWITCH_SGA
574 db8500_sga_reg: db8500_sga {
575 vin-supply = <&db8500_vape_reg>;
578 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
579 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
580 vin-supply = <&db8500_vape_reg>;
583 // DB8500_REGULATOR_SWITCH_ESRAM12
584 db8500_esram12_reg: db8500_esram12 {
587 // DB8500_REGULATOR_SWITCH_ESRAM12RET
588 db8500_esram12_ret_reg: db8500_esram12_ret {
591 // DB8500_REGULATOR_SWITCH_ESRAM34
592 db8500_esram34_reg: db8500_esram34 {
595 // DB8500_REGULATOR_SWITCH_ESRAM34RET
596 db8500_esram34_ret_reg: db8500_esram34_ret {
601 compatible = "stericsson,ab8500";
602 interrupt-parent = <&intc>;
603 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
607 ab8500_clock: clock-controller {
608 compatible = "stericsson,ab8500-clk";
612 ab8500_gpio: ab8500-gpio {
613 compatible = "stericsson,ab8500-gpio";
619 compatible = "stericsson,ab8500-rtc";
620 interrupts = <17 IRQ_TYPE_LEVEL_HIGH
621 18 IRQ_TYPE_LEVEL_HIGH>;
622 interrupt-names = "60S", "ALARM";
626 compatible = "stericsson,ab8500-gpadc";
627 interrupts = <32 IRQ_TYPE_LEVEL_HIGH
628 39 IRQ_TYPE_LEVEL_HIGH>;
629 interrupt-names = "HW_CONV_END", "SW_CONV_END";
630 vddadc-supply = <&ab8500_ldo_tvout_reg>;
633 ab8500_battery: ab8500_battery {
634 stericsson,battery-type = "LIPO";
635 thermistor-on-batctrl;
639 compatible = "stericsson,ab8500-fg";
640 battery = <&ab8500_battery>;
644 compatible = "stericsson,ab8500-btemp";
645 battery = <&ab8500_battery>;
649 compatible = "stericsson,ab8500-charger";
650 battery = <&ab8500_battery>;
651 vddadc-supply = <&ab8500_ldo_tvout_reg>;
655 compatible = "stericsson,ab8500-chargalg";
656 battery = <&ab8500_battery>;
660 compatible = "stericsson,ab8500-usb";
661 interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
662 96 IRQ_TYPE_LEVEL_HIGH
663 14 IRQ_TYPE_LEVEL_HIGH
664 15 IRQ_TYPE_LEVEL_HIGH
665 79 IRQ_TYPE_LEVEL_HIGH
666 74 IRQ_TYPE_LEVEL_HIGH
667 75 IRQ_TYPE_LEVEL_HIGH>;
668 interrupt-names = "ID_WAKEUP_R",
673 "USB_ADP_PROBE_PLUG",
674 "USB_ADP_PROBE_UNPLUG";
675 vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
676 v-ape-supply = <&db8500_vape_reg>;
677 musb_1v8-supply = <&db8500_vsmps2_reg>;
678 clocks = <&prcmu_clk PRCMU_SYSCLK>;
679 clock-names = "sysclk";
683 compatible = "stericsson,ab8500-poweron-key";
684 interrupts = <6 IRQ_TYPE_LEVEL_HIGH
685 7 IRQ_TYPE_LEVEL_HIGH>;
686 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
690 compatible = "stericsson,ab8500-sysctrl";
694 compatible = "stericsson,ab8500-pwm";
695 clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
696 clock-names = "intclk";
700 compatible = "stericsson,ab8500-debug";
703 codec: ab8500-codec {
704 compatible = "stericsson,ab8500-codec";
706 V-AUD-supply = <&ab8500_ldo_audio_reg>;
707 V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
708 V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
709 V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
711 clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
712 clock-names = "audioclk";
714 stericsson,earpeice-cmv = <950>; /* Units in mV. */
717 ext_regulators: ab8500-ext-regulators {
718 compatible = "stericsson,ab8500-ext-regulator";
720 ab8500_ext1_reg: ab8500_ext1 {
721 regulator-min-microvolt = <1800000>;
722 regulator-max-microvolt = <1800000>;
727 ab8500_ext2_reg: ab8500_ext2 {
728 regulator-min-microvolt = <1360000>;
729 regulator-max-microvolt = <1360000>;
734 ab8500_ext3_reg: ab8500_ext3 {
735 regulator-min-microvolt = <3400000>;
736 regulator-max-microvolt = <3400000>;
742 compatible = "stericsson,ab8500-regulator";
743 vin-supply = <&ab8500_ext3_reg>;
745 // supplies to the display/camera
746 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
747 regulator-min-microvolt = <2500000>;
748 regulator-max-microvolt = <2900000>;
750 /* BUG: If turned off MMC will be affected. */
754 // supplies to the on-board eMMC
755 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
756 regulator-min-microvolt = <1100000>;
757 regulator-max-microvolt = <3300000>;
760 // supply for VAUX3; SDcard slots
761 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
762 regulator-min-microvolt = <1100000>;
763 regulator-max-microvolt = <3300000>;
766 // supply for v-intcore12; VINTCORE12 LDO
767 ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
770 // supply for tvout; gpadc; TVOUT LDO
771 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
774 // supply for ab8500-usb; USB LDO
775 ab8500_ldo_usb_reg: ab8500_ldo_usb {
778 // supply for ab8500-vaudio; VAUDIO LDO
779 ab8500_ldo_audio_reg: ab8500_ldo_audio {
782 // supply for v-anamic1 VAMIC1 LDO
783 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
786 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
787 ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
790 // supply for v-dmic; VDMIC LDO
791 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
794 // supply for U8500 CSI/DSI; VANA LDO
795 ab8500_ldo_ana_reg: ab8500_ldo_ana {
802 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
803 reg = <0x80004000 0x1000>;
804 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
806 #address-cells = <1>;
808 v-i2c-supply = <&db8500_vape_reg>;
810 clock-frequency = <400000>;
811 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
812 clock-names = "i2cclk", "apb_pclk";
813 power-domains = <&pm_domains DOMAIN_VAPE>;
817 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
818 reg = <0x80122000 0x1000>;
819 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
821 #address-cells = <1>;
823 v-i2c-supply = <&db8500_vape_reg>;
825 clock-frequency = <400000>;
827 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
828 clock-names = "i2cclk", "apb_pclk";
829 power-domains = <&pm_domains DOMAIN_VAPE>;
833 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
834 reg = <0x80128000 0x1000>;
835 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
837 #address-cells = <1>;
839 v-i2c-supply = <&db8500_vape_reg>;
841 clock-frequency = <400000>;
843 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
844 clock-names = "i2cclk", "apb_pclk";
845 power-domains = <&pm_domains DOMAIN_VAPE>;
849 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
850 reg = <0x80110000 0x1000>;
851 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
853 #address-cells = <1>;
855 v-i2c-supply = <&db8500_vape_reg>;
857 clock-frequency = <400000>;
859 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
860 clock-names = "i2cclk", "apb_pclk";
861 power-domains = <&pm_domains DOMAIN_VAPE>;
865 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
866 reg = <0x8012a000 0x1000>;
867 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
869 #address-cells = <1>;
871 v-i2c-supply = <&db8500_vape_reg>;
873 clock-frequency = <400000>;
875 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
876 clock-names = "i2cclk", "apb_pclk";
877 power-domains = <&pm_domains DOMAIN_VAPE>;
881 compatible = "arm,pl022", "arm,primecell";
882 reg = <0x80002000 0x1000>;
883 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
884 #address-cells = <1>;
886 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
887 clock-names = "SSPCLK", "apb_pclk";
888 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
889 <&dma 8 0 0x0>; /* Logical - MemToDev */
890 dma-names = "rx", "tx";
891 power-domains = <&pm_domains DOMAIN_VAPE>;
895 compatible = "arm,pl022", "arm,primecell";
896 reg = <0x80003000 0x1000>;
897 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
898 #address-cells = <1>;
900 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
901 clock-names = "SSPCLK", "apb_pclk";
902 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
903 <&dma 9 0 0x0>; /* Logical - MemToDev */
904 dma-names = "rx", "tx";
905 power-domains = <&pm_domains DOMAIN_VAPE>;
909 compatible = "arm,pl022", "arm,primecell";
910 reg = <0x8011a000 0x1000>;
911 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
912 #address-cells = <1>;
914 /* Same clock wired to kernel and pclk */
915 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
916 clock-names = "SSPCLK", "apb_pclk";
917 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
918 <&dma 0 0 0x0>; /* Logical - MemToDev */
919 dma-names = "rx", "tx";
920 power-domains = <&pm_domains DOMAIN_VAPE>;
924 compatible = "arm,pl022", "arm,primecell";
925 reg = <0x80112000 0x1000>;
926 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
927 #address-cells = <1>;
929 /* Same clock wired to kernel and pclk */
930 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
931 clock-names = "SSPCLK", "apb_pclk";
932 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
933 <&dma 35 0 0x0>; /* Logical - MemToDev */
934 dma-names = "rx", "tx";
935 power-domains = <&pm_domains DOMAIN_VAPE>;
939 compatible = "arm,pl022", "arm,primecell";
940 reg = <0x80111000 0x1000>;
941 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
942 #address-cells = <1>;
944 /* Same clock wired to kernel and pclk */
945 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
946 clock-names = "SSPCLK", "apb_pclk";
947 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
948 <&dma 33 0 0x0>; /* Logical - MemToDev */
949 dma-names = "rx", "tx";
950 power-domains = <&pm_domains DOMAIN_VAPE>;
954 compatible = "arm,pl022", "arm,primecell";
955 reg = <0x80129000 0x1000>;
956 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
957 #address-cells = <1>;
959 /* Same clock wired to kernel and pclk */
960 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
961 clock-names = "SSPCLK", "apb_pclk";
962 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
963 <&dma 40 0 0x0>; /* Logical - MemToDev */
964 dma-names = "rx", "tx";
965 power-domains = <&pm_domains DOMAIN_VAPE>;
968 ux500_serial0: uart@80120000 {
969 compatible = "arm,pl011", "arm,primecell";
970 reg = <0x80120000 0x1000>;
971 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
973 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
974 <&dma 13 0 0x0>; /* Logical - MemToDev */
975 dma-names = "rx", "tx";
977 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
978 clock-names = "uart", "apb_pclk";
983 ux500_serial1: uart@80121000 {
984 compatible = "arm,pl011", "arm,primecell";
985 reg = <0x80121000 0x1000>;
986 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
988 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
989 <&dma 12 0 0x0>; /* Logical - MemToDev */
990 dma-names = "rx", "tx";
992 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
993 clock-names = "uart", "apb_pclk";
998 ux500_serial2: uart@80007000 {
999 compatible = "arm,pl011", "arm,primecell";
1000 reg = <0x80007000 0x1000>;
1001 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1003 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1004 <&dma 11 0 0x0>; /* Logical - MemToDev */
1005 dma-names = "rx", "tx";
1007 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1008 clock-names = "uart", "apb_pclk";
1010 status = "disabled";
1013 sdi0_per1@80126000 {
1014 compatible = "arm,pl18x", "arm,primecell";
1015 reg = <0x80126000 0x1000>;
1016 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1018 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1019 <&dma 29 0 0x0>; /* Logical - MemToDev */
1020 dma-names = "rx", "tx";
1022 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1023 clock-names = "sdi", "apb_pclk";
1024 power-domains = <&pm_domains DOMAIN_VAPE>;
1026 status = "disabled";
1029 sdi1_per2@80118000 {
1030 compatible = "arm,pl18x", "arm,primecell";
1031 reg = <0x80118000 0x1000>;
1032 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1034 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1035 <&dma 32 0 0x0>; /* Logical - MemToDev */
1036 dma-names = "rx", "tx";
1038 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1039 clock-names = "sdi", "apb_pclk";
1040 power-domains = <&pm_domains DOMAIN_VAPE>;
1042 status = "disabled";
1045 sdi2_per3@80005000 {
1046 compatible = "arm,pl18x", "arm,primecell";
1047 reg = <0x80005000 0x1000>;
1048 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1051 <&dma 28 0 0x0>; /* Logical - MemToDev */
1052 dma-names = "rx", "tx";
1054 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1055 clock-names = "sdi", "apb_pclk";
1056 power-domains = <&pm_domains DOMAIN_VAPE>;
1058 status = "disabled";
1061 sdi3_per2@80119000 {
1062 compatible = "arm,pl18x", "arm,primecell";
1063 reg = <0x80119000 0x1000>;
1064 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1066 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1067 <&dma 41 0 0x0>; /* Logical - MemToDev */
1068 dma-names = "rx", "tx";
1070 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1071 clock-names = "sdi", "apb_pclk";
1072 power-domains = <&pm_domains DOMAIN_VAPE>;
1074 status = "disabled";
1077 sdi4_per2@80114000 {
1078 compatible = "arm,pl18x", "arm,primecell";
1079 reg = <0x80114000 0x1000>;
1080 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1082 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1083 <&dma 42 0 0x0>; /* Logical - MemToDev */
1084 dma-names = "rx", "tx";
1086 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1087 clock-names = "sdi", "apb_pclk";
1088 power-domains = <&pm_domains DOMAIN_VAPE>;
1090 status = "disabled";
1093 sdi5_per3@80008000 {
1094 compatible = "arm,pl18x", "arm,primecell";
1095 reg = <0x80008000 0x1000>;
1096 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1098 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1099 <&dma 43 0 0x0>; /* Logical - MemToDev */
1100 dma-names = "rx", "tx";
1102 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1103 clock-names = "sdi", "apb_pclk";
1104 power-domains = <&pm_domains DOMAIN_VAPE>;
1106 status = "disabled";
1110 compatible = "stericsson,snd-soc-mop500";
1111 stericsson,cpu-dai = <&msp1 &msp3>;
1112 stericsson,audio-codec = <&codec>;
1113 clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
1114 clock-names = "sysclk", "ulpclk", "intclk";
1117 msp0: msp@80123000 {
1118 compatible = "stericsson,ux500-msp-i2s";
1119 reg = <0x80123000 0x1000>;
1120 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1121 v-ape-supply = <&db8500_vape_reg>;
1123 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1124 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1125 dma-names = "rx", "tx";
1127 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1128 clock-names = "msp", "apb_pclk";
1130 status = "disabled";
1133 msp1: msp@80124000 {
1134 compatible = "stericsson,ux500-msp-i2s";
1135 reg = <0x80124000 0x1000>;
1136 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1137 v-ape-supply = <&db8500_vape_reg>;
1139 /* This DMA channel only exist on DB8500 v1 */
1140 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1143 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1144 clock-names = "msp", "apb_pclk";
1146 status = "disabled";
1150 msp2: msp@80117000 {
1151 compatible = "stericsson,ux500-msp-i2s";
1152 reg = <0x80117000 0x1000>;
1153 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1154 v-ape-supply = <&db8500_vape_reg>;
1156 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1157 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1159 dma-names = "rx", "tx";
1161 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1162 clock-names = "msp", "apb_pclk";
1164 status = "disabled";
1167 msp3: msp@80125000 {
1168 compatible = "stericsson,ux500-msp-i2s";
1169 reg = <0x80125000 0x1000>;
1170 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1171 v-ape-supply = <&db8500_vape_reg>;
1173 /* This DMA channel only exist on DB8500 v2 */
1174 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1177 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1178 clock-names = "msp", "apb_pclk";
1180 status = "disabled";
1183 external-bus@50000000 {
1184 compatible = "simple-bus";
1185 reg = <0x50000000 0x4000000>;
1186 #address-cells = <1>;
1188 ranges = <0 0x50000000 0x4000000>;
1189 status = "disabled";
1193 compatible = "stericsson,mcde";
1194 reg = <0xa0350000 0x1000>, /* MCDE */
1195 <0xa0351000 0x1000>, /* DSI link 1 */
1196 <0xa0352000 0x1000>, /* DSI link 2 */
1197 <0xa0353000 0x1000>; /* DSI link 3 */
1198 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1200 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1201 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1202 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1203 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1204 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1205 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1206 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1210 compatible = "stericsson,ux500-cryp";
1211 reg = <0xa03cb000 0x1000>;
1212 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1214 v-ape-supply = <&db8500_vape_reg>;
1215 clocks = <&prcc_pclk 6 1>;
1219 compatible = "stericsson,ux500-hash";
1220 reg = <0xa03c2000 0x1000>;
1222 v-ape-supply = <&db8500_vape_reg>;
1223 clocks = <&prcc_pclk 6 2>;