arch/arm/boot/dts/stih407-family.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-pinctrl.dtsi"
  10 #include <dt-bindings/mfd/st-lpc.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/reset/stih407-resets.h>
  13 #include <dt-bindings/interrupt-controller/irq-st.h>
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <0>;
  25
  26                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  27                         cpu-release-addr = <0x94100A4>;
  28
  29                                          /* kHz     uV   */
  30                         operating-points = <1500000 0
  31                                             1200000 0
  32                                             800000  0
  33                                             500000  0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <1>;
  39
  40                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  41                         cpu-release-addr = <0x94100A4>;
  42
  43                                          /* kHz     uV   */
  44                         operating-points = <1500000 0
  45                                             1200000 0
  46                                             800000  0
  47                                             500000  0>;
  48                 };
  49         };
  50
  51         intc: interrupt-controller@08761000 {
  52                 compatible = "arm,cortex-a9-gic";
  53                 #interrupt-cells = <3>;
  54                 interrupt-controller;
  55                 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
  56         };
  57
  58         scu@08760000 {
  59                 compatible = "arm,cortex-a9-scu";
  60                 reg = <0x08760000 0x1000>;
  61         };
  62
  63         timer@08760200 {
  64                 interrupt-parent = <&intc>;
  65                 compatible = "arm,cortex-a9-global-timer";
  66                 reg = <0x08760200 0x100>;
  67                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  68                 clocks = <&arm_periph_clk>;
  69         };
  70
  71         l2: cache-controller {
  72                 compatible = "arm,pl310-cache";
  73                 reg = <0x08762000 0x1000>;
  74                 arm,data-latency = <3 3 3>;
  75                 arm,tag-latency = <2 2 2>;
  76                 cache-unified;
  77                 cache-level = <2>;
  78         };
  79
  80         arm-pmu {
  81                 interrupt-parent = <&intc>;
  82                 compatible = "arm,cortex-a9-pmu";
  83                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
  84         };
  85
  86         pwm_regulator: pwm-regulator {
  87                 compatible = "pwm-regulator";
  88                 pwms = <&pwm1 3 8448>;
  89                 regulator-name = "CPU_1V0_AVS";
  90                 regulator-min-microvolt = <784000>;
  91                 regulator-max-microvolt = <1299000>;
  92                 regulator-always-on;
  93                 max-duty-cycle = <255>;
  94                 status = "okay";
  95         };
  96
  97         soc {
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 interrupt-parent = <&intc>;
 101                 ranges;
 102                 compatible = "simple-bus";
 103
 104                 restart {
 105                         compatible = "st,stih407-restart";
 106                         st,syscfg = <&syscfg_sbc_reg>;
 107                         status = "okay";
 108                 };
 109
 110                 powerdown: powerdown-controller {
 111                         compatible = "st,stih407-powerdown";
 112                         #reset-cells = <1>;
 113                 };
 114
 115                 softreset: softreset-controller {
 116                         compatible = "st,stih407-softreset";
 117                         #reset-cells = <1>;
 118                 };
 119
 120                 picophyreset: picophyreset-controller {
 121                         compatible = "st,stih407-picophyreset";
 122                         #reset-cells = <1>;
 123                 };
 124
 125                 syscfg_sbc: sbc-syscfg@9620000 {
 126                         compatible = "st,stih407-sbc-syscfg", "syscon";
 127                         reg = <0x9620000 0x1000>;
 128                 };
 129
 130                 syscfg_front: front-syscfg@9280000 {
 131                         compatible = "st,stih407-front-syscfg", "syscon";
 132                         reg = <0x9280000 0x1000>;
 133                 };
 134
 135                 syscfg_rear: rear-syscfg@9290000 {
 136                         compatible = "st,stih407-rear-syscfg", "syscon";
 137                         reg = <0x9290000 0x1000>;
 138                 };
 139
 140                 syscfg_flash: flash-syscfg@92a0000 {
 141                         compatible = "st,stih407-flash-syscfg", "syscon";
 142                         reg = <0x92a0000 0x1000>;
 143                 };
 144
 145                 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
 146                         compatible = "st,stih407-sbc-reg-syscfg", "syscon";
 147                         reg = <0x9600000 0x1000>;
 148                 };
 149
 150                 syscfg_core: core-syscfg@92b0000 {
 151                         compatible = "st,stih407-core-syscfg", "syscon";
 152                         reg = <0x92b0000 0x1000>;
 153                 };
 154
 155                 syscfg_lpm: lpm-syscfg@94b5100 {
 156                         compatible = "st,stih407-lpm-syscfg", "syscon";
 157                         reg = <0x94b5100 0x1000>;
 158                 };
 159
 160                 irq-syscfg {
 161                         compatible    = "st,stih407-irq-syscfg";
 162                         st,syscfg     = <&syscfg_core>;
 163                         st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
 164                                         <ST_IRQ_SYSCFG_PMU_1>;
 165                         st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
 166                                         <ST_IRQ_SYSCFG_DISABLED>;
 167                 };
 168
 169                 /* Display */
 170                 vtg_main: sti-vtg-main@8d02800 {
 171                         compatible = "st,vtg";
 172                         reg = <0x8d02800 0x200>;
 173                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
 174                 };
 175
 176                 vtg_aux: sti-vtg-aux@8d00200 {
 177                         compatible = "st,vtg";
 178                         reg = <0x8d00200 0x100>;
 179                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
 180                 };
 181
 182                 serial@9830000 {
 183                         compatible = "st,asc";
 184                         reg = <0x9830000 0x2c>;
 185                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
 186                         pinctrl-names = "default";
 187                         pinctrl-0 = <&pinctrl_serial0>;
 188                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 189
 190                         status = "disabled";
 191                 };
 192
 193                 serial@9831000 {
 194                         compatible = "st,asc";
 195                         reg = <0x9831000 0x2c>;
 196                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&pinctrl_serial1>;
 199                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 200
 201                         status = "disabled";
 202                 };
 203
 204                 serial@9832000 {
 205                         compatible = "st,asc";
 206                         reg = <0x9832000 0x2c>;
 207                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 208                         pinctrl-names = "default";
 209                         pinctrl-0 = <&pinctrl_serial2>;
 210                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 211
 212                         status = "disabled";
 213                 };
 214
 215                 /* SBC_ASC0 - UART10 */
 216                 sbc_serial0: serial@9530000 {
 217                         compatible = "st,asc";
 218                         reg = <0x9530000 0x2c>;
 219                         interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
 220                         pinctrl-names = "default";
 221                         pinctrl-0 = <&pinctrl_sbc_serial0>;
 222                         clocks = <&clk_sysin>;
 223
 224                         status = "disabled";
 225                 };
 226
 227                 serial@9531000 {
 228                         compatible = "st,asc";
 229                         reg = <0x9531000 0x2c>;
 230                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
 231                         pinctrl-names = "default";
 232                         pinctrl-0 = <&pinctrl_sbc_serial1>;
 233                         clocks = <&clk_sysin>;
 234
 235                         status = "disabled";
 236                 };
 237
 238                 i2c@9840000 {
 239                         compatible = "st,comms-ssc4-i2c";
 240                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 241                         reg = <0x9840000 0x110>;
 242                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 243                         clock-names = "ssc";
 244                         clock-frequency = <400000>;
 245                         pinctrl-names = "default";
 246                         pinctrl-0 = <&pinctrl_i2c0_default>;
 247
 248                         status = "disabled";
 249                 };
 250
 251                 i2c@9841000 {
 252                         compatible = "st,comms-ssc4-i2c";
 253                         reg = <0x9841000 0x110>;
 254                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 255                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 256                         clock-names = "ssc";
 257                         clock-frequency = <400000>;
 258                         pinctrl-names = "default";
 259                         pinctrl-0 = <&pinctrl_i2c1_default>;
 260
 261                         status = "disabled";
 262                 };
 263
 264                 i2c@9842000 {
 265                         compatible = "st,comms-ssc4-i2c";
 266                         reg = <0x9842000 0x110>;
 267                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 269                         clock-names = "ssc";
 270                         clock-frequency = <400000>;
 271                         pinctrl-names = "default";
 272                         pinctrl-0 = <&pinctrl_i2c2_default>;
 273
 274                         status = "disabled";
 275                 };
 276
 277                 i2c@9843000 {
 278                         compatible = "st,comms-ssc4-i2c";
 279                         reg = <0x9843000 0x110>;
 280                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 282                         clock-names = "ssc";
 283                         clock-frequency = <400000>;
 284                         pinctrl-names = "default";
 285                         pinctrl-0 = <&pinctrl_i2c3_default>;
 286
 287                         status = "disabled";
 288                 };
 289
 290                 i2c@9844000 {
 291                         compatible = "st,comms-ssc4-i2c";
 292                         reg = <0x9844000 0x110>;
 293                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 295                         clock-names = "ssc";
 296                         clock-frequency = <400000>;
 297                         pinctrl-names = "default";
 298                         pinctrl-0 = <&pinctrl_i2c4_default>;
 299
 300                         status = "disabled";
 301                 };
 302
 303                 i2c@9845000 {
 304                         compatible = "st,comms-ssc4-i2c";
 305                         reg = <0x9845000 0x110>;
 306                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 308                         clock-names = "ssc";
 309                         clock-frequency = <400000>;
 310                         pinctrl-names = "default";
 311                         pinctrl-0 = <&pinctrl_i2c5_default>;
 312
 313                         status = "disabled";
 314                 };
 315
 316
 317                 /* SSCs on SBC */
 318                 i2c@9540000 {
 319                         compatible = "st,comms-ssc4-i2c";
 320                         reg = <0x9540000 0x110>;
 321                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&clk_sysin>;
 323                         clock-names = "ssc";
 324                         clock-frequency = <400000>;
 325                         pinctrl-names = "default";
 326                         pinctrl-0 = <&pinctrl_i2c10_default>;
 327
 328                         status = "disabled";
 329                 };
 330
 331                 i2c@9541000 {
 332                         compatible = "st,comms-ssc4-i2c";
 333                         reg = <0x9541000 0x110>;
 334                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&clk_sysin>;
 336                         clock-names = "ssc";
 337                         clock-frequency = <400000>;
 338                         pinctrl-names = "default";
 339                         pinctrl-0 = <&pinctrl_i2c11_default>;
 340
 341                         status = "disabled";
 342                 };
 343
 344                 usb2_picophy0: phy1 {
 345                         compatible = "st,stih407-usb2-phy";
 346                         #phy-cells = <0>;
 347                         st,syscfg = <&syscfg_core 0x100 0xf4>;
 348                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 349                                  <&picophyreset STIH407_PICOPHY2_RESET>;
 350                         reset-names = "global", "port";
 351                 };
 352
 353                 miphy28lp_phy: miphy28lp@9b22000 {
 354                         compatible = "st,miphy28lp-phy";
 355                         st,syscfg = <&syscfg_core>;
 356                         #address-cells  = <1>;
 357                         #size-cells     = <1>;
 358                         ranges;
 359
 360                         phy_port0: port@9b22000 {
 361                                 reg = <0x9b22000 0xff>,
 362                                       <0x9b09000 0xff>,
 363                                       <0x9b04000 0xff>;
 364                                 reg-names = "sata-up",
 365                                             "pcie-up",
 366                                             "pipew";
 367
 368                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
 369                                 #phy-cells = <1>;
 370
 371                                 reset-names = "miphy-sw-rst";
 372                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
 373                         };
 374
 375                         phy_port1: port@9b2a000 {
 376                                 reg = <0x9b2a000 0xff>,
 377                                       <0x9b19000 0xff>,
 378                                       <0x9b14000 0xff>;
 379                                 reg-names = "sata-up",
 380                                             "pcie-up",
 381                                             "pipew";
 382
 383                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
 384
 385                                 #phy-cells = <1>;
 386
 387                                 reset-names = "miphy-sw-rst";
 388                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
 389                         };
 390
 391                         phy_port2: port@8f95000 {
 392                                 reg = <0x8f95000 0xff>,
 393                                       <0x8f90000 0xff>;
 394                                 reg-names = "pipew",
 395                                             "usb3-up";
 396
 397                                 st,syscfg = <0x11c 0x820>;
 398
 399                                 #phy-cells = <1>;
 400
 401                                 reset-names = "miphy-sw-rst";
 402                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 403                         };
 404                 };
 405
 406                 spi@9840000 {
 407                         compatible = "st,comms-ssc4-spi";
 408                         reg = <0x9840000 0x110>;
 409                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 411                         clock-names = "ssc";
 412                         pinctrl-0 = <&pinctrl_spi0_default>;
 413                         pinctrl-names = "default";
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416
 417                         status = "disabled";
 418                 };
 419
 420                 spi@9841000 {
 421                         compatible = "st,comms-ssc4-spi";
 422                         reg = <0x9841000 0x110>;
 423                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 425                         clock-names = "ssc";
 426                         pinctrl-names = "default";
 427                         pinctrl-0 = <&pinctrl_spi1_default>;
 428
 429                         status = "disabled";
 430                 };
 431
 432                 spi@9842000 {
 433                         compatible = "st,comms-ssc4-spi";
 434                         reg = <0x9842000 0x110>;
 435                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 437                         clock-names = "ssc";
 438                         pinctrl-names = "default";
 439                         pinctrl-0 = <&pinctrl_spi2_default>;
 440
 441                         status = "disabled";
 442                 };
 443
 444                 spi@9843000 {
 445                         compatible = "st,comms-ssc4-spi";
 446                         reg = <0x9843000 0x110>;
 447                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 448                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 449                         clock-names = "ssc";
 450                         pinctrl-names = "default";
 451                         pinctrl-0 = <&pinctrl_spi3_default>;
 452
 453                         status = "disabled";
 454                 };
 455
 456                 spi@9844000 {
 457                         compatible = "st,comms-ssc4-spi";
 458                         reg = <0x9844000 0x110>;
 459                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 461                         clock-names = "ssc";
 462                         pinctrl-names = "default";
 463                         pinctrl-0 = <&pinctrl_spi4_default>;
 464
 465                         status = "disabled";
 466                 };
 467
 468                 /* SBC SSC */
 469                 spi@9540000 {
 470                         compatible = "st,comms-ssc4-spi";
 471                         reg = <0x9540000 0x110>;
 472                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&clk_sysin>;
 474                         clock-names = "ssc";
 475                         pinctrl-names = "default";
 476                         pinctrl-0 = <&pinctrl_spi10_default>;
 477
 478                         status = "disabled";
 479                 };
 480
 481                 spi@9541000 {
 482                         compatible = "st,comms-ssc4-spi";
 483                         reg = <0x9541000 0x110>;
 484                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 485                         clocks = <&clk_sysin>;
 486                         clock-names = "ssc";
 487                         pinctrl-names = "default";
 488                         pinctrl-0 = <&pinctrl_spi11_default>;
 489
 490                         status = "disabled";
 491                 };
 492
 493                 spi@9542000 {
 494                         compatible = "st,comms-ssc4-spi";
 495                         reg = <0x9542000 0x110>;
 496                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&clk_sysin>;
 498                         clock-names = "ssc";
 499                         pinctrl-names = "default";
 500                         pinctrl-0 = <&pinctrl_spi12_default>;
 501
 502                         status = "disabled";
 503                 };
 504
 505                 mmc0: sdhci@09060000 {
 506                         compatible = "st,sdhci-stih407", "st,sdhci";
 507                         status = "disabled";
 508                         reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
 509                         reg-names = "mmc", "top-mmc-delay";
 510                         interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
 511                         interrupt-names = "mmcirq";
 512                         pinctrl-names = "default";
 513                         pinctrl-0 = <&pinctrl_mmc0>;
 514                         clock-names = "mmc";
 515                         clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
 516                         bus-width = <8>;
 517                         non-removable;
 518                 };
 519
 520                 mmc1: sdhci@09080000 {
 521                         compatible = "st,sdhci-stih407", "st,sdhci";
 522                         status = "disabled";
 523                         reg = <0x09080000 0x7ff>;
 524                         reg-names = "mmc";
 525                         interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
 526                         interrupt-names = "mmcirq";
 527                         pinctrl-names = "default";
 528                         pinctrl-0 = <&pinctrl_sd1>;
 529                         clock-names = "mmc";
 530                         clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
 531                         resets = <&softreset STIH407_MMC1_SOFTRESET>;
 532                         bus-width = <4>;
 533                 };
 534
 535                 /* Watchdog and Real-Time Clock */
 536                 lpc@8787000 {
 537                         compatible = "st,stih407-lpc";
 538                         reg = <0x8787000 0x1000>;
 539                         interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
 540                         clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
 541                         timeout-sec = <120>;
 542                         st,syscfg = <&syscfg_core>;
 543                         st,lpc-mode = <ST_LPC_MODE_WDT>;
 544                 };
 545
 546                 lpc@8788000 {
 547                         compatible = "st,stih407-lpc";
 548                         reg = <0x8788000 0x1000>;
 549                         interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
 550                         clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
 551                         st,lpc-mode = <ST_LPC_MODE_RTC>;
 552                 };
 553
 554                 sata0: sata@9b20000 {
 555                         compatible = "st,ahci";
 556                         reg = <0x9b20000 0x1000>;
 557
 558                         interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 559                         interrupt-names = "hostc";
 560
 561                         phys = <&phy_port0 PHY_TYPE_SATA>;
 562                         phy-names = "ahci_phy";
 563
 564                         resets = <&powerdown STIH407_SATA0_POWERDOWN>,
 565                                  <&softreset STIH407_SATA0_SOFTRESET>,
 566                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
 567                         reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
 568
 569                         clock-names = "ahci_clk";
 570                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 571
 572                         status = "disabled";
 573                 };
 574
 575                 sata1: sata@9b28000 {
 576                         compatible = "st,ahci";
 577                         reg = <0x9b28000 0x1000>;
 578
 579                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 580                         interrupt-names = "hostc";
 581
 582                         phys = <&phy_port1 PHY_TYPE_SATA>;
 583                         phy-names = "ahci_phy";
 584
 585                         resets = <&powerdown STIH407_SATA1_POWERDOWN>,
 586                                  <&softreset STIH407_SATA1_SOFTRESET>,
 587                                  <&softreset STIH407_SATA1_PWR_SOFTRESET>;
 588                         reset-names = "pwr-dwn",
 589                                       "sw-rst",
 590                                       "pwr-rst";
 591
 592                         clock-names = "ahci_clk";
 593                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 594
 595                         status = "disabled";
 596                 };
 597
 598
 599                 st_dwc3: dwc3@8f94000 {
 600                         compatible      = "st,stih407-dwc3";
 601                         reg             = <0x08f94000 0x1000>, <0x110 0x4>;
 602                         reg-names       = "reg-glue", "syscfg-reg";
 603                         st,syscfg       = <&syscfg_core>;
 604                         resets          = <&powerdown STIH407_USB3_POWERDOWN>,
 605                                           <&softreset STIH407_MIPHY2_SOFTRESET>;
 606                         reset-names     = "powerdown", "softreset";
 607                         #address-cells  = <1>;
 608                         #size-cells     = <1>;
 609                         pinctrl-names   = "default";
 610                         pinctrl-0       = <&pinctrl_usb3>;
 611                         ranges;
 612
 613                         status = "disabled";
 614
 615                         dwc3: dwc3@9900000 {
 616                                 compatible      = "snps,dwc3";
 617                                 reg             = <0x09900000 0x100000>;
 618                                 interrupts      = <GIC_SPI 155 IRQ_TYPE_NONE>;
 619                                 dr_mode         = "host";
 620                                 phy-names       = "usb2-phy", "usb3-phy";
 621                                 phys            = <&usb2_picophy0>,
 622                                                   <&phy_port2 PHY_TYPE_USB3>;
 623                         };
 624                 };
 625
 626                 /* COMMS PWM Module */
 627                 pwm0: pwm@9810000 {
 628                         compatible      = "st,sti-pwm";
 629                         #pwm-cells      = <2>;
 630                         reg             = <0x9810000 0x68>;
 631                         pinctrl-names   = "default";
 632                         pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
 633                         clock-names     = "pwm";
 634                         clocks          = <&clk_sysin>;
 635                         st,pwm-num-chan = <1>;
 636
 637                         status          = "disabled";
 638                 };
 639
 640                 /* SBC PWM Module */
 641                 pwm1: pwm@9510000 {
 642                         compatible      = "st,sti-pwm";
 643                         #pwm-cells      = <2>;
 644                         reg             = <0x9510000 0x68>;
 645                         pinctrl-names   = "default";
 646                         pinctrl-0       = <&pinctrl_pwm1_chan0_default
 647                                         &pinctrl_pwm1_chan1_default
 648                                         &pinctrl_pwm1_chan2_default
 649                                         &pinctrl_pwm1_chan3_default>;
 650                         clock-names     = "pwm";
 651                         clocks          = <&clk_sysin>;
 652                         st,pwm-num-chan = <4>;
 653
 654                         status          = "disabled";
 655                 };
 656
 657                 rng10: rng@08a89000 {
 658                         compatible      = "st,rng";
 659                         reg             = <0x08a89000 0x1000>;
 660                         clocks          = <&clk_sysin>;
 661                         status          = "okay";
 662                 };
 663
 664                 rng11: rng@08a8a000 {
 665                         compatible      = "st,rng";
 666                         reg             = <0x08a8a000 0x1000>;
 667                         clocks          = <&clk_sysin>;
 668                         status          = "okay";
 669                 };
 670
 671                 ethernet0: dwmac@9630000 {
 672                         device_type = "network";
 673                         status = "disabled";
 674                         compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 675                         reg = <0x9630000 0x8000>, <0x80 0x4>;
 676                         reg-names = "stmmaceth", "sti-ethconf";
 677
 678                         st,syscon = <&syscfg_sbc_reg 0x80>;
 679                         st,gmac_en;
 680                         resets = <&softreset STIH407_ETH1_SOFTRESET>;
 681                         reset-names = "stmmaceth";
 682
 683                         interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
 684                                      <GIC_SPI 99 IRQ_TYPE_NONE>;
 685                         interrupt-names = "macirq", "eth_wake_irq";
 686
 687                         /* DMA Bus Mode */
 688                         snps,pbl = <8>;
 689
 690                         pinctrl-names = "default";
 691                         pinctrl-0 = <&pinctrl_rgmii1>;
 692
 693                         clock-names = "stmmaceth", "sti-ethclk";
 694                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 695                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
 696                 };
 697
 698                 rng10: rng@08a89000 {
 699                         compatible      = "st,rng";
 700                         reg             = <0x08a89000 0x1000>;
 701                         clocks          = <&clk_sysin>;
 702                         status          = "okay";
 703                 };
 704
 705                 rng11: rng@08a8a000 {
 706                         compatible      = "st,rng";
 707                         reg             = <0x08a8a000 0x1000>;
 708                         clocks          = <&clk_sysin>;
 709                         status          = "okay";
 710                 };
 711         };
 712 };