2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
9 #include "stih407-pinctrl.dtsi"
10 #include <dt-bindings/mfd/st-lpc.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/stih407-resets.h>
13 #include <dt-bindings/interrupt-controller/irq-st.h>
23 gp0_reserved: rproc@45000000 {
24 compatible = "shared-dma-pool";
25 reg = <0x45000000 0x00400000>;
29 delta_reserved: rproc@44000000 {
30 compatible = "shared-dma-pool";
31 reg = <0x44000000 0x01000000>;
41 compatible = "arm,cortex-a9";
44 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
45 cpu-release-addr = <0x94100A4>;
48 operating-points = <1500000 0
55 clock-latency = <100000>;
56 cpu0-supply = <&pwm_regulator>;
57 st,syscfg = <&syscfg_core 0x8e0>;
61 compatible = "arm,cortex-a9";
64 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
65 cpu-release-addr = <0x94100A4>;
68 operating-points = <1500000 0
75 intc: interrupt-controller@08761000 {
76 compatible = "arm,cortex-a9-gic";
77 #interrupt-cells = <3>;
79 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
83 compatible = "arm,cortex-a9-scu";
84 reg = <0x08760000 0x1000>;
88 interrupt-parent = <&intc>;
89 compatible = "arm,cortex-a9-global-timer";
90 reg = <0x08760200 0x100>;
91 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&arm_periph_clk>;
95 l2: cache-controller {
96 compatible = "arm,pl310-cache";
97 reg = <0x08762000 0x1000>;
98 arm,data-latency = <3 3 3>;
99 arm,tag-latency = <2 2 2>;
105 interrupt-parent = <&intc>;
106 compatible = "arm,cortex-a9-pmu";
107 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
110 pwm_regulator: pwm-regulator {
111 compatible = "pwm-regulator";
112 pwms = <&pwm1 3 8448>;
113 regulator-name = "CPU_1V0_AVS";
114 regulator-min-microvolt = <784000>;
115 regulator-max-microvolt = <1299000>;
117 max-duty-cycle = <255>;
122 #address-cells = <1>;
124 interrupt-parent = <&intc>;
126 compatible = "simple-bus";
129 compatible = "st,stih407-restart";
130 st,syscfg = <&syscfg_sbc_reg>;
134 powerdown: powerdown-controller {
135 compatible = "st,stih407-powerdown";
139 softreset: softreset-controller {
140 compatible = "st,stih407-softreset";
144 picophyreset: picophyreset-controller {
145 compatible = "st,stih407-picophyreset";
149 syscfg_sbc: sbc-syscfg@9620000 {
150 compatible = "st,stih407-sbc-syscfg", "syscon";
151 reg = <0x9620000 0x1000>;
154 syscfg_front: front-syscfg@9280000 {
155 compatible = "st,stih407-front-syscfg", "syscon";
156 reg = <0x9280000 0x1000>;
159 syscfg_rear: rear-syscfg@9290000 {
160 compatible = "st,stih407-rear-syscfg", "syscon";
161 reg = <0x9290000 0x1000>;
164 syscfg_flash: flash-syscfg@92a0000 {
165 compatible = "st,stih407-flash-syscfg", "syscon";
166 reg = <0x92a0000 0x1000>;
169 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
170 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
171 reg = <0x9600000 0x1000>;
174 syscfg_core: core-syscfg@92b0000 {
175 compatible = "st,stih407-core-syscfg", "syscon";
176 reg = <0x92b0000 0x1000>;
179 syscfg_lpm: lpm-syscfg@94b5100 {
180 compatible = "st,stih407-lpm-syscfg", "syscon";
181 reg = <0x94b5100 0x1000>;
185 compatible = "st,stih407-irq-syscfg";
186 st,syscfg = <&syscfg_core>;
187 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
188 <ST_IRQ_SYSCFG_PMU_1>;
189 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
190 <ST_IRQ_SYSCFG_DISABLED>;
194 vtg_main: sti-vtg-main@8d02800 {
195 compatible = "st,vtg";
196 reg = <0x8d02800 0x200>;
197 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
200 vtg_aux: sti-vtg-aux@8d00200 {
201 compatible = "st,vtg";
202 reg = <0x8d00200 0x100>;
203 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
207 compatible = "st,asc";
208 reg = <0x9830000 0x2c>;
209 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
210 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
211 /* Pinctrl moved out to a per-board configuration */
217 compatible = "st,asc";
218 reg = <0x9831000 0x2c>;
219 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_serial1>;
222 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
228 compatible = "st,asc";
229 reg = <0x9832000 0x2c>;
230 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_serial2>;
233 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
238 /* SBC_ASC0 - UART10 */
239 sbc_serial0: serial@9530000 {
240 compatible = "st,asc";
241 reg = <0x9530000 0x2c>;
242 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_sbc_serial0>;
245 clocks = <&clk_sysin>;
251 compatible = "st,asc";
252 reg = <0x9531000 0x2c>;
253 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_sbc_serial1>;
256 clocks = <&clk_sysin>;
262 compatible = "st,comms-ssc4-i2c";
263 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
264 reg = <0x9840000 0x110>;
265 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
267 clock-frequency = <400000>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c0_default>;
270 #address-cells = <1>;
277 compatible = "st,comms-ssc4-i2c";
278 reg = <0x9841000 0x110>;
279 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
282 clock-frequency = <400000>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_i2c1_default>;
285 #address-cells = <1>;
292 compatible = "st,comms-ssc4-i2c";
293 reg = <0x9842000 0x110>;
294 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
297 clock-frequency = <400000>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_i2c2_default>;
300 #address-cells = <1>;
307 compatible = "st,comms-ssc4-i2c";
308 reg = <0x9843000 0x110>;
309 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
312 clock-frequency = <400000>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_i2c3_default>;
315 #address-cells = <1>;
322 compatible = "st,comms-ssc4-i2c";
323 reg = <0x9844000 0x110>;
324 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
327 clock-frequency = <400000>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_i2c4_default>;
330 #address-cells = <1>;
337 compatible = "st,comms-ssc4-i2c";
338 reg = <0x9845000 0x110>;
339 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
342 clock-frequency = <400000>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_i2c5_default>;
345 #address-cells = <1>;
354 compatible = "st,comms-ssc4-i2c";
355 reg = <0x9540000 0x110>;
356 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clk_sysin>;
359 clock-frequency = <400000>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_i2c10_default>;
362 #address-cells = <1>;
369 compatible = "st,comms-ssc4-i2c";
370 reg = <0x9541000 0x110>;
371 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&clk_sysin>;
374 clock-frequency = <400000>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_i2c11_default>;
377 #address-cells = <1>;
383 usb2_picophy0: phy1 {
384 compatible = "st,stih407-usb2-phy";
386 st,syscfg = <&syscfg_core 0x100 0xf4>;
387 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
388 <&picophyreset STIH407_PICOPHY2_RESET>;
389 reset-names = "global", "port";
392 miphy28lp_phy: miphy28lp@9b22000 {
393 compatible = "st,miphy28lp-phy";
394 st,syscfg = <&syscfg_core>;
395 #address-cells = <1>;
399 phy_port0: port@9b22000 {
400 reg = <0x9b22000 0xff>,
403 reg-names = "sata-up",
407 st,syscfg = <0x114 0x818 0xe0 0xec>;
410 reset-names = "miphy-sw-rst";
411 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
414 phy_port1: port@9b2a000 {
415 reg = <0x9b2a000 0xff>,
418 reg-names = "sata-up",
422 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
426 reset-names = "miphy-sw-rst";
427 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
430 phy_port2: port@8f95000 {
431 reg = <0x8f95000 0xff>,
436 st,syscfg = <0x11c 0x820>;
440 reset-names = "miphy-sw-rst";
441 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
446 compatible = "st,comms-ssc4-spi";
447 reg = <0x9840000 0x110>;
448 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
451 pinctrl-0 = <&pinctrl_spi0_default>;
452 pinctrl-names = "default";
453 #address-cells = <1>;
460 compatible = "st,comms-ssc4-spi";
461 reg = <0x9841000 0x110>;
462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_spi1_default>;
472 compatible = "st,comms-ssc4-spi";
473 reg = <0x9842000 0x110>;
474 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_spi2_default>;
484 compatible = "st,comms-ssc4-spi";
485 reg = <0x9843000 0x110>;
486 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_spi3_default>;
496 compatible = "st,comms-ssc4-spi";
497 reg = <0x9844000 0x110>;
498 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_spi4_default>;
509 compatible = "st,comms-ssc4-spi";
510 reg = <0x9540000 0x110>;
511 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clk_sysin>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_spi10_default>;
521 compatible = "st,comms-ssc4-spi";
522 reg = <0x9541000 0x110>;
523 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&clk_sysin>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_spi11_default>;
533 compatible = "st,comms-ssc4-spi";
534 reg = <0x9542000 0x110>;
535 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&clk_sysin>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_spi12_default>;
544 mmc0: sdhci@09060000 {
545 compatible = "st,sdhci-stih407", "st,sdhci";
547 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
548 reg-names = "mmc", "top-mmc-delay";
549 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
550 interrupt-names = "mmcirq";
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_mmc0>;
553 clock-names = "mmc", "icn";
554 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
555 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
559 mmc1: sdhci@09080000 {
560 compatible = "st,sdhci-stih407", "st,sdhci";
562 reg = <0x09080000 0x7ff>;
564 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
565 interrupt-names = "mmcirq";
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_sd1>;
568 clock-names = "mmc", "icn";
569 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
570 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
571 resets = <&softreset STIH407_MMC1_SOFTRESET>;
575 /* Watchdog and Real-Time Clock */
577 compatible = "st,stih407-lpc";
578 reg = <0x8787000 0x1000>;
579 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
580 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
582 st,syscfg = <&syscfg_core>;
583 st,lpc-mode = <ST_LPC_MODE_WDT>;
587 compatible = "st,stih407-lpc";
588 reg = <0x8788000 0x1000>;
589 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
590 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
591 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
594 sata0: sata@9b20000 {
595 compatible = "st,ahci";
596 reg = <0x9b20000 0x1000>;
598 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
599 interrupt-names = "hostc";
601 phys = <&phy_port0 PHY_TYPE_SATA>;
602 phy-names = "ahci_phy";
604 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
605 <&softreset STIH407_SATA0_SOFTRESET>,
606 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
607 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
609 clock-names = "ahci_clk";
610 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
612 ports-implemented = <0x1>;
617 sata1: sata@9b28000 {
618 compatible = "st,ahci";
619 reg = <0x9b28000 0x1000>;
621 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
622 interrupt-names = "hostc";
624 phys = <&phy_port1 PHY_TYPE_SATA>;
625 phy-names = "ahci_phy";
627 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
628 <&softreset STIH407_SATA1_SOFTRESET>,
629 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
630 reset-names = "pwr-dwn",
634 clock-names = "ahci_clk";
635 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
637 ports-implemented = <0x1>;
643 st_dwc3: dwc3@8f94000 {
644 compatible = "st,stih407-dwc3";
645 reg = <0x08f94000 0x1000>, <0x110 0x4>;
646 reg-names = "reg-glue", "syscfg-reg";
647 st,syscfg = <&syscfg_core>;
648 resets = <&powerdown STIH407_USB3_POWERDOWN>,
649 <&softreset STIH407_MIPHY2_SOFTRESET>;
650 reset-names = "powerdown", "softreset";
651 #address-cells = <1>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&pinctrl_usb3>;
660 compatible = "snps,dwc3";
661 reg = <0x09900000 0x100000>;
662 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
664 phy-names = "usb2-phy", "usb3-phy";
665 phys = <&usb2_picophy0>,
666 <&phy_port2 PHY_TYPE_USB3>;
667 snps,dis_u3_susphy_quirk;
671 /* COMMS PWM Module */
673 compatible = "st,sti-pwm";
675 reg = <0x9810000 0x68>;
676 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
680 clocks = <&clk_sysin>;
681 st,pwm-num-chan = <1>;
688 compatible = "st,sti-pwm";
690 reg = <0x9510000 0x68>;
691 interrupts = <GIC_SPI 131 IRQ_TYPE_NONE>;
692 pinctrl-names = "default";
693 pinctrl-0 = <&pinctrl_pwm1_chan0_default
694 &pinctrl_pwm1_chan1_default
695 &pinctrl_pwm1_chan2_default
696 &pinctrl_pwm1_chan3_default>;
698 clocks = <&clk_sysin>;
699 st,pwm-num-chan = <4>;
704 rng10: rng@08a89000 {
705 compatible = "st,rng";
706 reg = <0x08a89000 0x1000>;
707 clocks = <&clk_sysin>;
711 rng11: rng@08a8a000 {
712 compatible = "st,rng";
713 reg = <0x08a8a000 0x1000>;
714 clocks = <&clk_sysin>;
718 ethernet0: dwmac@9630000 {
719 device_type = "network";
721 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
722 reg = <0x9630000 0x8000>, <0x80 0x4>;
723 reg-names = "stmmaceth", "sti-ethconf";
725 st,syscon = <&syscfg_sbc_reg 0x80>;
727 resets = <&softreset STIH407_ETH1_SOFTRESET>;
728 reset-names = "stmmaceth";
730 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
731 <GIC_SPI 99 IRQ_TYPE_NONE>;
732 interrupt-names = "macirq", "eth_wake_irq";
737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_rgmii1>;
740 clock-names = "stmmaceth", "sti-ethclk";
741 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
742 <&clk_s_c0_flexgen CLK_ETH_PHY>;
745 cec: sti-cec@094a087c {
746 compatible = "st,stih-cec";
747 reg = <0x94a087c 0x64>;
748 clocks = <&clk_sysin>;
749 clock-names = "cec-clk";
750 interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
751 interrupt-names = "cec-irq";
752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_cec0_default>;
754 resets = <&softreset STIH407_LPM_SOFTRESET>;
757 rng10: rng@08a89000 {
758 compatible = "st,rng";
759 reg = <0x08a89000 0x1000>;
760 clocks = <&clk_sysin>;
764 rng11: rng@08a8a000 {
765 compatible = "st,rng";
766 reg = <0x08a8a000 0x1000>;
767 clocks = <&clk_sysin>;
771 mailbox0: mailbox@8f00000 {
772 compatible = "st,stih407-mailbox";
773 reg = <0x8f00000 0x1000>;
774 interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
780 mailbox1: mailbox@8f01000 {
781 compatible = "st,stih407-mailbox";
782 reg = <0x8f01000 0x1000>;
784 mbox-name = "st231_gp_1";
788 mailbox2: mailbox@8f02000 {
789 compatible = "st,stih407-mailbox";
790 reg = <0x8f02000 0x1000>;
792 mbox-name = "st231_gp_0";
796 mailbox3: mailbox@8f03000 {
797 compatible = "st,stih407-mailbox";
798 reg = <0x8f03000 0x1000>;
800 mbox-name = "st231_audio_video";
804 st231_gp0: remote-processor {
805 compatible = "st,st231-rproc";
806 memory-region = <&gp0_reserved>;
807 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
808 reset-names = "sw_reset";
809 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
810 clock-frequency = <600000000>;
811 st,syscfg = <&syscfg_core 0x22c>;
813 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
814 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
817 st231_delta: remote-processor {
818 compatible = "st,st231-rproc";
819 memory-region = <&delta_reserved>;
820 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
821 reset-names = "sw_reset";
822 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
823 clock-frequency = <600000000>;
824 st,syscfg = <&syscfg_core 0x224>;
826 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
827 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
831 fdma0: dma-controller@8e20000 {
832 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
833 reg = <0x8e20000 0x8000>,
837 reg-names = "slimcore", "dmem", "peripherals", "imem";
838 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
839 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
840 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
841 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
842 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
848 fdma1: dma-controller@8e40000 {
849 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
850 reg = <0x8e40000 0x8000>,
854 reg-names = "slimcore", "dmem", "peripherals", "imem";
855 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
856 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
857 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
858 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
860 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
867 /* fdma free running */
868 fdma2: dma-controller@8e60000 {
869 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
870 reg = <0x8e60000 0x8000>,
874 reg-names = "slimcore", "dmem", "peripherals", "imem";
875 interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
878 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
879 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
880 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
881 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
886 sti_sasg_codec: sti-sasg-codec {
887 compatible = "st,stih407-sas-codec";
888 #sound-dai-cells = <1>;
890 st,syscfg = <&syscfg_core>;
893 sti_uni_player0: sti-uni-player@8d80000 {
894 compatible = "st,stih407-uni-player-hdmi";
895 #sound-dai-cells = <0>;
896 st,syscfg = <&syscfg_core>;
897 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
898 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
899 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
900 assigned-clock-rates = <50000000>;
901 reg = <0x8d80000 0x158>;
902 interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
903 dmas = <&fdma0 2 0 1>;
909 sti_uni_player1: sti-uni-player@8d81000 {
910 compatible = "st,stih407-uni-player-pcm-out";
911 #sound-dai-cells = <0>;
912 st,syscfg = <&syscfg_core>;
913 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
914 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
915 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
916 assigned-clock-rates = <50000000>;
917 reg = <0x8d81000 0x158>;
918 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
919 dmas = <&fdma0 3 0 1>;
925 sti_uni_player2: sti-uni-player@8d82000 {
926 compatible = "st,stih407-uni-player-dac";
927 #sound-dai-cells = <0>;
928 st,syscfg = <&syscfg_core>;
929 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
930 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
931 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
932 assigned-clock-rates = <50000000>;
933 reg = <0x8d82000 0x158>;
934 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
935 dmas = <&fdma0 4 0 1>;
941 sti_uni_player3: sti-uni-player@8d85000 {
942 compatible = "st,stih407-uni-player-spdif";
943 #sound-dai-cells = <0>;
944 st,syscfg = <&syscfg_core>;
945 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
946 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
947 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
948 assigned-clock-rates = <50000000>;
949 reg = <0x8d85000 0x158>;
950 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
951 dmas = <&fdma0 7 0 1>;
957 sti_uni_reader0: sti-uni-reader@8d83000 {
958 compatible = "st,stih407-uni-reader-pcm_in";
959 #sound-dai-cells = <0>;
960 st,syscfg = <&syscfg_core>;
961 reg = <0x8d83000 0x158>;
962 interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
963 dmas = <&fdma0 5 0 1>;
969 sti_uni_reader1: sti-uni-reader@8d84000 {
970 compatible = "st,stih407-uni-reader-hdmi";
971 #sound-dai-cells = <0>;
972 st,syscfg = <&syscfg_core>;
973 reg = <0x8d84000 0x158>;
974 interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
975 dmas = <&fdma0 6 0 1>;
982 compatible = "st,st-delta";
983 clock-names = "delta",
985 "delta-flash-promip";
986 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
987 <&clk_s_c0_flexgen CLK_ST231_DMU>,
988 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;