arch/arm/boot/dts/stih407-pinctrl.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "st-pincfg.h"
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 / {
  12
  13         aliases {
  14                 /* 0-5: PIO_SBC */
  15                 gpio0 = &pio0;
  16                 gpio1 = &pio1;
  17                 gpio2 = &pio2;
  18                 gpio3 = &pio3;
  19                 gpio4 = &pio4;
  20                 gpio5 = &pio5;
  21                 /* 10-19: PIO_FRONT0 */
  22                 gpio6 = &pio10;
  23                 gpio7 = &pio11;
  24                 gpio8 = &pio12;
  25                 gpio9 = &pio13;
  26                 gpio10 = &pio14;
  27                 gpio11 = &pio15;
  28                 gpio12 = &pio16;
  29                 gpio13 = &pio17;
  30                 gpio14 = &pio18;
  31                 gpio15 = &pio19;
  32                 /* 20: PIO_FRONT1 */
  33                 gpio16 = &pio20;
  34                 /* 30-35: PIO_REAR */
  35                 gpio17 = &pio30;
  36                 gpio18 = &pio31;
  37                 gpio19 = &pio32;
  38                 gpio20 = &pio33;
  39                 gpio21 = &pio34;
  40                 gpio22 = &pio35;
  41                 /* 40-42: PIO_FLASH */
  42                 gpio23 = &pio40;
  43                 gpio24 = &pio41;
  44                 gpio25 = &pio42;
  45         };
  46
  47         soc {
  48                 pin-controller-sbc {
  49                         #address-cells = <1>;
  50                         #size-cells = <1>;
  51                         compatible = "st,stih407-sbc-pinctrl";
  52                         st,syscfg = <&syscfg_sbc>;
  53                         reg = <0x0961f080 0x4>;
  54                         reg-names = "irqmux";
  55                         interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
  56                         interrupts-names = "irqmux";
  57                         ranges = <0 0x09610000 0x6000>;
  58
  59                         pio0: gpio@09610000 {
  60                                 gpio-controller;
  61                                 #gpio-cells = <1>;
  62                                 interrupt-controller;
  63                                 #interrupt-cells = <2>;
  64                                 reg = <0x0 0x100>;
  65                                 st,bank-name = "PIO0";
  66                         };
  67                         pio1: gpio@09611000 {
  68                                 gpio-controller;
  69                                 #gpio-cells = <1>;
  70                                 interrupt-controller;
  71                                 #interrupt-cells = <2>;
  72                                 reg = <0x1000 0x100>;
  73                                 st,bank-name = "PIO1";
  74                         };
  75                         pio2: gpio@09612000 {
  76                                 gpio-controller;
  77                                 #gpio-cells = <1>;
  78                                 interrupt-controller;
  79                                 #interrupt-cells = <2>;
  80                                 reg = <0x2000 0x100>;
  81                                 st,bank-name = "PIO2";
  82                         };
  83                         pio3: gpio@09613000 {
  84                                 gpio-controller;
  85                                 #gpio-cells = <1>;
  86                                 interrupt-controller;
  87                                 #interrupt-cells = <2>;
  88                                 reg = <0x3000 0x100>;
  89                                 st,bank-name = "PIO3";
  90                         };
  91                         pio4: gpio@09614000 {
  92                                 gpio-controller;
  93                                 #gpio-cells = <1>;
  94                                 interrupt-controller;
  95                                 #interrupt-cells = <2>;
  96                                 reg = <0x4000 0x100>;
  97                                 st,bank-name = "PIO4";
  98                         };
  99
 100                         pio5: gpio@09615000 {
 101                                 gpio-controller;
 102                                 #gpio-cells = <1>;
 103                                 interrupt-controller;
 104                                 #interrupt-cells = <2>;
 105                                 reg = <0x5000 0x100>;
 106                                 st,bank-name = "PIO5";
 107                                 st,retime-pin-mask = <0x3f>;
 108                         };
 109
 110                         cec0 {
 111                                 pinctrl_cec0_default: cec0-default {
 112                                         st,pins {
 113                                                 hdmi_cec = <&pio2 4 ALT1 BIDIR>;
 114                                         };
 115                                 };
 116                         };
 117
 118                         rc {
 119                                 pinctrl_ir: ir0 {
 120                                         st,pins {
 121                                                 ir = <&pio4 0 ALT2 IN>;
 122                                         };
 123                                 };
 124                         };
 125
 126                         /* SBC_ASC0 - UART10 */
 127                         sbc_serial0 {
 128                                 pinctrl_sbc_serial0: sbc_serial0-0 {
 129                                         st,pins {
 130                                                 tx = <&pio3 4 ALT1 OUT>;
 131                                                 rx = <&pio3 5 ALT1 IN>;
 132                                         };
 133                                 };
 134                         };
 135                         /* SBC_ASC1 - UART11 */
 136                         sbc_serial1 {
 137                                 pinctrl_sbc_serial1: sbc_serial1-0 {
 138                                         st,pins {
 139                                                 tx = <&pio2 6 ALT3 OUT>;
 140                                                 rx = <&pio2 7 ALT3 IN>;
 141                                         };
 142                                 };
 143                         };
 144
 145                         i2c10 {
 146                                 pinctrl_i2c10_default: i2c10-default {
 147                                         st,pins {
 148                                                 sda = <&pio4 6 ALT1 BIDIR>;
 149                                                 scl = <&pio4 5 ALT1 BIDIR>;
 150                                         };
 151                                 };
 152                         };
 153
 154                         i2c11 {
 155                                 pinctrl_i2c11_default: i2c11-default {
 156                                         st,pins {
 157                                                 sda = <&pio5 1 ALT1 BIDIR>;
 158                                                 scl = <&pio5 0 ALT1 BIDIR>;
 159                                         };
 160                                 };
 161                         };
 162
 163                         keyscan {
 164                                 pinctrl_keyscan: keyscan {
 165                                         st,pins {
 166                                                 keyin0 = <&pio4 0 ALT6 IN>;
 167                                                 keyin1 = <&pio4 5 ALT4 IN>;
 168                                                 keyin2 = <&pio0 4 ALT2 IN>;
 169                                                 keyin3 = <&pio2 6 ALT2 IN>;
 170
 171                                                 keyout0 = <&pio4 6 ALT4 OUT>;
 172                                                 keyout1 = <&pio1 7 ALT2 OUT>;
 173                                                 keyout2 = <&pio0 6 ALT2 OUT>;
 174                                                 keyout3 = <&pio2 7 ALT2 OUT>;
 175                                         };
 176                                 };
 177                         };
 178
 179                         gmac1 {
 180                                 /*
 181                                  * Almost all the boards based on STiH407 SoC have an embedded
 182                                  * switch where the mdio/mdc have been used for managing the SMI
 183                                  * iface via I2C. For this reason these lines can be allocated
 184                                  * by using dedicated configuration (in case of there will be a
 185                                  * standard PHY transceiver on-board).
 186                                  */
 187                                 pinctrl_rgmii1: rgmii1-0 {
 188                                         st,pins {
 189
 190                                                 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
 191                                                 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
 192                                                 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
 193                                                 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
 194                                                 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
 195                                                 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
 196                                                 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
 197                                                 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
 198                                                 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
 199                                                 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
 200                                                 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
 201                                                 rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
 202                                                 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
 203                                                 phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
 204                                         };
 205                                 };
 206
 207                                 pinctrl_rgmii1_mdio: rgmii1-mdio {
 208                                         st,pins {
 209                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
 210                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 211                                                 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
 212                                         };
 213                                 };
 214
 215                                 pinctrl_mii1: mii1 {
 216                                         st,pins {
 217                                                 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 218                                                 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 219                                                 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 220                                                 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 221                                                 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 222                                                 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 223                                                 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
 224                                                 col = <&pio0 7 ALT1 IN BYPASS 1000>;
 225
 226                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
 227                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 228                                                 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
 229                                                 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
 230                                                 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 231                                                 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 232                                                 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 233                                                 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 234
 235                                                 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 236                                                 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 237                                                 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
 238                                                 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
 239                                         };
 240                                 };
 241                         };
 242
 243                         pwm1 {
 244                                 pinctrl_pwm1_chan0_default: pwm1-0-default {
 245                                         st,pins {
 246                                                 pwm-out = <&pio3 0 ALT1 OUT>;
 247                                         };
 248                                 };
 249                                 pinctrl_pwm1_chan1_default: pwm1-1-default {
 250                                         st,pins {
 251                                                 pwm-out = <&pio4 4 ALT1 OUT>;
 252                                         };
 253                                 };
 254                                 pinctrl_pwm1_chan2_default: pwm1-2-default {
 255                                         st,pins {
 256                                                 pwm-out = <&pio4 6 ALT3 OUT>;
 257                                         };
 258                                 };
 259                                 pinctrl_pwm1_chan3_default: pwm1-3-default {
 260                                         st,pins {
 261                                                 pwm-out = <&pio4 7 ALT3 OUT>;
 262                                         };
 263                                 };
 264                         };
 265
 266                         spi10 {
 267                                 pinctrl_spi10_default: spi10-4w-alt1-0 {
 268                                         st,pins {
 269                                                 mtsr = <&pio4 6 ALT1 OUT>;
 270                                                 mrst = <&pio4 7 ALT1 IN>;
 271                                                 scl = <&pio4 5 ALT1 OUT>;
 272                                         };
 273                                 };
 274
 275                                 pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
 276                                         st,pins {
 277                                                 mtsr = <&pio4 6 ALT1 BIDIR_PU>;
 278                                                 scl = <&pio4 5 ALT1 OUT>;
 279                                         };
 280                                 };
 281                         };
 282
 283                         spi11 {
 284                                 pinctrl_spi11_default: spi11-4w-alt2-0 {
 285                                         st,pins {
 286                                                 mtsr = <&pio3 1 ALT2 OUT>;
 287                                                 mrst = <&pio3 0 ALT2 IN>;
 288                                                 scl = <&pio3 2 ALT2 OUT>;
 289                                         };
 290                                 };
 291
 292                                 pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
 293                                         st,pins {
 294                                                 mtsr = <&pio3 1 ALT2 BIDIR_PU>;
 295                                                 scl = <&pio3 2 ALT2 OUT>;
 296                                         };
 297                                 };
 298                         };
 299
 300                         spi12 {
 301                                 pinctrl_spi12_default: spi12-4w-alt2-0 {
 302                                         st,pins {
 303                                                 mtsr = <&pio3 6 ALT2 OUT>;
 304                                                 mrst = <&pio3 4 ALT2 IN>;
 305                                                 scl = <&pio3 7 ALT2 OUT>;
 306                                         };
 307                                 };
 308
 309                                 pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
 310                                         st,pins {
 311                                                 mtsr = <&pio3 6 ALT2 BIDIR_PU>;
 312                                                 scl = <&pio3 7 ALT2 OUT>;
 313                                         };
 314                                 };
 315                         };
 316                 };
 317
 318                 pin-controller-front0 {
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         compatible = "st,stih407-front-pinctrl";
 322                         st,syscfg = <&syscfg_front>;
 323                         reg = <0x0920f080 0x4>;
 324                         reg-names = "irqmux";
 325                         interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
 326                         interrupts-names = "irqmux";
 327                         ranges = <0 0x09200000 0x10000>;
 328
 329                         pio10: pio@09200000 {
 330                                 gpio-controller;
 331                                 #gpio-cells = <1>;
 332                                 interrupt-controller;
 333                                 #interrupt-cells = <2>;
 334                                 reg = <0x0 0x100>;
 335                                 st,bank-name = "PIO10";
 336                         };
 337                         pio11: pio@09201000 {
 338                                 gpio-controller;
 339                                 #gpio-cells = <1>;
 340                                 interrupt-controller;
 341                                 #interrupt-cells = <2>;
 342                                 reg = <0x1000 0x100>;
 343                                 st,bank-name = "PIO11";
 344                         };
 345                         pio12: pio@09202000 {
 346                                 gpio-controller;
 347                                 #gpio-cells = <1>;
 348                                 interrupt-controller;
 349                                 #interrupt-cells = <2>;
 350                                 reg = <0x2000 0x100>;
 351                                 st,bank-name = "PIO12";
 352                         };
 353                         pio13: pio@09203000 {
 354                                 gpio-controller;
 355                                 #gpio-cells = <1>;
 356                                 interrupt-controller;
 357                                 #interrupt-cells = <2>;
 358                                 reg = <0x3000 0x100>;
 359                                 st,bank-name = "PIO13";
 360                         };
 361                         pio14: pio@09204000 {
 362                                 gpio-controller;
 363                                 #gpio-cells = <1>;
 364                                 interrupt-controller;
 365                                 #interrupt-cells = <2>;
 366                                 reg = <0x4000 0x100>;
 367                                 st,bank-name = "PIO14";
 368                         };
 369                         pio15: pio@09205000 {
 370                                 gpio-controller;
 371                                 #gpio-cells = <1>;
 372                                 interrupt-controller;
 373                                 #interrupt-cells = <2>;
 374                                 reg = <0x5000 0x100>;
 375                                 st,bank-name = "PIO15";
 376                         };
 377                         pio16: pio@09206000 {
 378                                 gpio-controller;
 379                                 #gpio-cells = <1>;
 380                                 interrupt-controller;
 381                                 #interrupt-cells = <2>;
 382                                 reg = <0x6000 0x100>;
 383                                 st,bank-name = "PIO16";
 384                         };
 385                         pio17: pio@09207000 {
 386                                 gpio-controller;
 387                                 #gpio-cells = <1>;
 388                                 interrupt-controller;
 389                                 #interrupt-cells = <2>;
 390                                 reg = <0x7000 0x100>;
 391                                 st,bank-name = "PIO17";
 392                         };
 393                         pio18: pio@09208000 {
 394                                 gpio-controller;
 395                                 #gpio-cells = <1>;
 396                                 interrupt-controller;
 397                                 #interrupt-cells = <2>;
 398                                 reg = <0x8000 0x100>;
 399                                 st,bank-name = "PIO18";
 400                         };
 401                         pio19: pio@09209000 {
 402                                 gpio-controller;
 403                                 #gpio-cells = <1>;
 404                                 interrupt-controller;
 405                                 #interrupt-cells = <2>;
 406                                 reg = <0x9000 0x100>;
 407                                 st,bank-name = "PIO19";
 408                         };
 409
 410                         /* Comms */
 411                         serial0 {
 412                                 pinctrl_serial0: serial0-0 {
 413                                         st,pins {
 414                                                 tx = <&pio17 0 ALT1 OUT>;
 415                                                 rx = <&pio17 1 ALT1 IN>;
 416                                         };
 417                                 };
 418                         };
 419
 420                         serial1 {
 421                                 pinctrl_serial1: serial1-0 {
 422                                         st,pins {
 423                                                 tx = <&pio16 0 ALT1 OUT>;
 424                                                 rx = <&pio16 1 ALT1 IN>;
 425                                         };
 426                                 };
 427                         };
 428
 429                         serial2 {
 430                                 pinctrl_serial2: serial2-0 {
 431                                         st,pins {
 432                                                 tx = <&pio15 0 ALT1 OUT>;
 433                                                 rx = <&pio15 1 ALT1 IN>;
 434                                         };
 435                                 };
 436                         };
 437
 438                         mmc1 {
 439                                 pinctrl_sd1: sd1-0 {
 440                                         st,pins {
 441                                                 sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
 442                                                 sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
 443                                                 sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
 444                                                 sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
 445                                                 sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
 446                                                 sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
 447                                                 sd_led = <&pio16 6 ALT6 OUT>;
 448                                                 sd_pwren = <&pio16 7 ALT6 OUT>;
 449                                                 sd_cd = <&pio19 0 ALT6 IN>;
 450                                                 sd_wp = <&pio19 1 ALT6 IN>;
 451                                         };
 452                                 };
 453                         };
 454
 455
 456                         i2c0 {
 457                                 pinctrl_i2c0_default: i2c0-default {
 458                                         st,pins {
 459                                                 sda = <&pio10 6 ALT2 BIDIR>;
 460                                                 scl = <&pio10 5 ALT2 BIDIR>;
 461                                         };
 462                                 };
 463                         };
 464
 465                         i2c1 {
 466                                 pinctrl_i2c1_default: i2c1-default {
 467                                         st,pins {
 468                                                 sda = <&pio11 1 ALT2 BIDIR>;
 469                                                 scl = <&pio11 0 ALT2 BIDIR>;
 470                                         };
 471                                 };
 472                         };
 473
 474                         i2c2 {
 475                                 pinctrl_i2c2_default: i2c2-default {
 476                                         st,pins {
 477                                                 sda = <&pio15 6 ALT2 BIDIR>;
 478                                                 scl = <&pio15 5 ALT2 BIDIR>;
 479                                         };
 480                                 };
 481                         };
 482
 483                         i2c3 {
 484                                 pinctrl_i2c3_default: i2c3-alt1-0 {
 485                                         st,pins {
 486                                                 sda = <&pio18 6 ALT1 BIDIR>;
 487                                                 scl = <&pio18 5 ALT1 BIDIR>;
 488                                         };
 489                                 };
 490                                 pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
 491                                         st,pins {
 492                                                 sda = <&pio17 7 ALT1 BIDIR>;
 493                                                 scl = <&pio17 6 ALT1 BIDIR>;
 494                                         };
 495                                 };
 496                                 pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
 497                                         st,pins {
 498                                                 sda = <&pio13 6 ALT3 BIDIR>;
 499                                                 scl = <&pio13 5 ALT3 BIDIR>;
 500                                         };
 501                                 };
 502                         };
 503
 504                         spi0 {
 505                                 pinctrl_spi0_default: spi0-4w-alt2-0 {
 506                                         st,pins {
 507                                                 mtsr = <&pio10 6 ALT2 OUT>;
 508                                                 mrst = <&pio10 7 ALT2 IN>;
 509                                                 scl = <&pio10 5 ALT2 OUT>;
 510                                         };
 511                                 };
 512
 513                                 pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
 514                                         st,pins {
 515                                                 mtsr = <&pio10 6 ALT2 BIDIR_PU>;
 516                                                 scl = <&pio10 5 ALT2 OUT>;
 517                                         };
 518                                 };
 519
 520                                 pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
 521                                         st,pins {
 522                                                 mtsr = <&pio19 7 ALT1 OUT>;
 523                                                 mrst = <&pio19 5 ALT1 IN>;
 524                                                 scl = <&pio19 6 ALT1 OUT>;
 525                                         };
 526                                 };
 527
 528                                 pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
 529                                         st,pins {
 530                                                 mtsr = <&pio19 7 ALT1 BIDIR_PU>;
 531                                                 scl = <&pio19 6 ALT1 OUT>;
 532                                         };
 533                                 };
 534                         };
 535
 536                         spi1 {
 537                                 pinctrl_spi1_default: spi1-4w-alt2-0 {
 538                                         st,pins {
 539                                                 mtsr = <&pio11 1 ALT2 OUT>;
 540                                                 mrst = <&pio11 2 ALT2 IN>;
 541                                                 scl = <&pio11 0 ALT2 OUT>;
 542                                         };
 543                                 };
 544
 545                                 pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
 546                                         st,pins {
 547                                                 mtsr = <&pio11 1 ALT2 BIDIR_PU>;
 548                                                 scl = <&pio11 0 ALT2 OUT>;
 549                                         };
 550                                 };
 551
 552                                 pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
 553                                         st,pins {
 554                                                 mtsr = <&pio14 3 ALT1 OUT>;
 555                                                 mrst = <&pio14 4 ALT1 IN>;
 556                                                 scl = <&pio14 2 ALT1 OUT>;
 557                                         };
 558                                 };
 559
 560                                 pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
 561                                         st,pins {
 562                                                 mtsr = <&pio14 3 ALT1 BIDIR_PU>;
 563                                                 scl = <&pio14 2 ALT1 OUT>;
 564                                         };
 565                                 };
 566                         };
 567
 568                         spi2 {
 569                                 pinctrl_spi2_default: spi2-4w-alt2-0 {
 570                                         st,pins {
 571                                                 mtsr = <&pio12 6 ALT2 OUT>;
 572                                                 mrst = <&pio12 7 ALT2 IN>;
 573                                                 scl = <&pio12 5 ALT2 OUT>;
 574                                         };
 575                                 };
 576
 577                                 pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
 578                                         st,pins {
 579                                                 mtsr = <&pio12 6 ALT2 BIDIR_PU>;
 580                                                 scl = <&pio12 5 ALT2 OUT>;
 581                                         };
 582                                 };
 583
 584                                 pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
 585                                         st,pins {
 586                                                 mtsr = <&pio14 6 ALT1 OUT>;
 587                                                 mrst = <&pio14 7 ALT1 IN>;
 588                                                 scl = <&pio14 5 ALT1 OUT>;
 589                                         };
 590                                 };
 591
 592                                 pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
 593                                         st,pins {
 594                                                 mtsr = <&pio14 6 ALT1 BIDIR_PU>;
 595                                                 scl = <&pio14 5 ALT1 OUT>;
 596                                         };
 597                                 };
 598
 599                                 pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
 600                                         st,pins {
 601                                                 mtsr = <&pio15 6 ALT2 OUT>;
 602                                                 mrst = <&pio15 7 ALT2 IN>;
 603                                                 scl = <&pio15 5 ALT2 OUT>;
 604                                         };
 605                                 };
 606
 607                                 pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
 608                                         st,pins {
 609                                                 mtsr = <&pio15 6 ALT2 BIDIR_PU>;
 610                                                 scl = <&pio15 5 ALT2 OUT>;
 611                                         };
 612                                 };
 613                         };
 614
 615                         spi3 {
 616                                 pinctrl_spi3_default: spi3-4w-alt3-0 {
 617                                         st,pins {
 618                                                 mtsr = <&pio13 6 ALT3 OUT>;
 619                                                 mrst = <&pio13 7 ALT3 IN>;
 620                                                 scl = <&pio13 5 ALT3 OUT>;
 621                                         };
 622                                 };
 623
 624                                 pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
 625                                         st,pins {
 626                                                 mtsr = <&pio13 6 ALT3 BIDIR_PU>;
 627                                                 scl = <&pio13 5 ALT3 OUT>;
 628                                         };
 629                                 };
 630
 631                                 pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
 632                                         st,pins {
 633                                                 mtsr = <&pio17 7 ALT1 OUT>;
 634                                                 mrst = <&pio17 5 ALT1 IN>;
 635                                                 scl = <&pio17 6 ALT1 OUT>;
 636                                         };
 637                                 };
 638
 639                                 pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
 640                                         st,pins {
 641                                                 mtsr = <&pio17 7 ALT1 BIDIR_PU>;
 642                                                 scl = <&pio17 6 ALT1 OUT>;
 643                                         };
 644                                 };
 645
 646                                 pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
 647                                         st,pins {
 648                                                 mtsr = <&pio18 6 ALT1 OUT>;
 649                                                 mrst = <&pio18 7 ALT1 IN>;
 650                                                 scl = <&pio18 5 ALT1 OUT>;
 651                                         };
 652                                 };
 653
 654                                 pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
 655                                         st,pins {
 656                                                 mtsr = <&pio18 6 ALT1 BIDIR_PU>;
 657                                                 scl = <&pio18 5 ALT1 OUT>;
 658                                         };
 659                                 };
 660                         };
 661
 662                         tsin0 {
 663                                 pinctrl_tsin0_parallel: tsin0_parallel {
 664                                         st,pins {
 665                                                 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 666                                                 DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 667                                                 DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 668                                                 DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 669                                                 DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 670                                                 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 671                                                 DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 672                                                 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 673                                                 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 674                                                 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 675                                                 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 676                                                 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 677                                         };
 678                                 };
 679                                 pinctrl_tsin0_serial: tsin0_serial {
 680                                         st,pins {
 681                                                 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 682                                                 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 683                                                 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 684                                                 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 685                                                 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 686                                         };
 687                                 };
 688                         };
 689
 690                         tsin1 {
 691                                 pinctrl_tsin1_parallel: tsin1_parallel {
 692                                         st,pins {
 693                                                 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 694                                                 DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 695                                                 DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 696                                                 DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 697                                                 DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 698                                                 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 699                                                 DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 700                                                 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 701                                                 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
 702                                                 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 703                                                 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 704                                                 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 705                                         };
 706                                 };
 707                                 pinctrl_tsin1_serial: tsin1_serial {
 708                                         st,pins {
 709                                                 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 710                                                 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
 711                                                 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 712                                                 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 713                                                 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 714                                         };
 715                                 };
 716                         };
 717
 718                         tsin2 {
 719                                 pinctrl_tsin2_parallel: tsin2_parallel {
 720                                         st,pins {
 721                                                 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 722                                                 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 723                                                 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 724                                                 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 725                                                 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 726                                                 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 727                                                 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 728                                                 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 729                                                 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 730                                                 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 731                                                 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 732                                                 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 733                                         };
 734                                 };
 735                                 pinctrl_tsin2_serial: tsin2_serial {
 736                                         st,pins {
 737                                                 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 738                                                 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 739                                                 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 740                                                 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 741                                                 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 742                                         };
 743                                 };
 744                         };
 745
 746                         tsin3 {
 747                                 pinctrl_tsin3_serial: tsin3_serial {
 748                                         st,pins {
 749                                                 DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 750                                                 CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
 751                                                 VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 752                                                 ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 753                                                 PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 754                                         };
 755                                 };
 756                         };
 757
 758                         tsin4 {
 759                                 pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
 760                                         st,pins {
 761                                                 DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 762                                                 CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
 763                                                 VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
 764                                                 ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
 765                                                 PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 766                                         };
 767                                 };
 768                         };
 769
 770                         tsin5 {
 771                                 pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
 772                                         st,pins {
 773                                                 DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 774                                                 CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 775                                                 VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 776                                                 ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 777                                                 PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 778                                         };
 779                                 };
 780                                 pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
 781                                         st,pins {
 782                                                 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 783                                                 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
 784                                                 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 785                                                 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 786                                                 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 787                                         };
 788                                 };
 789                         };
 790
 791                         tsout0 {
 792                                 pinctrl_tsout0_parallel: tsout0_parallel {
 793                                         st,pins {
 794                                                 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 795                                                 DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 796                                                 DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 797                                                 DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 798                                                 DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 799                                                 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 800                                                 DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 801                                                 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 802                                                 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
 803                                                 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 804                                                 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 805                                                 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 806                                         };
 807                                 };
 808                                 pinctrl_tsout0_serial: tsout0_serial {
 809                                         st,pins {
 810                                                 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 811                                                 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
 812                                                 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 813                                                 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 814                                                 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 815                                         };
 816                                 };
 817                         };
 818
 819                         tsout1 {
 820                                 pinctrl_tsout1_serial: tsout1_serial {
 821                                         st,pins {
 822                                                 DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 823                                                 CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
 824                                                 VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 825                                                 ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 826                                                 PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 827                                         };
 828                                 };
 829                         };
 830
 831                         mtsin0 {
 832                                 pinctrl_mtsin0_parallel: mtsin0_parallel {
 833                                         st,pins {
 834                                                 DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 835                                                 DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 836                                                 DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 837                                                 DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 838                                                 DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 839                                                 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 840                                                 DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 841                                                 DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 842                                                 CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
 843                                                 VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 844                                                 ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 845                                                 PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 846                                         };
 847                                 };
 848                         };
 849                 };
 850
 851                 pin-controller-front1 {
 852                         #address-cells = <1>;
 853                         #size-cells = <1>;
 854                         compatible = "st,stih407-front-pinctrl";
 855                         st,syscfg = <&syscfg_front>;
 856                         reg = <0x0921f080 0x4>;
 857                         reg-names = "irqmux";
 858                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 859                         interrupts-names = "irqmux";
 860                         ranges = <0 0x09210000 0x10000>;
 861
 862                         tsin4 {
 863                                 pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
 864                                         st,pins {
 865                                                 DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 866                                                 CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 867                                                 VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 868                                                 ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 869                                                 PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 870                                         };
 871                                 };
 872                         };
 873
 874                         pio20: pio@09210000 {
 875                                 gpio-controller;
 876                                 #gpio-cells = <1>;
 877                                 interrupt-controller;
 878                                 #interrupt-cells = <2>;
 879                                 reg = <0x0 0x100>;
 880                                 st,bank-name = "PIO20";
 881                         };
 882                 };
 883
 884                 pin-controller-rear {
 885                         #address-cells = <1>;
 886                         #size-cells = <1>;
 887                         compatible = "st,stih407-rear-pinctrl";
 888                         st,syscfg = <&syscfg_rear>;
 889                         reg = <0x0922f080 0x4>;
 890                         reg-names = "irqmux";
 891                         interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
 892                         interrupts-names = "irqmux";
 893                         ranges = <0 0x09220000 0x6000>;
 894
 895                         pio30: gpio@09220000 {
 896                                 gpio-controller;
 897                                 #gpio-cells = <1>;
 898                                 interrupt-controller;
 899                                 #interrupt-cells = <2>;
 900                                 reg = <0x0 0x100>;
 901                                 st,bank-name = "PIO30";
 902                         };
 903                         pio31: gpio@09221000 {
 904                                 gpio-controller;
 905                                 #gpio-cells = <1>;
 906                                 interrupt-controller;
 907                                 #interrupt-cells = <2>;
 908                                 reg = <0x1000 0x100>;
 909                                 st,bank-name = "PIO31";
 910                         };
 911                         pio32: gpio@09222000 {
 912                                 gpio-controller;
 913                                 #gpio-cells = <1>;
 914                                 interrupt-controller;
 915                                 #interrupt-cells = <2>;
 916                                 reg = <0x2000 0x100>;
 917                                 st,bank-name = "PIO32";
 918                         };
 919                         pio33: gpio@09223000 {
 920                                 gpio-controller;
 921                                 #gpio-cells = <1>;
 922                                 interrupt-controller;
 923                                 #interrupt-cells = <2>;
 924                                 reg = <0x3000 0x100>;
 925                                 st,bank-name = "PIO33";
 926                         };
 927                         pio34: gpio@09224000 {
 928                                 gpio-controller;
 929                                 #gpio-cells = <1>;
 930                                 interrupt-controller;
 931                                 #interrupt-cells = <2>;
 932                                 reg = <0x4000 0x100>;
 933                                 st,bank-name = "PIO34";
 934                         };
 935                         pio35: gpio@09225000 {
 936                                 gpio-controller;
 937                                 #gpio-cells = <1>;
 938                                 interrupt-controller;
 939                                 #interrupt-cells = <2>;
 940                                 reg = <0x5000 0x100>;
 941                                 st,bank-name = "PIO35";
 942                                 st,retime-pin-mask = <0x7f>;
 943                         };
 944
 945                         i2c4 {
 946                                 pinctrl_i2c4_default: i2c4-default {
 947                                         st,pins {
 948                                                 sda = <&pio30 1 ALT1 BIDIR>;
 949                                                 scl = <&pio30 0 ALT1 BIDIR>;
 950                                         };
 951                                 };
 952                         };
 953
 954                         i2c5 {
 955                                 pinctrl_i2c5_default: i2c5-default {
 956                                         st,pins {
 957                                                 sda = <&pio34 4 ALT1 BIDIR>;
 958                                                 scl = <&pio34 3 ALT1 BIDIR>;
 959                                         };
 960                                 };
 961                         };
 962
 963                         usb3 {
 964                                 pinctrl_usb3: usb3-2 {
 965                                         st,pins {
 966                                                 usb-oc-detect = <&pio35 4 ALT1 IN>;
 967                                                 usb-pwr-enable = <&pio35 5 ALT1 OUT>;
 968                                                 usb-vbus-valid = <&pio35 6 ALT1 IN>;
 969                                         };
 970                                 };
 971                         };
 972
 973                         pwm0 {
 974                                 pinctrl_pwm0_chan0_default: pwm0-0-default {
 975                                         st,pins {
 976                                                 pwm-out = <&pio31 1 ALT1 OUT>;
 977                                         };
 978                                 };
 979                         };
 980
 981                         spi4 {
 982                                 pinctrl_spi4_default: spi4-4w-alt1-0 {
 983                                         st,pins {
 984                                                 mtsr = <&pio30 1 ALT1 OUT>;
 985                                                 mrst = <&pio30 2 ALT1 IN>;
 986                                                 scl = <&pio30 0 ALT1 OUT>;
 987                                         };
 988                                 };
 989
 990                                 pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
 991                                         st,pins {
 992                                                 mtsr = <&pio30 1 ALT1 BIDIR_PU>;
 993                                                 scl = <&pio30 0 ALT1 OUT>;
 994                                         };
 995                                 };
 996
 997                                 pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
 998                                         st,pins {
 999                                                 mtsr = <&pio34 1 ALT3 OUT>;
1000                                                 mrst = <&pio34 2 ALT3 IN>;
1001                                                 scl = <&pio34 0 ALT3 OUT>;
1002                                         };
1003                                 };
1004
1005                                 pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
1006                                         st,pins {
1007                                                 mtsr = <&pio34 1 ALT3 BIDIR_PU>;
1008                                                 scl = <&pio34 0 ALT3 OUT>;
1009                                         };
1010                                 };
1011                         };
1012                 };
1013
1014                 pin-controller-flash {
1015                         #address-cells = <1>;
1016                         #size-cells = <1>;
1017                         compatible = "st,stih407-flash-pinctrl";
1018                         st,syscfg = <&syscfg_flash>;
1019                         reg = <0x0923f080 0x4>;
1020                         reg-names = "irqmux";
1021                         interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
1022                         interrupts-names = "irqmux";
1023                         ranges = <0 0x09230000 0x3000>;
1024
1025                         pio40: gpio@09230000 {
1026                                 gpio-controller;
1027                                 #gpio-cells = <1>;
1028                                 interrupt-controller;
1029                                 #interrupt-cells = <2>;
1030                                 reg = <0 0x100>;
1031                                 st,bank-name = "PIO40";
1032                         };
1033                         pio41: gpio@09231000 {
1034                                 gpio-controller;
1035                                 #gpio-cells = <1>;
1036                                 interrupt-controller;
1037                                 #interrupt-cells = <2>;
1038                                 reg = <0x1000 0x100>;
1039                                 st,bank-name = "PIO41";
1040                         };
1041                         pio42: gpio@09232000 {
1042                                 gpio-controller;
1043                                 #gpio-cells = <1>;
1044                                 interrupt-controller;
1045                                 #interrupt-cells = <2>;
1046                                 reg = <0x2000 0x100>;
1047                                 st,bank-name = "PIO42";
1048                         };
1049
1050                         mmc0 {
1051                                 pinctrl_mmc0: mmc0-0 {
1052                                         st,pins {
1053                                                 emmc_clk = <&pio40 6 ALT1 BIDIR>;
1054                                                 emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1055                                                 emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
1056                                                 emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
1057                                                 emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
1058                                                 emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
1059                                                 emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
1060                                                 emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
1061                                                 emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
1062                                                 emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
1063                                         };
1064                                 };
1065                         };
1066                 };
1067         };
1068 };