2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 compatible = "st,stih415-sbc-pinctrl";
48 st,syscfg = <&syscfg_sbc>;
49 reg = <0xfe61f080 0x4>;
51 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
52 interrupts-names = "irqmux";
53 ranges = <0 0xfe610000 0x5000>;
59 #interrupt-cells = <2>;
61 st,bank-name = "PIO0";
67 #interrupt-cells = <2>;
69 st,bank-name = "PIO1";
75 #interrupt-cells = <2>;
77 st,bank-name = "PIO2";
83 #interrupt-cells = <2>;
85 st,bank-name = "PIO3";
91 #interrupt-cells = <2>;
93 st,bank-name = "PIO4";
97 pinctrl_sbc_serial1:sbc_serial1 {
99 tx = <&PIO2 6 ALT3 OUT>;
100 rx = <&PIO2 7 ALT3 IN>;
106 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
108 sda = <&PIO4 6 ALT1 BIDIR>;
109 scl = <&PIO4 5 ALT1 BIDIR>;
115 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
117 sda = <&PIO3 2 ALT2 BIDIR>;
118 scl = <&PIO3 1 ALT2 BIDIR>;
126 ir = <&PIO4 0 ALT2 IN>;
134 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
135 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
136 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
137 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
138 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
139 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
140 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
141 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
142 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
143 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
144 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
145 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
146 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
147 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
148 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
149 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
150 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
151 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
152 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
153 phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
157 pinctrl_rgmii1: rgmii1-0 {
159 txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
160 txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
161 txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
162 txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
163 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
164 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
165 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
166 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
167 rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
168 rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
169 rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
170 rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
172 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
173 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
174 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
176 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
182 pin-controller-front {
183 #address-cells = <1>;
185 compatible = "st,stih415-front-pinctrl";
186 st,syscfg = <&syscfg_front>;
187 reg = <0xfee0f080 0x4>;
188 reg-names = "irqmux";
189 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
190 interrupts-names = "irqmux";
191 ranges = <0 0xfee00000 0x8000>;
193 PIO5: gpio@fee00000 {
196 interrupt-controller;
197 #interrupt-cells = <2>;
199 st,bank-name = "PIO5";
201 PIO6: gpio@fee01000 {
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 reg = <0x1000 0x100>;
207 st,bank-name = "PIO6";
209 PIO7: gpio@fee02000 {
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 reg = <0x2000 0x100>;
215 st,bank-name = "PIO7";
217 PIO8: gpio@fee03000 {
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 reg = <0x3000 0x100>;
223 st,bank-name = "PIO8";
225 PIO9: gpio@fee04000 {
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 reg = <0x4000 0x100>;
231 st,bank-name = "PIO9";
233 PIO10: gpio@fee05000 {
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 reg = <0x5000 0x100>;
239 st,bank-name = "PIO10";
241 PIO11: gpio@fee06000 {
244 interrupt-controller;
245 #interrupt-cells = <2>;
246 reg = <0x6000 0x100>;
247 st,bank-name = "PIO11";
249 PIO12: gpio@fee07000 {
252 interrupt-controller;
253 #interrupt-cells = <2>;
254 reg = <0x7000 0x100>;
255 st,bank-name = "PIO12";
259 pinctrl_i2c0_default: i2c0-default {
261 sda = <&PIO9 3 ALT1 BIDIR>;
262 scl = <&PIO9 2 ALT1 BIDIR>;
268 pinctrl_i2c1_default: i2c1-default {
270 sda = <&PIO12 1 ALT1 BIDIR>;
271 scl = <&PIO12 0 ALT1 BIDIR>;
277 pin-controller-rear {
278 #address-cells = <1>;
280 compatible = "st,stih415-rear-pinctrl";
281 st,syscfg = <&syscfg_rear>;
282 reg = <0xfe82f080 0x4>;
283 reg-names = "irqmux";
284 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
285 interrupts-names = "irqmux";
286 ranges = <0 0xfe820000 0x8000>;
288 PIO13: gpio@fe820000 {
291 interrupt-controller;
292 #interrupt-cells = <2>;
294 st,bank-name = "PIO13";
296 PIO14: gpio@fe821000 {
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 reg = <0x1000 0x100>;
302 st,bank-name = "PIO14";
304 PIO15: gpio@fe822000 {
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 reg = <0x2000 0x100>;
310 st,bank-name = "PIO15";
312 PIO16: gpio@fe823000 {
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 reg = <0x3000 0x100>;
318 st,bank-name = "PIO16";
320 PIO17: gpio@fe824000 {
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 reg = <0x4000 0x100>;
326 st,bank-name = "PIO17";
328 PIO18: gpio@fe825000 {
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 reg = <0x5000 0x100>;
334 st,bank-name = "PIO18";
338 pinctrl_serial2: serial2-0 {
340 tx = <&PIO17 4 ALT2 OUT>;
341 rx = <&PIO17 5 ALT2 IN>;
349 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
350 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
352 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
353 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
354 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
355 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
357 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
358 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
359 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
360 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
361 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
362 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
364 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
365 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
366 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
367 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
368 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
369 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
370 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
371 phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
376 pinctrl_gmii0: gmii0 {
378 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
379 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
380 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
381 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
383 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
384 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
385 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
386 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
387 txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
388 txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
389 txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
390 txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
392 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
393 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
394 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
395 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
396 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
397 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
399 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
400 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
401 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
402 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
403 rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
404 rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
405 rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
406 rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
408 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
409 clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
410 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
418 pin-controller-left {
419 #address-cells = <1>;
421 compatible = "st,stih415-left-pinctrl";
422 st,syscfg = <&syscfg_left>;
423 reg = <0xfd6bf080 0x4>;
424 reg-names = "irqmux";
425 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
426 interrupts-names = "irqmux";
427 ranges = <0 0xfd6b0000 0x3000>;
429 PIO100: gpio@fd6b0000 {
432 interrupt-controller;
433 #interrupt-cells = <2>;
435 st,bank-name = "PIO100";
437 PIO101: gpio@fd6b1000 {
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 reg = <0x1000 0x100>;
443 st,bank-name = "PIO101";
445 PIO102: gpio@fd6b2000 {
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 reg = <0x2000 0x100>;
451 st,bank-name = "PIO102";
455 pin-controller-right {
456 #address-cells = <1>;
458 compatible = "st,stih415-right-pinctrl";
459 st,syscfg = <&syscfg_right>;
460 reg = <0xfd33f080 0x4>;
461 reg-names = "irqmux";
462 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
463 interrupts-names = "irqmux";
464 ranges = <0 0xfd330000 0x5000>;
466 PIO103: gpio@fd330000 {
469 interrupt-controller;
470 #interrupt-cells = <2>;
472 st,bank-name = "PIO103";
474 PIO104: gpio@fd331000 {
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 reg = <0x1000 0x100>;
480 st,bank-name = "PIO104";
482 PIO105: gpio@fd332000 {
485 interrupt-controller;
486 #interrupt-cells = <2>;
487 reg = <0x2000 0x100>;
488 st,bank-name = "PIO105";
490 PIO106: gpio@fd333000 {
493 interrupt-controller;
494 #interrupt-cells = <2>;
495 reg = <0x3000 0x100>;
496 st,bank-name = "PIO106";
498 PIO107: gpio@fd334000 {
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 reg = <0x4000 0x100>;
504 st,bank-name = "PIO107";