2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f7-rcc.h>
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
65 compatible = "fixed-clock";
66 clock-frequency = <32000>;
69 clk_i2s_ckin: clk-i2s-ckin {
71 compatible = "fixed-clock";
72 clock-frequency = <48000000>;
77 timer2: timer@40000000 {
78 compatible = "st,stm32-timer";
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
85 timer3: timer@40000400 {
86 compatible = "st,stm32-timer";
87 reg = <0x40000400 0x400>;
89 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
93 timer4: timer@40000800 {
94 compatible = "st,stm32-timer";
95 reg = <0x40000800 0x400>;
97 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
101 timer5: timer@40000c00 {
102 compatible = "st,stm32-timer";
103 reg = <0x40000c00 0x400>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
108 timer6: timer@40001000 {
109 compatible = "st,stm32-timer";
110 reg = <0x40001000 0x400>;
112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
116 timer7: timer@40001400 {
117 compatible = "st,stm32-timer";
118 reg = <0x40001400 0x400>;
120 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
125 compatible = "st,stm32-rtc";
126 reg = <0x40002800 0x400>;
127 clocks = <&rcc 1 CLK_RTC>;
128 clock-names = "ck_rtc";
129 assigned-clocks = <&rcc 1 CLK_RTC>;
130 assigned-clock-parents = <&rcc 1 CLK_LSE>;
131 interrupt-parent = <&exti>;
133 interrupt-names = "alarm";
134 st,syscfg = <&pwrcfg>;
138 usart2: serial@40004400 {
139 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
140 reg = <0x40004400 0x400>;
142 clocks = <&rcc 1 CLK_USART2>;
146 usart3: serial@40004800 {
147 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
148 reg = <0x40004800 0x400>;
150 clocks = <&rcc 1 CLK_USART3>;
154 usart4: serial@40004c00 {
155 compatible = "st,stm32f7-uart";
156 reg = <0x40004c00 0x400>;
158 clocks = <&rcc 1 CLK_UART4>;
162 usart5: serial@40005000 {
163 compatible = "st,stm32f7-uart";
164 reg = <0x40005000 0x400>;
166 clocks = <&rcc 1 CLK_UART5>;
170 usart7: serial@40007800 {
171 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
172 reg = <0x40007800 0x400>;
174 clocks = <&rcc 1 CLK_UART7>;
178 usart8: serial@40007c00 {
179 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
180 reg = <0x40007c00 0x400>;
182 clocks = <&rcc 1 CLK_UART8>;
186 usart1: serial@40011000 {
187 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
188 reg = <0x40011000 0x400>;
190 clocks = <&rcc 1 CLK_USART1>;
194 usart6: serial@40011400 {
195 compatible = "st,stm32f7-usart", "st,stm32f7-uart";
196 reg = <0x40011400 0x400>;
198 clocks = <&rcc 1 CLK_USART6>;
202 syscfg: system-config@40013800 {
203 compatible = "syscon";
204 reg = <0x40013800 0x400>;
207 exti: interrupt-controller@40013c00 {
208 compatible = "st,stm32-exti";
209 interrupt-controller;
210 #interrupt-cells = <2>;
211 reg = <0x40013C00 0x400>;
212 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
215 pwrcfg: power-config@40007000 {
216 compatible = "syscon";
217 reg = <0x40007000 0x400>;
221 #address-cells = <1>;
223 compatible = "st,stm32f746-pinctrl";
224 ranges = <0 0x40020000 0x3000>;
225 interrupt-parent = <&exti>;
226 st,syscfg = <&syscfg 0x8>;
229 gpioa: gpio@40020000 {
233 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
234 st,bank-name = "GPIOA";
237 gpiob: gpio@40020400 {
241 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
242 st,bank-name = "GPIOB";
245 gpioc: gpio@40020800 {
249 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
250 st,bank-name = "GPIOC";
253 gpiod: gpio@40020c00 {
257 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
258 st,bank-name = "GPIOD";
261 gpioe: gpio@40021000 {
264 reg = <0x1000 0x400>;
265 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
266 st,bank-name = "GPIOE";
269 gpiof: gpio@40021400 {
272 reg = <0x1400 0x400>;
273 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
274 st,bank-name = "GPIOF";
277 gpiog: gpio@40021800 {
280 reg = <0x1800 0x400>;
281 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
282 st,bank-name = "GPIOG";
285 gpioh: gpio@40021c00 {
288 reg = <0x1c00 0x400>;
289 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
290 st,bank-name = "GPIOH";
293 gpioi: gpio@40022000 {
296 reg = <0x2000 0x400>;
297 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
298 st,bank-name = "GPIOI";
301 gpioj: gpio@40022400 {
304 reg = <0x2400 0x400>;
305 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
306 st,bank-name = "GPIOJ";
309 gpiok: gpio@40022800 {
312 reg = <0x2800 0x400>;
313 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
314 st,bank-name = "GPIOK";
317 usart1_pins_a: usart1@0 {
319 pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
325 pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
332 compatible = "st,stm32f7-crc";
333 reg = <0x40023000 0x400>;
334 clocks = <&rcc 0 12>;
340 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
341 reg = <0x40023800 0x400>;
342 clocks = <&clk_hse>, <&clk_i2s_ckin>;
343 st,syscfg = <&pwrcfg>;
344 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
345 assigned-clock-rates = <1000000>;