arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         aliases {
  19                 ethernet0 = &emac;
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26                 serial6 = &uart6;
  27                 serial7 = &uart7;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a8";
  36                         reg = <0x0>;
  37                 };
  38         };
  39
  40         memory {
  41                 reg = <0x40000000 0x80000000>;
  42         };
  43
  44         clocks {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges;
  48
  49                 /*
  50                  * This is a dummy clock, to be used as placeholder on
  51                  * other mux clocks when a specific parent clock is not
  52                  * yet implemented. It should be dropped when the driver
  53                  * is complete.
  54                  */
  55                 dummy: dummy {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-clock";
  58                         clock-frequency = <0>;
  59                 };
  60
  61                 osc24M: clk@01c20050 {
  62                         #clock-cells = <0>;
  63                         compatible = "allwinner,sun4i-osc-clk";
  64                         reg = <0x01c20050 0x4>;
  65                         clock-frequency = <24000000>;
  66                         clock-output-names = "osc24M";
  67                 };
  68
  69                 osc32k: clk@0 {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <32768>;
  73                         clock-output-names = "osc32k";
  74                 };
  75
  76                 pll1: clk@01c20000 {
  77                         #clock-cells = <0>;
  78                         compatible = "allwinner,sun4i-pll1-clk";
  79                         reg = <0x01c20000 0x4>;
  80                         clocks = <&osc24M>;
  81                         clock-output-names = "pll1";
  82                 };
  83
  84                 pll4: clk@01c20018 {
  85                         #clock-cells = <0>;
  86                         compatible = "allwinner,sun4i-pll1-clk";
  87                         reg = <0x01c20018 0x4>;
  88                         clocks = <&osc24M>;
  89                         clock-output-names = "pll4";
  90                 };
  91
  92                 pll5: clk@01c20020 {
  93                         #clock-cells = <1>;
  94                         compatible = "allwinner,sun4i-pll5-clk";
  95                         reg = <0x01c20020 0x4>;
  96                         clocks = <&osc24M>;
  97                         clock-output-names = "pll5_ddr", "pll5_other";
  98                 };
  99
 100                 pll6: clk@01c20028 {
 101                         #clock-cells = <1>;
 102                         compatible = "allwinner,sun4i-pll6-clk";
 103                         reg = <0x01c20028 0x4>;
 104                         clocks = <&osc24M>;
 105                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 106                 };
 107
 108                 /* dummy is 200M */
 109                 cpu: cpu@01c20054 {
 110                         #clock-cells = <0>;
 111                         compatible = "allwinner,sun4i-cpu-clk";
 112                         reg = <0x01c20054 0x4>;
 113                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 114                         clock-output-names = "cpu";
 115                 };
 116
 117                 axi: axi@01c20054 {
 118                         #clock-cells = <0>;
 119                         compatible = "allwinner,sun4i-axi-clk";
 120                         reg = <0x01c20054 0x4>;
 121                         clocks = <&cpu>;
 122                         clock-output-names = "axi";
 123                 };
 124
 125                 axi_gates: clk@01c2005c {
 126                         #clock-cells = <1>;
 127                         compatible = "allwinner,sun4i-axi-gates-clk";
 128                         reg = <0x01c2005c 0x4>;
 129                         clocks = <&axi>;
 130                         clock-output-names = "axi_dram";
 131                 };
 132
 133                 ahb: ahb@01c20054 {
 134                         #clock-cells = <0>;
 135                         compatible = "allwinner,sun4i-ahb-clk";
 136                         reg = <0x01c20054 0x4>;
 137                         clocks = <&axi>;
 138                         clock-output-names = "ahb";
 139                 };
 140
 141                 ahb_gates: clk@01c20060 {
 142                         #clock-cells = <1>;
 143                         compatible = "allwinner,sun4i-ahb-gates-clk";
 144                         reg = <0x01c20060 0x8>;
 145                         clocks = <&ahb>;
 146                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 147                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 148                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 149                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 150                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 151                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 152                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 153                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 154                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 155                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 156                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 157                 };
 158
 159                 apb0: apb0@01c20054 {
 160                         #clock-cells = <0>;
 161                         compatible = "allwinner,sun4i-apb0-clk";
 162                         reg = <0x01c20054 0x4>;
 163                         clocks = <&ahb>;
 164                         clock-output-names = "apb0";
 165                 };
 166
 167                 apb0_gates: clk@01c20068 {
 168                         #clock-cells = <1>;
 169                         compatible = "allwinner,sun4i-apb0-gates-clk";
 170                         reg = <0x01c20068 0x4>;
 171                         clocks = <&apb0>;
 172                         clock-output-names = "apb0_codec", "apb0_spdif",
 173                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 174                                 "apb0_ir1", "apb0_keypad";
 175                 };
 176
 177                 apb1_mux: apb1_mux@01c20058 {
 178                         #clock-cells = <0>;
 179                         compatible = "allwinner,sun4i-apb1-mux-clk";
 180                         reg = <0x01c20058 0x4>;
 181                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 182                         clock-output-names = "apb1_mux";
 183                 };
 184
 185                 apb1: apb1@01c20058 {
 186                         #clock-cells = <0>;
 187                         compatible = "allwinner,sun4i-apb1-clk";
 188                         reg = <0x01c20058 0x4>;
 189                         clocks = <&apb1_mux>;
 190                         clock-output-names = "apb1";
 191                 };
 192
 193                 apb1_gates: clk@01c2006c {
 194                         #clock-cells = <1>;
 195                         compatible = "allwinner,sun4i-apb1-gates-clk";
 196                         reg = <0x01c2006c 0x4>;
 197                         clocks = <&apb1>;
 198                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 199                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 200                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 201                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 202                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 203                                 "apb1_uart7";
 204                 };
 205
 206                 nand_clk: clk@01c20080 {
 207                         #clock-cells = <0>;
 208                         compatible = "allwinner,sun4i-mod0-clk";
 209                         reg = <0x01c20080 0x4>;
 210                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 211                         clock-output-names = "nand";
 212                 };
 213
 214                 ms_clk: clk@01c20084 {
 215                         #clock-cells = <0>;
 216                         compatible = "allwinner,sun4i-mod0-clk";
 217                         reg = <0x01c20084 0x4>;
 218                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 219                         clock-output-names = "ms";
 220                 };
 221
 222                 mmc0_clk: clk@01c20088 {
 223                         #clock-cells = <0>;
 224                         compatible = "allwinner,sun4i-mod0-clk";
 225                         reg = <0x01c20088 0x4>;
 226                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 227                         clock-output-names = "mmc0";
 228                 };
 229
 230                 mmc1_clk: clk@01c2008c {
 231                         #clock-cells = <0>;
 232                         compatible = "allwinner,sun4i-mod0-clk";
 233                         reg = <0x01c2008c 0x4>;
 234                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 235                         clock-output-names = "mmc1";
 236                 };
 237
 238                 mmc2_clk: clk@01c20090 {
 239                         #clock-cells = <0>;
 240                         compatible = "allwinner,sun4i-mod0-clk";
 241                         reg = <0x01c20090 0x4>;
 242                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 243                         clock-output-names = "mmc2";
 244                 };
 245
 246                 mmc3_clk: clk@01c20094 {
 247                         #clock-cells = <0>;
 248                         compatible = "allwinner,sun4i-mod0-clk";
 249                         reg = <0x01c20094 0x4>;
 250                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 251                         clock-output-names = "mmc3";
 252                 };
 253
 254                 ts_clk: clk@01c20098 {
 255                         #clock-cells = <0>;
 256                         compatible = "allwinner,sun4i-mod0-clk";
 257                         reg = <0x01c20098 0x4>;
 258                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 259                         clock-output-names = "ts";
 260                 };
 261
 262                 ss_clk: clk@01c2009c {
 263                         #clock-cells = <0>;
 264                         compatible = "allwinner,sun4i-mod0-clk";
 265                         reg = <0x01c2009c 0x4>;
 266                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 267                         clock-output-names = "ss";
 268                 };
 269
 270                 spi0_clk: clk@01c200a0 {
 271                         #clock-cells = <0>;
 272                         compatible = "allwinner,sun4i-mod0-clk";
 273                         reg = <0x01c200a0 0x4>;
 274                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 275                         clock-output-names = "spi0";
 276                 };
 277
 278                 spi1_clk: clk@01c200a4 {
 279                         #clock-cells = <0>;
 280                         compatible = "allwinner,sun4i-mod0-clk";
 281                         reg = <0x01c200a4 0x4>;
 282                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 283                         clock-output-names = "spi1";
 284                 };
 285
 286                 spi2_clk: clk@01c200a8 {
 287                         #clock-cells = <0>;
 288                         compatible = "allwinner,sun4i-mod0-clk";
 289                         reg = <0x01c200a8 0x4>;
 290                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 291                         clock-output-names = "spi2";
 292                 };
 293
 294                 pata_clk: clk@01c200ac {
 295                         #clock-cells = <0>;
 296                         compatible = "allwinner,sun4i-mod0-clk";
 297                         reg = <0x01c200ac 0x4>;
 298                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 299                         clock-output-names = "pata";
 300                 };
 301
 302                 ir0_clk: clk@01c200b0 {
 303                         #clock-cells = <0>;
 304                         compatible = "allwinner,sun4i-mod0-clk";
 305                         reg = <0x01c200b0 0x4>;
 306                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 307                         clock-output-names = "ir0";
 308                 };
 309
 310                 ir1_clk: clk@01c200b4 {
 311                         #clock-cells = <0>;
 312                         compatible = "allwinner,sun4i-mod0-clk";
 313                         reg = <0x01c200b4 0x4>;
 314                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 315                         clock-output-names = "ir1";
 316                 };
 317
 318                 spi3_clk: clk@01c200d4 {
 319                         #clock-cells = <0>;
 320                         compatible = "allwinner,sun4i-mod0-clk";
 321                         reg = <0x01c200d4 0x4>;
 322                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 323                         clock-output-names = "spi3";
 324                 };
 325         };
 326
 327         soc@01c00000 {
 328                 compatible = "simple-bus";
 329                 #address-cells = <1>;
 330                 #size-cells = <1>;
 331                 ranges;
 332
 333                 emac: ethernet@01c0b000 {
 334                         compatible = "allwinner,sun4i-emac";
 335                         reg = <0x01c0b000 0x1000>;
 336                         interrupts = <55>;
 337                         clocks = <&ahb_gates 17>;
 338                         status = "disabled";
 339                 };
 340
 341                 mdio@01c0b080 {
 342                         compatible = "allwinner,sun4i-mdio";
 343                         reg = <0x01c0b080 0x14>;
 344                         status = "disabled";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                 };
 348
 349                 intc: interrupt-controller@01c20400 {
 350                         compatible = "allwinner,sun4i-ic";
 351                         reg = <0x01c20400 0x400>;
 352                         interrupt-controller;
 353                         #interrupt-cells = <1>;
 354                 };
 355
 356                 pio: pinctrl@01c20800 {
 357                         compatible = "allwinner,sun4i-a10-pinctrl";
 358                         reg = <0x01c20800 0x400>;
 359                         interrupts = <28>;
 360                         clocks = <&apb0_gates 5>;
 361                         gpio-controller;
 362                         interrupt-controller;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         #gpio-cells = <3>;
 366
 367                         uart0_pins_a: uart0@0 {
 368                                 allwinner,pins = "PB22", "PB23";
 369                                 allwinner,function = "uart0";
 370                                 allwinner,drive = <0>;
 371                                 allwinner,pull = <0>;
 372                         };
 373
 374                         uart0_pins_b: uart0@1 {
 375                                 allwinner,pins = "PF2", "PF4";
 376                                 allwinner,function = "uart0";
 377                                 allwinner,drive = <0>;
 378                                 allwinner,pull = <0>;
 379                         };
 380
 381                         uart1_pins_a: uart1@0 {
 382                                 allwinner,pins = "PA10", "PA11";
 383                                 allwinner,function = "uart1";
 384                                 allwinner,drive = <0>;
 385                                 allwinner,pull = <0>;
 386                         };
 387
 388                         i2c0_pins_a: i2c0@0 {
 389                                 allwinner,pins = "PB0", "PB1";
 390                                 allwinner,function = "i2c0";
 391                                 allwinner,drive = <0>;
 392                                 allwinner,pull = <0>;
 393                         };
 394
 395                         i2c1_pins_a: i2c1@0 {
 396                                 allwinner,pins = "PB18", "PB19";
 397                                 allwinner,function = "i2c1";
 398                                 allwinner,drive = <0>;
 399                                 allwinner,pull = <0>;
 400                         };
 401
 402                         i2c2_pins_a: i2c2@0 {
 403                                 allwinner,pins = "PB20", "PB21";
 404                                 allwinner,function = "i2c2";
 405                                 allwinner,drive = <0>;
 406                                 allwinner,pull = <0>;
 407                         };
 408
 409                         emac_pins_a: emac0@0 {
 410                                 allwinner,pins = "PA0", "PA1", "PA2",
 411                                                 "PA3", "PA4", "PA5", "PA6",
 412                                                 "PA7", "PA8", "PA9", "PA10",
 413                                                 "PA11", "PA12", "PA13", "PA14",
 414                                                 "PA15", "PA16";
 415                                 allwinner,function = "emac";
 416                                 allwinner,drive = <0>;
 417                                 allwinner,pull = <0>;
 418                         };
 419                 };
 420
 421                 timer@01c20c00 {
 422                         compatible = "allwinner,sun4i-timer";
 423                         reg = <0x01c20c00 0x90>;
 424                         interrupts = <22>;
 425                         clocks = <&osc24M>;
 426                 };
 427
 428                 wdt: watchdog@01c20c90 {
 429                         compatible = "allwinner,sun4i-wdt";
 430                         reg = <0x01c20c90 0x10>;
 431                 };
 432
 433                 rtc: rtc@01c20d00 {
 434                         compatible = "allwinner,sun4i-rtc";
 435                         reg = <0x01c20d00 0x20>;
 436                         interrupts = <24>;
 437                 };
 438
 439                 sid: eeprom@01c23800 {
 440                         compatible = "allwinner,sun4i-sid";
 441                         reg = <0x01c23800 0x10>;
 442                 };
 443
 444                 rtp: rtp@01c25000 {
 445                         compatible = "allwinner,sun4i-ts";
 446                         reg = <0x01c25000 0x100>;
 447                         interrupts = <29>;
 448                 };
 449
 450                 uart0: serial@01c28000 {
 451                         compatible = "snps,dw-apb-uart";
 452                         reg = <0x01c28000 0x400>;
 453                         interrupts = <1>;
 454                         reg-shift = <2>;
 455                         reg-io-width = <4>;
 456                         clocks = <&apb1_gates 16>;
 457                         status = "disabled";
 458                 };
 459
 460                 uart1: serial@01c28400 {
 461                         compatible = "snps,dw-apb-uart";
 462                         reg = <0x01c28400 0x400>;
 463                         interrupts = <2>;
 464                         reg-shift = <2>;
 465                         reg-io-width = <4>;
 466                         clocks = <&apb1_gates 17>;
 467                         status = "disabled";
 468                 };
 469
 470                 uart2: serial@01c28800 {
 471                         compatible = "snps,dw-apb-uart";
 472                         reg = <0x01c28800 0x400>;
 473                         interrupts = <3>;
 474                         reg-shift = <2>;
 475                         reg-io-width = <4>;
 476                         clocks = <&apb1_gates 18>;
 477                         status = "disabled";
 478                 };
 479
 480                 uart3: serial@01c28c00 {
 481                         compatible = "snps,dw-apb-uart";
 482                         reg = <0x01c28c00 0x400>;
 483                         interrupts = <4>;
 484                         reg-shift = <2>;
 485                         reg-io-width = <4>;
 486                         clocks = <&apb1_gates 19>;
 487                         status = "disabled";
 488                 };
 489
 490                 uart4: serial@01c29000 {
 491                         compatible = "snps,dw-apb-uart";
 492                         reg = <0x01c29000 0x400>;
 493                         interrupts = <17>;
 494                         reg-shift = <2>;
 495                         reg-io-width = <4>;
 496                         clocks = <&apb1_gates 20>;
 497                         status = "disabled";
 498                 };
 499
 500                 uart5: serial@01c29400 {
 501                         compatible = "snps,dw-apb-uart";
 502                         reg = <0x01c29400 0x400>;
 503                         interrupts = <18>;
 504                         reg-shift = <2>;
 505                         reg-io-width = <4>;
 506                         clocks = <&apb1_gates 21>;
 507                         status = "disabled";
 508                 };
 509
 510                 uart6: serial@01c29800 {
 511                         compatible = "snps,dw-apb-uart";
 512                         reg = <0x01c29800 0x400>;
 513                         interrupts = <19>;
 514                         reg-shift = <2>;
 515                         reg-io-width = <4>;
 516                         clocks = <&apb1_gates 22>;
 517                         status = "disabled";
 518                 };
 519
 520                 uart7: serial@01c29c00 {
 521                         compatible = "snps,dw-apb-uart";
 522                         reg = <0x01c29c00 0x400>;
 523                         interrupts = <20>;
 524                         reg-shift = <2>;
 525                         reg-io-width = <4>;
 526                         clocks = <&apb1_gates 23>;
 527                         status = "disabled";
 528                 };
 529
 530                 i2c0: i2c@01c2ac00 {
 531                         compatible = "allwinner,sun4i-i2c";
 532                         reg = <0x01c2ac00 0x400>;
 533                         interrupts = <7>;
 534                         clocks = <&apb1_gates 0>;
 535                         clock-frequency = <100000>;
 536                         status = "disabled";
 537                 };
 538
 539                 i2c1: i2c@01c2b000 {
 540                         compatible = "allwinner,sun4i-i2c";
 541                         reg = <0x01c2b000 0x400>;
 542                         interrupts = <8>;
 543                         clocks = <&apb1_gates 1>;
 544                         clock-frequency = <100000>;
 545                         status = "disabled";
 546                 };
 547
 548                 i2c2: i2c@01c2b400 {
 549                         compatible = "allwinner,sun4i-i2c";
 550                         reg = <0x01c2b400 0x400>;
 551                         interrupts = <9>;
 552                         clocks = <&apb1_gates 2>;
 553                         clock-frequency = <100000>;
 554                         status = "disabled";
 555                 };
 556         };
 557 };