arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         aliases {
  19                 ethernet0 = &emac;
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26                 serial6 = &uart6;
  27                 serial7 = &uart7;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a8";
  36                         reg = <0x0>;
  37                 };
  38         };
  39
  40         memory {
  41                 reg = <0x40000000 0x80000000>;
  42         };
  43
  44         clocks {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges;
  48
  49                 /*
  50                  * This is a dummy clock, to be used as placeholder on
  51                  * other mux clocks when a specific parent clock is not
  52                  * yet implemented. It should be dropped when the driver
  53                  * is complete.
  54                  */
  55                 dummy: dummy {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-clock";
  58                         clock-frequency = <0>;
  59                 };
  60
  61                 osc24M: osc24M@01c20050 {
  62                         #clock-cells = <0>;
  63                         compatible = "allwinner,sun4i-osc-clk";
  64                         reg = <0x01c20050 0x4>;
  65                         clock-frequency = <24000000>;
  66                 };
  67
  68                 osc32k: osc32k {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                 };
  73
  74                 pll1: pll1@01c20000 {
  75                         #clock-cells = <0>;
  76                         compatible = "allwinner,sun4i-pll1-clk";
  77                         reg = <0x01c20000 0x4>;
  78                         clocks = <&osc24M>;
  79                 };
  80
  81                 pll4: pll4@01c20018 {
  82                         #clock-cells = <0>;
  83                         compatible = "allwinner,sun4i-pll1-clk";
  84                         reg = <0x01c20018 0x4>;
  85                         clocks = <&osc24M>;
  86                 };
  87
  88                 pll5: pll5@01c20020 {
  89                         #clock-cells = <1>;
  90                         compatible = "allwinner,sun4i-pll5-clk";
  91                         reg = <0x01c20020 0x4>;
  92                         clocks = <&osc24M>;
  93                         clock-output-names = "pll5_ddr", "pll5_other";
  94                 };
  95
  96                 pll6: pll6@01c20028 {
  97                         #clock-cells = <1>;
  98                         compatible = "allwinner,sun4i-pll6-clk";
  99                         reg = <0x01c20028 0x4>;
 100                         clocks = <&osc24M>;
 101                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 102                 };
 103
 104                 /* dummy is 200M */
 105                 cpu: cpu@01c20054 {
 106                         #clock-cells = <0>;
 107                         compatible = "allwinner,sun4i-cpu-clk";
 108                         reg = <0x01c20054 0x4>;
 109                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 110                 };
 111
 112                 axi: axi@01c20054 {
 113                         #clock-cells = <0>;
 114                         compatible = "allwinner,sun4i-axi-clk";
 115                         reg = <0x01c20054 0x4>;
 116                         clocks = <&cpu>;
 117                 };
 118
 119                 axi_gates: axi_gates@01c2005c {
 120                         #clock-cells = <1>;
 121                         compatible = "allwinner,sun4i-axi-gates-clk";
 122                         reg = <0x01c2005c 0x4>;
 123                         clocks = <&axi>;
 124                         clock-output-names = "axi_dram";
 125                 };
 126
 127                 ahb: ahb@01c20054 {
 128                         #clock-cells = <0>;
 129                         compatible = "allwinner,sun4i-ahb-clk";
 130                         reg = <0x01c20054 0x4>;
 131                         clocks = <&axi>;
 132                 };
 133
 134                 ahb_gates: ahb_gates@01c20060 {
 135                         #clock-cells = <1>;
 136                         compatible = "allwinner,sun4i-ahb-gates-clk";
 137                         reg = <0x01c20060 0x8>;
 138                         clocks = <&ahb>;
 139                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 140                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 141                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 142                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 143                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 144                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 145                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 146                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 147                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 148                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 149                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 150                 };
 151
 152                 apb0: apb0@01c20054 {
 153                         #clock-cells = <0>;
 154                         compatible = "allwinner,sun4i-apb0-clk";
 155                         reg = <0x01c20054 0x4>;
 156                         clocks = <&ahb>;
 157                 };
 158
 159                 apb0_gates: apb0_gates@01c20068 {
 160                         #clock-cells = <1>;
 161                         compatible = "allwinner,sun4i-apb0-gates-clk";
 162                         reg = <0x01c20068 0x4>;
 163                         clocks = <&apb0>;
 164                         clock-output-names = "apb0_codec", "apb0_spdif",
 165                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 166                                 "apb0_ir1", "apb0_keypad";
 167                 };
 168
 169                 apb1_mux: apb1_mux@01c20058 {
 170                         #clock-cells = <0>;
 171                         compatible = "allwinner,sun4i-apb1-mux-clk";
 172                         reg = <0x01c20058 0x4>;
 173                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 174                 };
 175
 176                 apb1: apb1@01c20058 {
 177                         #clock-cells = <0>;
 178                         compatible = "allwinner,sun4i-apb1-clk";
 179                         reg = <0x01c20058 0x4>;
 180                         clocks = <&apb1_mux>;
 181                 };
 182
 183                 apb1_gates: apb1_gates@01c2006c {
 184                         #clock-cells = <1>;
 185                         compatible = "allwinner,sun4i-apb1-gates-clk";
 186                         reg = <0x01c2006c 0x4>;
 187                         clocks = <&apb1>;
 188                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 189                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 190                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 191                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 192                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 193                                 "apb1_uart7";
 194                 };
 195
 196                 nand_clk: clk@01c20080 {
 197                         #clock-cells = <0>;
 198                         compatible = "allwinner,sun4i-mod0-clk";
 199                         reg = <0x01c20080 0x4>;
 200                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 201                         clock-output-names = "nand";
 202                 };
 203
 204                 ms_clk: clk@01c20084 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun4i-mod0-clk";
 207                         reg = <0x01c20084 0x4>;
 208                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 209                         clock-output-names = "ms";
 210                 };
 211
 212                 mmc0_clk: clk@01c20088 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-mod0-clk";
 215                         reg = <0x01c20088 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "mmc0";
 218                 };
 219
 220                 mmc1_clk: clk@01c2008c {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-mod0-clk";
 223                         reg = <0x01c2008c 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "mmc1";
 226                 };
 227
 228                 mmc2_clk: clk@01c20090 {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun4i-mod0-clk";
 231                         reg = <0x01c20090 0x4>;
 232                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 233                         clock-output-names = "mmc2";
 234                 };
 235
 236                 mmc3_clk: clk@01c20094 {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-mod0-clk";
 239                         reg = <0x01c20094 0x4>;
 240                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 241                         clock-output-names = "mmc3";
 242                 };
 243
 244                 ts_clk: clk@01c20098 {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun4i-mod0-clk";
 247                         reg = <0x01c20098 0x4>;
 248                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 249                         clock-output-names = "ts";
 250                 };
 251
 252                 ss_clk: clk@01c2009c {
 253                         #clock-cells = <0>;
 254                         compatible = "allwinner,sun4i-mod0-clk";
 255                         reg = <0x01c2009c 0x4>;
 256                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 257                         clock-output-names = "ss";
 258                 };
 259
 260                 spi0_clk: clk@01c200a0 {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun4i-mod0-clk";
 263                         reg = <0x01c200a0 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 265                         clock-output-names = "spi0";
 266                 };
 267
 268                 spi1_clk: clk@01c200a4 {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-mod0-clk";
 271                         reg = <0x01c200a4 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "spi1";
 274                 };
 275
 276                 spi2_clk: clk@01c200a8 {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-mod0-clk";
 279                         reg = <0x01c200a8 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "spi2";
 282                 };
 283
 284                 pata_clk: clk@01c200ac {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-mod0-clk";
 287                         reg = <0x01c200ac 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "pata";
 290                 };
 291
 292                 ir0_clk: clk@01c200b0 {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-mod0-clk";
 295                         reg = <0x01c200b0 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "ir0";
 298                 };
 299
 300                 ir1_clk: clk@01c200b4 {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-mod0-clk";
 303                         reg = <0x01c200b4 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "ir1";
 306                 };
 307
 308                 spi3_clk: clk@01c200d4 {
 309                         #clock-cells = <0>;
 310                         compatible = "allwinner,sun4i-mod0-clk";
 311                         reg = <0x01c200d4 0x4>;
 312                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 313                         clock-output-names = "spi3";
 314                 };
 315         };
 316
 317         soc@01c00000 {
 318                 compatible = "simple-bus";
 319                 #address-cells = <1>;
 320                 #size-cells = <1>;
 321                 ranges;
 322
 323                 emac: ethernet@01c0b000 {
 324                         compatible = "allwinner,sun4i-emac";
 325                         reg = <0x01c0b000 0x1000>;
 326                         interrupts = <55>;
 327                         clocks = <&ahb_gates 17>;
 328                         status = "disabled";
 329                 };
 330
 331                 mdio@01c0b080 {
 332                         compatible = "allwinner,sun4i-mdio";
 333                         reg = <0x01c0b080 0x14>;
 334                         status = "disabled";
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                 };
 338
 339                 intc: interrupt-controller@01c20400 {
 340                         compatible = "allwinner,sun4i-ic";
 341                         reg = <0x01c20400 0x400>;
 342                         interrupt-controller;
 343                         #interrupt-cells = <1>;
 344                 };
 345
 346                 pio: pinctrl@01c20800 {
 347                         compatible = "allwinner,sun4i-a10-pinctrl";
 348                         reg = <0x01c20800 0x400>;
 349                         interrupts = <28>;
 350                         clocks = <&apb0_gates 5>;
 351                         gpio-controller;
 352                         interrupt-controller;
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         #gpio-cells = <3>;
 356
 357                         uart0_pins_a: uart0@0 {
 358                                 allwinner,pins = "PB22", "PB23";
 359                                 allwinner,function = "uart0";
 360                                 allwinner,drive = <0>;
 361                                 allwinner,pull = <0>;
 362                         };
 363
 364                         uart0_pins_b: uart0@1 {
 365                                 allwinner,pins = "PF2", "PF4";
 366                                 allwinner,function = "uart0";
 367                                 allwinner,drive = <0>;
 368                                 allwinner,pull = <0>;
 369                         };
 370
 371                         uart1_pins_a: uart1@0 {
 372                                 allwinner,pins = "PA10", "PA11";
 373                                 allwinner,function = "uart1";
 374                                 allwinner,drive = <0>;
 375                                 allwinner,pull = <0>;
 376                         };
 377
 378                         i2c0_pins_a: i2c0@0 {
 379                                 allwinner,pins = "PB0", "PB1";
 380                                 allwinner,function = "i2c0";
 381                                 allwinner,drive = <0>;
 382                                 allwinner,pull = <0>;
 383                         };
 384
 385                         i2c1_pins_a: i2c1@0 {
 386                                 allwinner,pins = "PB18", "PB19";
 387                                 allwinner,function = "i2c1";
 388                                 allwinner,drive = <0>;
 389                                 allwinner,pull = <0>;
 390                         };
 391
 392                         i2c2_pins_a: i2c2@0 {
 393                                 allwinner,pins = "PB20", "PB21";
 394                                 allwinner,function = "i2c2";
 395                                 allwinner,drive = <0>;
 396                                 allwinner,pull = <0>;
 397                         };
 398
 399                         emac_pins_a: emac0@0 {
 400                                 allwinner,pins = "PA0", "PA1", "PA2",
 401                                                 "PA3", "PA4", "PA5", "PA6",
 402                                                 "PA7", "PA8", "PA9", "PA10",
 403                                                 "PA11", "PA12", "PA13", "PA14",
 404                                                 "PA15", "PA16";
 405                                 allwinner,function = "emac";
 406                                 allwinner,drive = <0>;
 407                                 allwinner,pull = <0>;
 408                         };
 409                 };
 410
 411                 timer@01c20c00 {
 412                         compatible = "allwinner,sun4i-timer";
 413                         reg = <0x01c20c00 0x90>;
 414                         interrupts = <22>;
 415                         clocks = <&osc24M>;
 416                 };
 417
 418                 wdt: watchdog@01c20c90 {
 419                         compatible = "allwinner,sun4i-wdt";
 420                         reg = <0x01c20c90 0x10>;
 421                 };
 422
 423                 rtc: rtc@01c20d00 {
 424                         compatible = "allwinner,sun4i-rtc";
 425                         reg = <0x01c20d00 0x20>;
 426                         interrupts = <24>;
 427                 };
 428
 429                 sid: eeprom@01c23800 {
 430                         compatible = "allwinner,sun4i-sid";
 431                         reg = <0x01c23800 0x10>;
 432                 };
 433
 434                 rtp: rtp@01c25000 {
 435                         compatible = "allwinner,sun4i-ts";
 436                         reg = <0x01c25000 0x100>;
 437                         interrupts = <29>;
 438                 };
 439
 440                 uart0: serial@01c28000 {
 441                         compatible = "snps,dw-apb-uart";
 442                         reg = <0x01c28000 0x400>;
 443                         interrupts = <1>;
 444                         reg-shift = <2>;
 445                         reg-io-width = <4>;
 446                         clocks = <&apb1_gates 16>;
 447                         status = "disabled";
 448                 };
 449
 450                 uart1: serial@01c28400 {
 451                         compatible = "snps,dw-apb-uart";
 452                         reg = <0x01c28400 0x400>;
 453                         interrupts = <2>;
 454                         reg-shift = <2>;
 455                         reg-io-width = <4>;
 456                         clocks = <&apb1_gates 17>;
 457                         status = "disabled";
 458                 };
 459
 460                 uart2: serial@01c28800 {
 461                         compatible = "snps,dw-apb-uart";
 462                         reg = <0x01c28800 0x400>;
 463                         interrupts = <3>;
 464                         reg-shift = <2>;
 465                         reg-io-width = <4>;
 466                         clocks = <&apb1_gates 18>;
 467                         status = "disabled";
 468                 };
 469
 470                 uart3: serial@01c28c00 {
 471                         compatible = "snps,dw-apb-uart";
 472                         reg = <0x01c28c00 0x400>;
 473                         interrupts = <4>;
 474                         reg-shift = <2>;
 475                         reg-io-width = <4>;
 476                         clocks = <&apb1_gates 19>;
 477                         status = "disabled";
 478                 };
 479
 480                 uart4: serial@01c29000 {
 481                         compatible = "snps,dw-apb-uart";
 482                         reg = <0x01c29000 0x400>;
 483                         interrupts = <17>;
 484                         reg-shift = <2>;
 485                         reg-io-width = <4>;
 486                         clocks = <&apb1_gates 20>;
 487                         status = "disabled";
 488                 };
 489
 490                 uart5: serial@01c29400 {
 491                         compatible = "snps,dw-apb-uart";
 492                         reg = <0x01c29400 0x400>;
 493                         interrupts = <18>;
 494                         reg-shift = <2>;
 495                         reg-io-width = <4>;
 496                         clocks = <&apb1_gates 21>;
 497                         status = "disabled";
 498                 };
 499
 500                 uart6: serial@01c29800 {
 501                         compatible = "snps,dw-apb-uart";
 502                         reg = <0x01c29800 0x400>;
 503                         interrupts = <19>;
 504                         reg-shift = <2>;
 505                         reg-io-width = <4>;
 506                         clocks = <&apb1_gates 22>;
 507                         status = "disabled";
 508                 };
 509
 510                 uart7: serial@01c29c00 {
 511                         compatible = "snps,dw-apb-uart";
 512                         reg = <0x01c29c00 0x400>;
 513                         interrupts = <20>;
 514                         reg-shift = <2>;
 515                         reg-io-width = <4>;
 516                         clocks = <&apb1_gates 23>;
 517                         status = "disabled";
 518                 };
 519
 520                 i2c0: i2c@01c2ac00 {
 521                         compatible = "allwinner,sun4i-i2c";
 522                         reg = <0x01c2ac00 0x400>;
 523                         interrupts = <7>;
 524                         clocks = <&apb1_gates 0>;
 525                         clock-frequency = <100000>;
 526                         status = "disabled";
 527                 };
 528
 529                 i2c1: i2c@01c2b000 {
 530                         compatible = "allwinner,sun4i-i2c";
 531                         reg = <0x01c2b000 0x400>;
 532                         interrupts = <8>;
 533                         clocks = <&apb1_gates 1>;
 534                         clock-frequency = <100000>;
 535                         status = "disabled";
 536                 };
 537
 538                 i2c2: i2c@01c2b400 {
 539                         compatible = "allwinner,sun4i-i2c";
 540                         reg = <0x01c2b400 0x400>;
 541                         interrupts = <9>;
 542                         clocks = <&apb1_gates 2>;
 543                         clock-frequency = <100000>;
 544                         status = "disabled";
 545                 };
 546         };
 547 };