2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
16 interrupt-parent = <&intc>;
36 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
37 allwinner,pipeline = "de_be0-lcd0-hdmi";
38 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
49 compatible = "arm,cortex-a8";
55 reg = <0x40000000 0x80000000>;
64 * This is a dummy clock, to be used as placeholder on
65 * other mux clocks when a specific parent clock is not
66 * yet implemented. It should be dropped when the driver
71 compatible = "fixed-clock";
72 clock-frequency = <0>;
75 osc24M: clk@01c20050 {
77 compatible = "allwinner,sun4i-a10-osc-clk";
78 reg = <0x01c20050 0x4>;
79 clock-frequency = <24000000>;
80 clock-output-names = "osc24M";
85 compatible = "fixed-clock";
86 clock-frequency = <32768>;
87 clock-output-names = "osc32k";
92 compatible = "allwinner,sun4i-a10-pll1-clk";
93 reg = <0x01c20000 0x4>;
95 clock-output-names = "pll1";
100 compatible = "allwinner,sun4i-a10-pll1-clk";
101 reg = <0x01c20018 0x4>;
103 clock-output-names = "pll4";
108 compatible = "allwinner,sun4i-a10-pll5-clk";
109 reg = <0x01c20020 0x4>;
111 clock-output-names = "pll5_ddr", "pll5_other";
116 compatible = "allwinner,sun4i-a10-pll6-clk";
117 reg = <0x01c20028 0x4>;
119 clock-output-names = "pll6_sata", "pll6_other", "pll6";
125 compatible = "allwinner,sun4i-a10-cpu-clk";
126 reg = <0x01c20054 0x4>;
127 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
128 clock-output-names = "cpu";
133 compatible = "allwinner,sun4i-a10-axi-clk";
134 reg = <0x01c20054 0x4>;
136 clock-output-names = "axi";
139 axi_gates: clk@01c2005c {
141 compatible = "allwinner,sun4i-a10-axi-gates-clk";
142 reg = <0x01c2005c 0x4>;
144 clock-output-names = "axi_dram";
149 compatible = "allwinner,sun4i-a10-ahb-clk";
150 reg = <0x01c20054 0x4>;
152 clock-output-names = "ahb";
155 ahb_gates: clk@01c20060 {
157 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
158 reg = <0x01c20060 0x8>;
160 clock-output-names = "ahb_usb0", "ahb_ehci0",
161 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
162 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
163 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
164 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
165 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
166 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
167 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
168 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
169 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
170 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
173 apb0: apb0@01c20054 {
175 compatible = "allwinner,sun4i-a10-apb0-clk";
176 reg = <0x01c20054 0x4>;
178 clock-output-names = "apb0";
181 apb0_gates: clk@01c20068 {
183 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
184 reg = <0x01c20068 0x4>;
186 clock-output-names = "apb0_codec", "apb0_spdif",
187 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
188 "apb0_ir1", "apb0_keypad";
193 compatible = "allwinner,sun4i-a10-apb1-clk";
194 reg = <0x01c20058 0x4>;
195 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
196 clock-output-names = "apb1";
199 apb1_gates: clk@01c2006c {
201 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
202 reg = <0x01c2006c 0x4>;
204 clock-output-names = "apb1_i2c0", "apb1_i2c1",
205 "apb1_i2c2", "apb1_can", "apb1_scr",
206 "apb1_ps20", "apb1_ps21", "apb1_uart0",
207 "apb1_uart1", "apb1_uart2", "apb1_uart3",
208 "apb1_uart4", "apb1_uart5", "apb1_uart6",
212 nand_clk: clk@01c20080 {
214 compatible = "allwinner,sun4i-a10-mod0-clk";
215 reg = <0x01c20080 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "nand";
220 ms_clk: clk@01c20084 {
222 compatible = "allwinner,sun4i-a10-mod0-clk";
223 reg = <0x01c20084 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "ms";
228 mmc0_clk: clk@01c20088 {
230 compatible = "allwinner,sun4i-a10-mod0-clk";
231 reg = <0x01c20088 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc0";
236 mmc1_clk: clk@01c2008c {
238 compatible = "allwinner,sun4i-a10-mod0-clk";
239 reg = <0x01c2008c 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc1";
244 mmc2_clk: clk@01c20090 {
246 compatible = "allwinner,sun4i-a10-mod0-clk";
247 reg = <0x01c20090 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "mmc2";
252 mmc3_clk: clk@01c20094 {
254 compatible = "allwinner,sun4i-a10-mod0-clk";
255 reg = <0x01c20094 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "mmc3";
260 ts_clk: clk@01c20098 {
262 compatible = "allwinner,sun4i-a10-mod0-clk";
263 reg = <0x01c20098 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "ts";
268 ss_clk: clk@01c2009c {
270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c2009c 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "ss";
276 spi0_clk: clk@01c200a0 {
278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c200a0 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "spi0";
284 spi1_clk: clk@01c200a4 {
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c200a4 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "spi1";
292 spi2_clk: clk@01c200a8 {
294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c200a8 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "spi2";
300 pata_clk: clk@01c200ac {
302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c200ac 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "pata";
308 ir0_clk: clk@01c200b0 {
310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c200b0 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "ir0";
316 ir1_clk: clk@01c200b4 {
318 compatible = "allwinner,sun4i-a10-mod0-clk";
319 reg = <0x01c200b4 0x4>;
320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321 clock-output-names = "ir1";
324 usb_clk: clk@01c200cc {
327 compatible = "allwinner,sun4i-a10-usb-clk";
328 reg = <0x01c200cc 0x4>;
330 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
333 spi3_clk: clk@01c200d4 {
335 compatible = "allwinner,sun4i-a10-mod0-clk";
336 reg = <0x01c200d4 0x4>;
337 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
338 clock-output-names = "spi3";
343 compatible = "simple-bus";
344 #address-cells = <1>;
348 dma: dma-controller@01c02000 {
349 compatible = "allwinner,sun4i-a10-dma";
350 reg = <0x01c02000 0x1000>;
352 clocks = <&ahb_gates 6>;
357 compatible = "allwinner,sun4i-a10-spi";
358 reg = <0x01c05000 0x1000>;
360 clocks = <&ahb_gates 20>, <&spi0_clk>;
361 clock-names = "ahb", "mod";
362 dmas = <&dma 1 27>, <&dma 1 26>;
363 dma-names = "rx", "tx";
365 #address-cells = <1>;
370 compatible = "allwinner,sun4i-a10-spi";
371 reg = <0x01c06000 0x1000>;
373 clocks = <&ahb_gates 21>, <&spi1_clk>;
374 clock-names = "ahb", "mod";
375 dmas = <&dma 1 9>, <&dma 1 8>;
376 dma-names = "rx", "tx";
378 #address-cells = <1>;
382 emac: ethernet@01c0b000 {
383 compatible = "allwinner,sun4i-a10-emac";
384 reg = <0x01c0b000 0x1000>;
386 clocks = <&ahb_gates 17>;
391 compatible = "allwinner,sun4i-a10-mdio";
392 reg = <0x01c0b080 0x14>;
394 #address-cells = <1>;
399 compatible = "allwinner,sun4i-a10-mmc";
400 reg = <0x01c0f000 0x1000>;
401 clocks = <&ahb_gates 8>, <&mmc0_clk>;
402 clock-names = "ahb", "mmc";
408 compatible = "allwinner,sun4i-a10-mmc";
409 reg = <0x01c10000 0x1000>;
410 clocks = <&ahb_gates 9>, <&mmc1_clk>;
411 clock-names = "ahb", "mmc";
417 compatible = "allwinner,sun4i-a10-mmc";
418 reg = <0x01c11000 0x1000>;
419 clocks = <&ahb_gates 10>, <&mmc2_clk>;
420 clock-names = "ahb", "mmc";
426 compatible = "allwinner,sun4i-a10-mmc";
427 reg = <0x01c12000 0x1000>;
428 clocks = <&ahb_gates 11>, <&mmc3_clk>;
429 clock-names = "ahb", "mmc";
434 usbphy: phy@01c13400 {
436 compatible = "allwinner,sun4i-a10-usb-phy";
437 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
438 reg-names = "phy_ctrl", "pmu1", "pmu2";
439 clocks = <&usb_clk 8>;
440 clock-names = "usb_phy";
441 resets = <&usb_clk 1>, <&usb_clk 2>;
442 reset-names = "usb1_reset", "usb2_reset";
446 ehci0: usb@01c14000 {
447 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
448 reg = <0x01c14000 0x100>;
450 clocks = <&ahb_gates 1>;
456 ohci0: usb@01c14400 {
457 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
458 reg = <0x01c14400 0x100>;
460 clocks = <&usb_clk 6>, <&ahb_gates 2>;
467 compatible = "allwinner,sun4i-a10-spi";
468 reg = <0x01c17000 0x1000>;
470 clocks = <&ahb_gates 22>, <&spi2_clk>;
471 clock-names = "ahb", "mod";
472 dmas = <&dma 1 29>, <&dma 1 28>;
473 dma-names = "rx", "tx";
475 #address-cells = <1>;
479 ahci: sata@01c18000 {
480 compatible = "allwinner,sun4i-a10-ahci";
481 reg = <0x01c18000 0x1000>;
483 clocks = <&pll6 0>, <&ahb_gates 25>;
487 ehci1: usb@01c1c000 {
488 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
489 reg = <0x01c1c000 0x100>;
491 clocks = <&ahb_gates 3>;
497 ohci1: usb@01c1c400 {
498 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
499 reg = <0x01c1c400 0x100>;
501 clocks = <&usb_clk 7>, <&ahb_gates 4>;
508 compatible = "allwinner,sun4i-a10-spi";
509 reg = <0x01c1f000 0x1000>;
511 clocks = <&ahb_gates 23>, <&spi3_clk>;
512 clock-names = "ahb", "mod";
513 dmas = <&dma 1 31>, <&dma 1 30>;
514 dma-names = "rx", "tx";
516 #address-cells = <1>;
520 intc: interrupt-controller@01c20400 {
521 compatible = "allwinner,sun4i-a10-ic";
522 reg = <0x01c20400 0x400>;
523 interrupt-controller;
524 #interrupt-cells = <1>;
527 pio: pinctrl@01c20800 {
528 compatible = "allwinner,sun4i-a10-pinctrl";
529 reg = <0x01c20800 0x400>;
531 clocks = <&apb0_gates 5>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
538 pwm0_pins_a: pwm0@0 {
539 allwinner,pins = "PB2";
540 allwinner,function = "pwm";
541 allwinner,drive = <0>;
542 allwinner,pull = <0>;
545 pwm1_pins_a: pwm1@0 {
546 allwinner,pins = "PI3";
547 allwinner,function = "pwm";
548 allwinner,drive = <0>;
549 allwinner,pull = <0>;
552 uart0_pins_a: uart0@0 {
553 allwinner,pins = "PB22", "PB23";
554 allwinner,function = "uart0";
555 allwinner,drive = <0>;
556 allwinner,pull = <0>;
559 uart0_pins_b: uart0@1 {
560 allwinner,pins = "PF2", "PF4";
561 allwinner,function = "uart0";
562 allwinner,drive = <0>;
563 allwinner,pull = <0>;
566 uart1_pins_a: uart1@0 {
567 allwinner,pins = "PA10", "PA11";
568 allwinner,function = "uart1";
569 allwinner,drive = <0>;
570 allwinner,pull = <0>;
573 i2c0_pins_a: i2c0@0 {
574 allwinner,pins = "PB0", "PB1";
575 allwinner,function = "i2c0";
576 allwinner,drive = <0>;
577 allwinner,pull = <0>;
580 i2c1_pins_a: i2c1@0 {
581 allwinner,pins = "PB18", "PB19";
582 allwinner,function = "i2c1";
583 allwinner,drive = <0>;
584 allwinner,pull = <0>;
587 i2c2_pins_a: i2c2@0 {
588 allwinner,pins = "PB20", "PB21";
589 allwinner,function = "i2c2";
590 allwinner,drive = <0>;
591 allwinner,pull = <0>;
594 emac_pins_a: emac0@0 {
595 allwinner,pins = "PA0", "PA1", "PA2",
596 "PA3", "PA4", "PA5", "PA6",
597 "PA7", "PA8", "PA9", "PA10",
598 "PA11", "PA12", "PA13", "PA14",
600 allwinner,function = "emac";
601 allwinner,drive = <0>;
602 allwinner,pull = <0>;
605 mmc0_pins_a: mmc0@0 {
606 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
607 allwinner,function = "mmc0";
608 allwinner,drive = <2>;
609 allwinner,pull = <0>;
612 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
613 allwinner,pins = "PH1";
614 allwinner,function = "gpio_in";
615 allwinner,drive = <0>;
616 allwinner,pull = <1>;
620 allwinner,pins = "PB3","PB4";
621 allwinner,function = "ir0";
622 allwinner,drive = <0>;
623 allwinner,pull = <0>;
627 allwinner,pins = "PB22","PB23";
628 allwinner,function = "ir1";
629 allwinner,drive = <0>;
630 allwinner,pull = <0>;
635 compatible = "allwinner,sun4i-a10-timer";
636 reg = <0x01c20c00 0x90>;
641 wdt: watchdog@01c20c90 {
642 compatible = "allwinner,sun4i-a10-wdt";
643 reg = <0x01c20c90 0x10>;
647 compatible = "allwinner,sun4i-a10-rtc";
648 reg = <0x01c20d00 0x20>;
653 compatible = "allwinner,sun4i-a10-pwm";
654 reg = <0x01c20e00 0xc>;
661 compatible = "allwinner,sun4i-a10-ir";
662 clocks = <&apb0_gates 6>, <&ir0_clk>;
663 clock-names = "apb", "ir";
665 reg = <0x01c21800 0x40>;
670 compatible = "allwinner,sun4i-a10-ir";
671 clocks = <&apb0_gates 7>, <&ir1_clk>;
672 clock-names = "apb", "ir";
674 reg = <0x01c21c00 0x40>;
678 sid: eeprom@01c23800 {
679 compatible = "allwinner,sun4i-a10-sid";
680 reg = <0x01c23800 0x10>;
684 compatible = "allwinner,sun4i-a10-ts";
685 reg = <0x01c25000 0x100>;
689 uart0: serial@01c28000 {
690 compatible = "snps,dw-apb-uart";
691 reg = <0x01c28000 0x400>;
695 clocks = <&apb1_gates 16>;
699 uart1: serial@01c28400 {
700 compatible = "snps,dw-apb-uart";
701 reg = <0x01c28400 0x400>;
705 clocks = <&apb1_gates 17>;
709 uart2: serial@01c28800 {
710 compatible = "snps,dw-apb-uart";
711 reg = <0x01c28800 0x400>;
715 clocks = <&apb1_gates 18>;
719 uart3: serial@01c28c00 {
720 compatible = "snps,dw-apb-uart";
721 reg = <0x01c28c00 0x400>;
725 clocks = <&apb1_gates 19>;
729 uart4: serial@01c29000 {
730 compatible = "snps,dw-apb-uart";
731 reg = <0x01c29000 0x400>;
735 clocks = <&apb1_gates 20>;
739 uart5: serial@01c29400 {
740 compatible = "snps,dw-apb-uart";
741 reg = <0x01c29400 0x400>;
745 clocks = <&apb1_gates 21>;
749 uart6: serial@01c29800 {
750 compatible = "snps,dw-apb-uart";
751 reg = <0x01c29800 0x400>;
755 clocks = <&apb1_gates 22>;
759 uart7: serial@01c29c00 {
760 compatible = "snps,dw-apb-uart";
761 reg = <0x01c29c00 0x400>;
765 clocks = <&apb1_gates 23>;
770 compatible = "allwinner,sun4i-a10-i2c";
771 reg = <0x01c2ac00 0x400>;
773 clocks = <&apb1_gates 0>;
775 #address-cells = <1>;
780 compatible = "allwinner,sun4i-a10-i2c";
781 reg = <0x01c2b000 0x400>;
783 clocks = <&apb1_gates 1>;
785 #address-cells = <1>;
790 compatible = "allwinner,sun4i-a10-i2c";
791 reg = <0x01c2b400 0x400>;
793 clocks = <&apb1_gates 2>;
795 #address-cells = <1>;