2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include "skeleton.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
65 compatible = "allwinner,simple-framebuffer",
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
68 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
69 <&ahb_gates 44>, <&de_be0_clk>,
70 <&tcon0_ch1_clk>, <&dram_gates 26>;
75 compatible = "allwinner,simple-framebuffer",
77 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
78 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
79 <&ahb_gates 44>, <&ahb_gates 46>,
80 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
81 <&dram_gates 25>, <&dram_gates 26>;
86 compatible = "allwinner,simple-framebuffer",
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
90 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
91 <&dram_gates 25>, <&dram_gates 26>;
96 compatible = "allwinner,simple-framebuffer",
98 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
99 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
100 <&ahb_gates 44>, <&ahb_gates 46>,
101 <&de_be0_clk>, <&de_fe0_clk>,
102 <&tcon0_ch1_clk>, <&dram_gates 5>,
103 <&dram_gates 25>, <&dram_gates 26>;
109 #address-cells = <1>;
113 compatible = "arm,cortex-a8";
116 clock-latency = <244144>; /* 8 32k periods */
124 #cooling-cells = <2>;
125 cooling-min-level = <0>;
126 cooling-max-level = <3>;
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
135 thermal-sensors = <&rtp>;
139 trip = <&cpu_alert0>;
140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
145 cpu_alert0: cpu_alert0 {
147 temperature = <850000>;
154 temperature = <100000>;
163 reg = <0x40000000 0x80000000>;
167 #address-cells = <1>;
172 * This is a dummy clock, to be used as placeholder on
173 * other mux clocks when a specific parent clock is not
174 * yet implemented. It should be dropped when the driver
179 compatible = "fixed-clock";
180 clock-frequency = <0>;
183 osc24M: clk@01c20050 {
185 compatible = "allwinner,sun4i-a10-osc-clk";
186 reg = <0x01c20050 0x4>;
187 clock-frequency = <24000000>;
188 clock-output-names = "osc24M";
192 compatible = "fixed-factor-clock";
197 clock-output-names = "osc3M";
202 compatible = "fixed-clock";
203 clock-frequency = <32768>;
204 clock-output-names = "osc32k";
209 compatible = "allwinner,sun4i-a10-pll1-clk";
210 reg = <0x01c20000 0x4>;
212 clock-output-names = "pll1";
217 compatible = "allwinner,sun4i-a10-pll2-clk";
218 reg = <0x01c20008 0x8>;
220 clock-output-names = "pll2-1x", "pll2-2x",
221 "pll2-4x", "pll2-8x";
226 compatible = "allwinner,sun4i-a10-pll3-clk";
227 reg = <0x01c20010 0x4>;
229 clock-output-names = "pll3";
233 compatible = "fixed-factor-clock";
238 clock-output-names = "pll3-2x";
243 compatible = "allwinner,sun4i-a10-pll1-clk";
244 reg = <0x01c20018 0x4>;
246 clock-output-names = "pll4";
251 compatible = "allwinner,sun4i-a10-pll5-clk";
252 reg = <0x01c20020 0x4>;
254 clock-output-names = "pll5_ddr", "pll5_other";
259 compatible = "allwinner,sun4i-a10-pll6-clk";
260 reg = <0x01c20028 0x4>;
262 clock-output-names = "pll6_sata", "pll6_other", "pll6";
267 compatible = "allwinner,sun4i-a10-pll3-clk";
268 reg = <0x01c20030 0x4>;
270 clock-output-names = "pll7";
274 compatible = "fixed-factor-clock";
279 clock-output-names = "pll7-2x";
285 compatible = "allwinner,sun4i-a10-cpu-clk";
286 reg = <0x01c20054 0x4>;
287 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
288 clock-output-names = "cpu";
293 compatible = "allwinner,sun4i-a10-axi-clk";
294 reg = <0x01c20054 0x4>;
296 clock-output-names = "axi";
299 axi_gates: clk@01c2005c {
301 compatible = "allwinner,sun4i-a10-axi-gates-clk";
302 reg = <0x01c2005c 0x4>;
305 clock-output-names = "axi_dram";
310 compatible = "allwinner,sun4i-a10-ahb-clk";
311 reg = <0x01c20054 0x4>;
313 clock-output-names = "ahb";
316 ahb_gates: clk@01c20060 {
318 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
319 reg = <0x01c20060 0x8>;
321 clock-indices = <0>, <1>,
336 clock-output-names = "ahb_usb0", "ahb_ehci0",
337 "ahb_ohci0", "ahb_ehci1",
338 "ahb_ohci1", "ahb_ss", "ahb_dma",
339 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
340 "ahb_mmc2", "ahb_mmc3", "ahb_ms",
341 "ahb_nand", "ahb_sdram", "ahb_ace",
342 "ahb_emac", "ahb_ts", "ahb_spi0",
343 "ahb_spi1", "ahb_spi2", "ahb_spi3",
344 "ahb_pata", "ahb_sata", "ahb_gps",
345 "ahb_ve", "ahb_tvd", "ahb_tve0",
346 "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
347 "ahb_csi0", "ahb_csi1", "ahb_hdmi",
348 "ahb_de_be0", "ahb_de_be1",
349 "ahb_de_fe0", "ahb_de_fe1",
350 "ahb_mp", "ahb_mali400";
353 apb0: apb0@01c20054 {
355 compatible = "allwinner,sun4i-a10-apb0-clk";
356 reg = <0x01c20054 0x4>;
358 clock-output-names = "apb0";
361 apb0_gates: clk@01c20068 {
363 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
364 reg = <0x01c20068 0x4>;
366 clock-indices = <0>, <1>,
370 clock-output-names = "apb0_codec", "apb0_spdif",
371 "apb0_ac97", "apb0_iis",
372 "apb0_pio", "apb0_ir0",
373 "apb0_ir1", "apb0_keypad";
378 compatible = "allwinner,sun4i-a10-apb1-clk";
379 reg = <0x01c20058 0x4>;
380 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
381 clock-output-names = "apb1";
384 apb1_gates: clk@01c2006c {
386 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
387 reg = <0x01c2006c 0x4>;
389 clock-indices = <0>, <1>,
397 clock-output-names = "apb1_i2c0", "apb1_i2c1",
398 "apb1_i2c2", "apb1_can",
399 "apb1_scr", "apb1_ps20",
400 "apb1_ps21", "apb1_uart0",
401 "apb1_uart1", "apb1_uart2",
402 "apb1_uart3", "apb1_uart4",
403 "apb1_uart5", "apb1_uart6",
407 nand_clk: clk@01c20080 {
409 compatible = "allwinner,sun4i-a10-mod0-clk";
410 reg = <0x01c20080 0x4>;
411 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
412 clock-output-names = "nand";
415 ms_clk: clk@01c20084 {
417 compatible = "allwinner,sun4i-a10-mod0-clk";
418 reg = <0x01c20084 0x4>;
419 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
420 clock-output-names = "ms";
423 mmc0_clk: clk@01c20088 {
425 compatible = "allwinner,sun4i-a10-mmc-clk";
426 reg = <0x01c20088 0x4>;
427 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
428 clock-output-names = "mmc0",
433 mmc1_clk: clk@01c2008c {
435 compatible = "allwinner,sun4i-a10-mmc-clk";
436 reg = <0x01c2008c 0x4>;
437 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
438 clock-output-names = "mmc1",
443 mmc2_clk: clk@01c20090 {
445 compatible = "allwinner,sun4i-a10-mmc-clk";
446 reg = <0x01c20090 0x4>;
447 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
448 clock-output-names = "mmc2",
453 mmc3_clk: clk@01c20094 {
455 compatible = "allwinner,sun4i-a10-mmc-clk";
456 reg = <0x01c20094 0x4>;
457 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
458 clock-output-names = "mmc3",
463 ts_clk: clk@01c20098 {
465 compatible = "allwinner,sun4i-a10-mod0-clk";
466 reg = <0x01c20098 0x4>;
467 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
468 clock-output-names = "ts";
471 ss_clk: clk@01c2009c {
473 compatible = "allwinner,sun4i-a10-mod0-clk";
474 reg = <0x01c2009c 0x4>;
475 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
476 clock-output-names = "ss";
479 spi0_clk: clk@01c200a0 {
481 compatible = "allwinner,sun4i-a10-mod0-clk";
482 reg = <0x01c200a0 0x4>;
483 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
484 clock-output-names = "spi0";
487 spi1_clk: clk@01c200a4 {
489 compatible = "allwinner,sun4i-a10-mod0-clk";
490 reg = <0x01c200a4 0x4>;
491 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
492 clock-output-names = "spi1";
495 spi2_clk: clk@01c200a8 {
497 compatible = "allwinner,sun4i-a10-mod0-clk";
498 reg = <0x01c200a8 0x4>;
499 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
500 clock-output-names = "spi2";
503 pata_clk: clk@01c200ac {
505 compatible = "allwinner,sun4i-a10-mod0-clk";
506 reg = <0x01c200ac 0x4>;
507 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
508 clock-output-names = "pata";
511 ir0_clk: clk@01c200b0 {
513 compatible = "allwinner,sun4i-a10-mod0-clk";
514 reg = <0x01c200b0 0x4>;
515 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
516 clock-output-names = "ir0";
519 ir1_clk: clk@01c200b4 {
521 compatible = "allwinner,sun4i-a10-mod0-clk";
522 reg = <0x01c200b4 0x4>;
523 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
524 clock-output-names = "ir1";
527 spdif_clk: clk@01c200c0 {
529 compatible = "allwinner,sun4i-a10-mod1-clk";
530 reg = <0x01c200c0 0x4>;
531 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
532 <&pll2 SUN4I_A10_PLL2_4X>,
533 <&pll2 SUN4I_A10_PLL2_2X>,
534 <&pll2 SUN4I_A10_PLL2_1X>;
535 clock-output-names = "spdif";
538 usb_clk: clk@01c200cc {
541 compatible = "allwinner,sun4i-a10-usb-clk";
542 reg = <0x01c200cc 0x4>;
544 clock-output-names = "usb_ohci0", "usb_ohci1",
548 spi3_clk: clk@01c200d4 {
550 compatible = "allwinner,sun4i-a10-mod0-clk";
551 reg = <0x01c200d4 0x4>;
552 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
553 clock-output-names = "spi3";
556 dram_gates: clk@01c20100 {
558 compatible = "allwinner,sun4i-a10-dram-gates-clk";
559 reg = <0x01c20100 0x4>;
570 clock-output-names = "dram_ve",
571 "dram_csi0", "dram_csi1",
574 "dram_tve0", "dram_tve1",
576 "dram_de_fe1", "dram_de_fe0",
577 "dram_de_be0", "dram_de_be1",
578 "dram_de_mp", "dram_ace";
581 de_be0_clk: clk@01c20104 {
584 compatible = "allwinner,sun4i-a10-display-clk";
585 reg = <0x01c20104 0x4>;
586 clocks = <&pll3>, <&pll7>, <&pll5 1>;
587 clock-output-names = "de-be0";
590 de_be1_clk: clk@01c20108 {
593 compatible = "allwinner,sun4i-a10-display-clk";
594 reg = <0x01c20108 0x4>;
595 clocks = <&pll3>, <&pll7>, <&pll5 1>;
596 clock-output-names = "de-be1";
599 de_fe0_clk: clk@01c2010c {
602 compatible = "allwinner,sun4i-a10-display-clk";
603 reg = <0x01c2010c 0x4>;
604 clocks = <&pll3>, <&pll7>, <&pll5 1>;
605 clock-output-names = "de-fe0";
608 de_fe1_clk: clk@01c20110 {
611 compatible = "allwinner,sun4i-a10-display-clk";
612 reg = <0x01c20110 0x4>;
613 clocks = <&pll3>, <&pll7>, <&pll5 1>;
614 clock-output-names = "de-fe1";
618 tcon0_ch0_clk: clk@01c20118 {
621 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
622 reg = <0x01c20118 0x4>;
623 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
624 clock-output-names = "tcon0-ch0-sclk";
628 tcon1_ch0_clk: clk@01c2011c {
631 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
632 reg = <0x01c2011c 0x4>;
633 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
634 clock-output-names = "tcon1-ch0-sclk";
638 tcon0_ch1_clk: clk@01c2012c {
640 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
641 reg = <0x01c2012c 0x4>;
642 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
643 clock-output-names = "tcon0-ch1-sclk";
647 tcon1_ch1_clk: clk@01c20130 {
649 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
650 reg = <0x01c20130 0x4>;
651 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
652 clock-output-names = "tcon1-ch1-sclk";
656 ve_clk: clk@01c2013c {
659 compatible = "allwinner,sun4i-a10-ve-clk";
660 reg = <0x01c2013c 0x4>;
662 clock-output-names = "ve";
665 codec_clk: clk@01c20140 {
667 compatible = "allwinner,sun4i-a10-codec-clk";
668 reg = <0x01c20140 0x4>;
669 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
670 clock-output-names = "codec";
675 compatible = "simple-bus";
676 #address-cells = <1>;
680 sram-controller@01c00000 {
681 compatible = "allwinner,sun4i-a10-sram-controller";
682 reg = <0x01c00000 0x30>;
683 #address-cells = <1>;
687 sram_a: sram@00000000 {
688 compatible = "mmio-sram";
689 reg = <0x00000000 0xc000>;
690 #address-cells = <1>;
692 ranges = <0 0x00000000 0xc000>;
694 emac_sram: sram-section@8000 {
695 compatible = "allwinner,sun4i-a10-sram-a3-a4";
696 reg = <0x8000 0x4000>;
701 sram_d: sram@00010000 {
702 compatible = "mmio-sram";
703 reg = <0x00010000 0x1000>;
704 #address-cells = <1>;
706 ranges = <0 0x00010000 0x1000>;
708 otg_sram: sram-section@0000 {
709 compatible = "allwinner,sun4i-a10-sram-d";
710 reg = <0x0000 0x1000>;
716 dma: dma-controller@01c02000 {
717 compatible = "allwinner,sun4i-a10-dma";
718 reg = <0x01c02000 0x1000>;
720 clocks = <&ahb_gates 6>;
725 compatible = "allwinner,sun4i-a10-nand";
726 reg = <0x01c03000 0x1000>;
728 clocks = <&ahb_gates 13>, <&nand_clk>;
729 clock-names = "ahb", "mod";
730 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
733 #address-cells = <1>;
738 compatible = "allwinner,sun4i-a10-spi";
739 reg = <0x01c05000 0x1000>;
741 clocks = <&ahb_gates 20>, <&spi0_clk>;
742 clock-names = "ahb", "mod";
743 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
744 <&dma SUN4I_DMA_DEDICATED 26>;
745 dma-names = "rx", "tx";
747 #address-cells = <1>;
752 compatible = "allwinner,sun4i-a10-spi";
753 reg = <0x01c06000 0x1000>;
755 clocks = <&ahb_gates 21>, <&spi1_clk>;
756 clock-names = "ahb", "mod";
757 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
758 <&dma SUN4I_DMA_DEDICATED 8>;
759 dma-names = "rx", "tx";
761 #address-cells = <1>;
765 emac: ethernet@01c0b000 {
766 compatible = "allwinner,sun4i-a10-emac";
767 reg = <0x01c0b000 0x1000>;
769 clocks = <&ahb_gates 17>;
770 allwinner,sram = <&emac_sram 1>;
774 mdio: mdio@01c0b080 {
775 compatible = "allwinner,sun4i-a10-mdio";
776 reg = <0x01c0b080 0x14>;
778 #address-cells = <1>;
783 compatible = "allwinner,sun4i-a10-mmc";
784 reg = <0x01c0f000 0x1000>;
785 clocks = <&ahb_gates 8>,
795 #address-cells = <1>;
800 compatible = "allwinner,sun4i-a10-mmc";
801 reg = <0x01c10000 0x1000>;
802 clocks = <&ahb_gates 9>,
812 #address-cells = <1>;
817 compatible = "allwinner,sun4i-a10-mmc";
818 reg = <0x01c11000 0x1000>;
819 clocks = <&ahb_gates 10>,
829 #address-cells = <1>;
834 compatible = "allwinner,sun4i-a10-mmc";
835 reg = <0x01c12000 0x1000>;
836 clocks = <&ahb_gates 11>,
846 #address-cells = <1>;
850 usb_otg: usb@01c13000 {
851 compatible = "allwinner,sun4i-a10-musb";
852 reg = <0x01c13000 0x0400>;
853 clocks = <&ahb_gates 0>;
855 interrupt-names = "mc";
858 extcon = <&usbphy 0>;
859 allwinner,sram = <&otg_sram 1>;
863 usbphy: phy@01c13400 {
865 compatible = "allwinner,sun4i-a10-usb-phy";
866 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
867 reg-names = "phy_ctrl", "pmu1", "pmu2";
868 clocks = <&usb_clk 8>;
869 clock-names = "usb_phy";
870 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
871 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
875 ehci0: usb@01c14000 {
876 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
877 reg = <0x01c14000 0x100>;
879 clocks = <&ahb_gates 1>;
885 ohci0: usb@01c14400 {
886 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
887 reg = <0x01c14400 0x100>;
889 clocks = <&usb_clk 6>, <&ahb_gates 2>;
895 crypto: crypto-engine@01c15000 {
896 compatible = "allwinner,sun4i-a10-crypto";
897 reg = <0x01c15000 0x1000>;
899 clocks = <&ahb_gates 5>, <&ss_clk>;
900 clock-names = "ahb", "mod";
904 compatible = "allwinner,sun4i-a10-spi";
905 reg = <0x01c17000 0x1000>;
907 clocks = <&ahb_gates 22>, <&spi2_clk>;
908 clock-names = "ahb", "mod";
909 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
910 <&dma SUN4I_DMA_DEDICATED 28>;
911 dma-names = "rx", "tx";
913 #address-cells = <1>;
917 ahci: sata@01c18000 {
918 compatible = "allwinner,sun4i-a10-ahci";
919 reg = <0x01c18000 0x1000>;
921 clocks = <&pll6 0>, <&ahb_gates 25>;
925 ehci1: usb@01c1c000 {
926 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
927 reg = <0x01c1c000 0x100>;
929 clocks = <&ahb_gates 3>;
935 ohci1: usb@01c1c400 {
936 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
937 reg = <0x01c1c400 0x100>;
939 clocks = <&usb_clk 7>, <&ahb_gates 4>;
946 compatible = "allwinner,sun4i-a10-spi";
947 reg = <0x01c1f000 0x1000>;
949 clocks = <&ahb_gates 23>, <&spi3_clk>;
950 clock-names = "ahb", "mod";
951 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
952 <&dma SUN4I_DMA_DEDICATED 30>;
953 dma-names = "rx", "tx";
955 #address-cells = <1>;
959 intc: interrupt-controller@01c20400 {
960 compatible = "allwinner,sun4i-a10-ic";
961 reg = <0x01c20400 0x400>;
962 interrupt-controller;
963 #interrupt-cells = <1>;
966 pio: pinctrl@01c20800 {
967 compatible = "allwinner,sun4i-a10-pinctrl";
968 reg = <0x01c20800 0x400>;
970 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
971 clock-names = "apb", "hosc", "losc";
973 interrupt-controller;
974 #interrupt-cells = <3>;
977 emac_pins_a: emac0@0 {
978 pins = "PA0", "PA1", "PA2",
979 "PA3", "PA4", "PA5", "PA6",
980 "PA7", "PA8", "PA9", "PA10",
981 "PA11", "PA12", "PA13", "PA14",
986 i2c0_pins_a: i2c0@0 {
991 i2c1_pins_a: i2c1@0 {
992 pins = "PB18", "PB19";
996 i2c2_pins_a: i2c2@0 {
997 pins = "PB20", "PB21";
1001 ir0_rx_pins_a: ir0@0 {
1006 ir0_tx_pins_a: ir0@1 {
1011 ir1_rx_pins_a: ir1@0 {
1016 ir1_tx_pins_a: ir1@1 {
1021 mmc0_pins_a: mmc0@0 {
1022 pins = "PF0", "PF1", "PF2",
1023 "PF3", "PF4", "PF5";
1025 drive-strength = <30>;
1029 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1031 function = "gpio_in";
1035 ps20_pins_a: ps20@0 {
1036 pins = "PI20", "PI21";
1040 ps21_pins_a: ps21@0 {
1041 pins = "PH12", "PH13";
1045 pwm0_pins_a: pwm0@0 {
1050 pwm1_pins_a: pwm1@0 {
1055 spdif_tx_pins_a: spdif@0 {
1061 spi0_pins_a: spi0@0 {
1062 pins = "PI11", "PI12", "PI13";
1066 spi0_cs0_pins_a: spi0_cs0@0 {
1071 spi1_pins_a: spi1@0 {
1072 pins = "PI17", "PI18", "PI19";
1076 spi1_cs0_pins_a: spi1_cs0@0 {
1081 spi2_pins_a: spi2@0 {
1082 pins = "PC20", "PC21", "PC22";
1086 spi2_pins_b: spi2@1 {
1087 pins = "PB15", "PB16", "PB17";
1091 spi2_cs0_pins_a: spi2_cs0@0 {
1096 spi2_cs0_pins_b: spi2_cs0@1 {
1101 uart0_pins_a: uart0@0 {
1102 pins = "PB22", "PB23";
1106 uart0_pins_b: uart0@1 {
1107 pins = "PF2", "PF4";
1111 uart1_pins_a: uart1@0 {
1112 pins = "PA10", "PA11";
1118 compatible = "allwinner,sun4i-a10-timer";
1119 reg = <0x01c20c00 0x90>;
1124 wdt: watchdog@01c20c90 {
1125 compatible = "allwinner,sun4i-a10-wdt";
1126 reg = <0x01c20c90 0x10>;
1130 compatible = "allwinner,sun4i-a10-rtc";
1131 reg = <0x01c20d00 0x20>;
1136 compatible = "allwinner,sun4i-a10-pwm";
1137 reg = <0x01c20e00 0xc>;
1140 status = "disabled";
1143 spdif: spdif@01c21000 {
1144 #sound-dai-cells = <0>;
1145 compatible = "allwinner,sun4i-a10-spdif";
1146 reg = <0x01c21000 0x400>;
1148 clocks = <&apb0_gates 1>, <&spdif_clk>;
1149 clock-names = "apb", "spdif";
1150 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1151 <&dma SUN4I_DMA_NORMAL 2>;
1152 dma-names = "rx", "tx";
1153 status = "disabled";
1157 compatible = "allwinner,sun4i-a10-ir";
1158 clocks = <&apb0_gates 6>, <&ir0_clk>;
1159 clock-names = "apb", "ir";
1161 reg = <0x01c21800 0x40>;
1162 status = "disabled";
1166 compatible = "allwinner,sun4i-a10-ir";
1167 clocks = <&apb0_gates 7>, <&ir1_clk>;
1168 clock-names = "apb", "ir";
1170 reg = <0x01c21c00 0x40>;
1171 status = "disabled";
1174 lradc: lradc@01c22800 {
1175 compatible = "allwinner,sun4i-a10-lradc-keys";
1176 reg = <0x01c22800 0x100>;
1178 status = "disabled";
1181 codec: codec@01c22c00 {
1182 #sound-dai-cells = <0>;
1183 compatible = "allwinner,sun4i-a10-codec";
1184 reg = <0x01c22c00 0x40>;
1186 clocks = <&apb0_gates 0>, <&codec_clk>;
1187 clock-names = "apb", "codec";
1188 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1189 <&dma SUN4I_DMA_NORMAL 19>;
1190 dma-names = "rx", "tx";
1191 status = "disabled";
1194 sid: eeprom@01c23800 {
1195 compatible = "allwinner,sun4i-a10-sid";
1196 reg = <0x01c23800 0x10>;
1200 compatible = "allwinner,sun4i-a10-ts";
1201 reg = <0x01c25000 0x100>;
1203 #thermal-sensor-cells = <0>;
1206 uart0: serial@01c28000 {
1207 compatible = "snps,dw-apb-uart";
1208 reg = <0x01c28000 0x400>;
1212 clocks = <&apb1_gates 16>;
1213 status = "disabled";
1216 uart1: serial@01c28400 {
1217 compatible = "snps,dw-apb-uart";
1218 reg = <0x01c28400 0x400>;
1222 clocks = <&apb1_gates 17>;
1223 status = "disabled";
1226 uart2: serial@01c28800 {
1227 compatible = "snps,dw-apb-uart";
1228 reg = <0x01c28800 0x400>;
1232 clocks = <&apb1_gates 18>;
1233 status = "disabled";
1236 uart3: serial@01c28c00 {
1237 compatible = "snps,dw-apb-uart";
1238 reg = <0x01c28c00 0x400>;
1242 clocks = <&apb1_gates 19>;
1243 status = "disabled";
1246 uart4: serial@01c29000 {
1247 compatible = "snps,dw-apb-uart";
1248 reg = <0x01c29000 0x400>;
1252 clocks = <&apb1_gates 20>;
1253 status = "disabled";
1256 uart5: serial@01c29400 {
1257 compatible = "snps,dw-apb-uart";
1258 reg = <0x01c29400 0x400>;
1262 clocks = <&apb1_gates 21>;
1263 status = "disabled";
1266 uart6: serial@01c29800 {
1267 compatible = "snps,dw-apb-uart";
1268 reg = <0x01c29800 0x400>;
1272 clocks = <&apb1_gates 22>;
1273 status = "disabled";
1276 uart7: serial@01c29c00 {
1277 compatible = "snps,dw-apb-uart";
1278 reg = <0x01c29c00 0x400>;
1282 clocks = <&apb1_gates 23>;
1283 status = "disabled";
1286 i2c0: i2c@01c2ac00 {
1287 compatible = "allwinner,sun4i-a10-i2c";
1288 reg = <0x01c2ac00 0x400>;
1290 clocks = <&apb1_gates 0>;
1291 status = "disabled";
1292 #address-cells = <1>;
1296 i2c1: i2c@01c2b000 {
1297 compatible = "allwinner,sun4i-a10-i2c";
1298 reg = <0x01c2b000 0x400>;
1300 clocks = <&apb1_gates 1>;
1301 status = "disabled";
1302 #address-cells = <1>;
1306 i2c2: i2c@01c2b400 {
1307 compatible = "allwinner,sun4i-a10-i2c";
1308 reg = <0x01c2b400 0x400>;
1310 clocks = <&apb1_gates 2>;
1311 status = "disabled";
1312 #address-cells = <1>;
1316 ps20: ps2@01c2a000 {
1317 compatible = "allwinner,sun4i-a10-ps2";
1318 reg = <0x01c2a000 0x400>;
1320 clocks = <&apb1_gates 6>;
1321 status = "disabled";
1324 ps21: ps2@01c2a400 {
1325 compatible = "allwinner,sun4i-a10-ps2";
1326 reg = <0x01c2a400 0x400>;
1328 clocks = <&apb1_gates 7>;
1329 status = "disabled";