arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/clock/sun5i-ccu.h>
  48 #include <dt-bindings/dma/sun4i-a10.h>
  49 #include <dt-bindings/reset/sun5i-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&intc>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a8";
  61                         reg = <0x0>;
  62                         clocks = <&ccu CLK_CPU>;
  63                 };
  64         };
  65
  66         chosen {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 framebuffer@0 {
  72                         compatible = "allwinner,simple-framebuffer",
  73                                      "simple-framebuffer";
  74                         allwinner,pipeline = "de_be0-lcd0";
  75                         clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  76                                  <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
  77                         status = "disabled";
  78                 };
  79
  80                 framebuffer@1 {
  81                         compatible = "allwinner,simple-framebuffer",
  82                                      "simple-framebuffer";
  83                         allwinner,pipeline = "de_be0-lcd0-tve0";
  84                         clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
  85                                  <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  86                                  <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
  87                         status = "disabled";
  88                 };
  89         };
  90
  91         clocks {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 osc24M: clk@01c20050 {
  97                         #clock-cells = <0>;
  98                         compatible = "fixed-clock";
  99                         clock-frequency = <24000000>;
 100                         clock-output-names = "osc24M";
 101                 };
 102
 103                 osc32k: clk@0 {
 104                         #clock-cells = <0>;
 105                         compatible = "fixed-clock";
 106                         clock-frequency = <32768>;
 107                         clock-output-names = "osc32k";
 108                 };
 109         };
 110
 111         soc@01c00000 {
 112                 compatible = "simple-bus";
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115                 ranges;
 116
 117                 sram-controller@01c00000 {
 118                         compatible = "allwinner,sun4i-a10-sram-controller";
 119                         reg = <0x01c00000 0x30>;
 120                         #address-cells = <1>;
 121                         #size-cells = <1>;
 122                         ranges;
 123
 124                         sram_a: sram@00000000 {
 125                                 compatible = "mmio-sram";
 126                                 reg = <0x00000000 0xc000>;
 127                                 #address-cells = <1>;
 128                                 #size-cells = <1>;
 129                                 ranges = <0 0x00000000 0xc000>;
 130                         };
 131
 132                         emac_sram: sram-section@8000 {
 133                                 compatible = "allwinner,sun4i-a10-sram-a3-a4";
 134                                 reg = <0x8000 0x4000>;
 135                                 status = "disabled";
 136                         };
 137
 138                         sram_d: sram@00010000 {
 139                                 compatible = "mmio-sram";
 140                                 reg = <0x00010000 0x1000>;
 141                                 #address-cells = <1>;
 142                                 #size-cells = <1>;
 143                                 ranges = <0 0x00010000 0x1000>;
 144
 145                                 otg_sram: sram-section@0000 {
 146                                         compatible = "allwinner,sun4i-a10-sram-d";
 147                                         reg = <0x0000 0x1000>;
 148                                         status = "disabled";
 149                                 };
 150                         };
 151                 };
 152
 153                 dma: dma-controller@01c02000 {
 154                         compatible = "allwinner,sun4i-a10-dma";
 155                         reg = <0x01c02000 0x1000>;
 156                         interrupts = <27>;
 157                         clocks = <&ccu CLK_AHB_DMA>;
 158                         #dma-cells = <2>;
 159                 };
 160
 161                 nfc: nand@01c03000 {
 162                         compatible = "allwinner,sun4i-a10-nand";
 163                         reg = <0x01c03000 0x1000>;
 164                         interrupts = <37>;
 165                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 166                         clock-names = "ahb", "mod";
 167                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 168                         dma-names = "rxtx";
 169                         status = "disabled";
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                 };
 173
 174                 spi0: spi@01c05000 {
 175                         compatible = "allwinner,sun4i-a10-spi";
 176                         reg = <0x01c05000 0x1000>;
 177                         interrupts = <10>;
 178                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 179                         clock-names = "ahb", "mod";
 180                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 181                                <&dma SUN4I_DMA_DEDICATED 26>;
 182                         dma-names = "rx", "tx";
 183                         status = "disabled";
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                 };
 187
 188                 spi1: spi@01c06000 {
 189                         compatible = "allwinner,sun4i-a10-spi";
 190                         reg = <0x01c06000 0x1000>;
 191                         interrupts = <11>;
 192                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 193                         clock-names = "ahb", "mod";
 194                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 195                                <&dma SUN4I_DMA_DEDICATED 8>;
 196                         dma-names = "rx", "tx";
 197                         status = "disabled";
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                 };
 201
 202                 tve0: tv-encoder@01c0a000 {
 203                         compatible = "allwinner,sun4i-a10-tv-encoder";
 204                         reg = <0x01c0a000 0x1000>;
 205                         clocks = <&ccu CLK_AHB_TVE>;
 206                         resets = <&ccu RST_TVE>;
 207                         status = "disabled";
 208
 209                         port {
 210                                 #address-cells = <1>;
 211                                 #size-cells = <0>;
 212
 213                                 tve0_in_tcon0: endpoint@0 {
 214                                         reg = <0>;
 215                                         remote-endpoint = <&tcon0_out_tve0>;
 216                                 };
 217                         };
 218                 };
 219
 220                 emac: ethernet@01c0b000 {
 221                         compatible = "allwinner,sun4i-a10-emac";
 222                         reg = <0x01c0b000 0x1000>;
 223                         interrupts = <55>;
 224                         clocks = <&ccu CLK_AHB_EMAC>;
 225                         allwinner,sram = <&emac_sram 1>;
 226                         status = "disabled";
 227                 };
 228
 229                 mdio: mdio@01c0b080 {
 230                         compatible = "allwinner,sun4i-a10-mdio";
 231                         reg = <0x01c0b080 0x14>;
 232                         status = "disabled";
 233                         #address-cells = <1>;
 234                         #size-cells = <0>;
 235                 };
 236
 237                 tcon0: lcd-controller@01c0c000 {
 238                         compatible = "allwinner,sun5i-a13-tcon";
 239                         reg = <0x01c0c000 0x1000>;
 240                         interrupts = <44>;
 241                         resets = <&ccu RST_LCD>;
 242                         reset-names = "lcd";
 243                         clocks = <&ccu CLK_AHB_LCD>,
 244                                  <&ccu CLK_TCON_CH0>,
 245                                  <&ccu CLK_TCON_CH1>;
 246                         clock-names = "ahb",
 247                                       "tcon-ch0",
 248                                       "tcon-ch1";
 249                         clock-output-names = "tcon-pixel-clock";
 250                         status = "disabled";
 251
 252                         ports {
 253                                 #address-cells = <1>;
 254                                 #size-cells = <0>;
 255
 256                                 tcon0_in: port@0 {
 257                                         #address-cells = <1>;
 258                                         #size-cells = <0>;
 259                                         reg = <0>;
 260
 261                                         tcon0_in_be0: endpoint@0 {
 262                                                 reg = <0>;
 263                                                 remote-endpoint = <&be0_out_tcon0>;
 264                                         };
 265                                 };
 266
 267                                 tcon0_out: port@1 {
 268                                         #address-cells = <1>;
 269                                         #size-cells = <0>;
 270                                         reg = <1>;
 271
 272                                         tcon0_out_tve0: endpoint@1 {
 273                                                 reg = <1>;
 274                                                 remote-endpoint = <&tve0_in_tcon0>;
 275                                         };
 276                                 };
 277                         };
 278                 };
 279
 280                 mmc0: mmc@01c0f000 {
 281                         compatible = "allwinner,sun5i-a13-mmc";
 282                         reg = <0x01c0f000 0x1000>;
 283                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 284                         clock-names = "ahb", "mmc";
 285                         interrupts = <32>;
 286                         status = "disabled";
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                 };
 290
 291                 mmc1: mmc@01c10000 {
 292                         compatible = "allwinner,sun5i-a13-mmc";
 293                         reg = <0x01c10000 0x1000>;
 294                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 295                         clock-names = "ahb", "mmc";
 296                         interrupts = <33>;
 297                         status = "disabled";
 298                         #address-cells = <1>;
 299                         #size-cells = <0>;
 300                 };
 301
 302                 mmc2: mmc@01c11000 {
 303                         compatible = "allwinner,sun5i-a13-mmc";
 304                         reg = <0x01c11000 0x1000>;
 305                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 306                         clock-names = "ahb", "mmc";
 307                         interrupts = <34>;
 308                         status = "disabled";
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                 };
 312
 313                 usb_otg: usb@01c13000 {
 314                         compatible = "allwinner,sun4i-a10-musb";
 315                         reg = <0x01c13000 0x0400>;
 316                         clocks = <&ccu CLK_AHB_OTG>;
 317                         interrupts = <38>;
 318                         interrupt-names = "mc";
 319                         phys = <&usbphy 0>;
 320                         phy-names = "usb";
 321                         extcon = <&usbphy 0>;
 322                         allwinner,sram = <&otg_sram 1>;
 323                         status = "disabled";
 324                 };
 325
 326                 usbphy: phy@01c13400 {
 327                         #phy-cells = <1>;
 328                         compatible = "allwinner,sun5i-a13-usb-phy";
 329                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 330                         reg-names = "phy_ctrl", "pmu1";
 331                         clocks = <&ccu CLK_USB_PHY0>;
 332                         clock-names = "usb_phy";
 333                         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
 334                         reset-names = "usb0_reset", "usb1_reset";
 335                         status = "disabled";
 336                 };
 337
 338                 ehci0: usb@01c14000 {
 339                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 340                         reg = <0x01c14000 0x100>;
 341                         interrupts = <39>;
 342                         clocks = <&ccu CLK_AHB_EHCI>;
 343                         phys = <&usbphy 1>;
 344                         phy-names = "usb";
 345                         status = "disabled";
 346                 };
 347
 348                 ohci0: usb@01c14400 {
 349                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 350                         reg = <0x01c14400 0x100>;
 351                         interrupts = <40>;
 352                         clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
 353                         phys = <&usbphy 1>;
 354                         phy-names = "usb";
 355                         status = "disabled";
 356                 };
 357
 358                 spi2: spi@01c17000 {
 359                         compatible = "allwinner,sun4i-a10-spi";
 360                         reg = <0x01c17000 0x1000>;
 361                         interrupts = <12>;
 362                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 363                         clock-names = "ahb", "mod";
 364                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 365                                <&dma SUN4I_DMA_DEDICATED 28>;
 366                         dma-names = "rx", "tx";
 367                         status = "disabled";
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                 };
 371
 372                 ccu: clock@01c20000 {
 373                         reg = <0x01c20000 0x400>;
 374                         clocks = <&osc24M>, <&osc32k>;
 375                         clock-names = "hosc", "losc";
 376                         #clock-cells = <1>;
 377                         #reset-cells = <1>;
 378                 };
 379
 380                 intc: interrupt-controller@01c20400 {
 381                         compatible = "allwinner,sun4i-a10-ic";
 382                         reg = <0x01c20400 0x400>;
 383                         interrupt-controller;
 384                         #interrupt-cells = <1>;
 385                 };
 386
 387                 pio: pinctrl@01c20800 {
 388                         reg = <0x01c20800 0x400>;
 389                         interrupts = <28>;
 390                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 391                         clock-names = "apb", "hosc", "losc";
 392                         gpio-controller;
 393                         interrupt-controller;
 394                         #interrupt-cells = <3>;
 395                         #gpio-cells = <3>;
 396
 397                         emac_pins_a: emac0@0 {
 398                                 pins = "PD6", "PD7", "PD10",
 399                                        "PD11", "PD12", "PD13", "PD14",
 400                                        "PD15", "PD18", "PD19", "PD20",
 401                                        "PD21", "PD22", "PD23", "PD24",
 402                                        "PD25", "PD26", "PD27";
 403                                 function = "emac";
 404                         };
 405
 406                         i2c0_pins_a: i2c0@0 {
 407                                 pins = "PB0", "PB1";
 408                                 function = "i2c0";
 409                         };
 410
 411                         i2c1_pins_a: i2c1@0 {
 412                                 pins = "PB15", "PB16";
 413                                 function = "i2c1";
 414                         };
 415
 416                         i2c2_pins_a: i2c2@0 {
 417                                 pins = "PB17", "PB18";
 418                                 function = "i2c2";
 419                         };
 420
 421                         ir0_rx_pins_a: ir0@0 {
 422                                 pins = "PB4";
 423                                 function = "ir0";
 424                         };
 425
 426                         lcd_rgb565_pins: lcd_rgb565@0 {
 427                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
 428                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 429                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
 430                                                  "PD24", "PD25", "PD26", "PD27";
 431                                 function = "lcd0";
 432                         };
 433
 434                         lcd_rgb666_pins: lcd_rgb666@0 {
 435                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 436                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 437                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 438                                        "PD24", "PD25", "PD26", "PD27";
 439                                 function = "lcd0";
 440                         };
 441
 442                         mmc0_pins_a: mmc0@0 {
 443                                 pins = "PF0", "PF1", "PF2", "PF3",
 444                                        "PF4", "PF5";
 445                                 function = "mmc0";
 446                                 drive-strength = <30>;
 447                                 bias-pull-up;
 448                         };
 449
 450                         mmc2_pins_a: mmc2@0 {
 451                                 pins = "PC6", "PC7", "PC8", "PC9",
 452                                        "PC10", "PC11", "PC12", "PC13",
 453                                        "PC14", "PC15";
 454                                 function = "mmc2";
 455                                 drive-strength = <30>;
 456                                 bias-pull-up;
 457                         };
 458
 459                         mmc2_4bit_pins_a: mmc2-4bit@0 {
 460                                 pins = "PC6", "PC7", "PC8", "PC9",
 461                                        "PC10", "PC11";
 462                                 function = "mmc2";
 463                                 drive-strength = <30>;
 464                                 bias-pull-up;
 465                         };
 466
 467                         nand_pins_a: nand-base0@0 {
 468                                 pins = "PC0", "PC1", "PC2",
 469                                        "PC5", "PC8", "PC9", "PC10",
 470                                        "PC11", "PC12", "PC13", "PC14",
 471                                        "PC15";
 472                                 function = "nand0";
 473                         };
 474
 475                         nand_cs0_pins_a: nand-cs@0 {
 476                                 pins = "PC4";
 477                                 function = "nand0";
 478                         };
 479
 480                         nand_rb0_pins_a: nand-rb@0 {
 481                                 pins = "PC6";
 482                                 function = "nand0";
 483                         };
 484
 485                         spi2_pins_a: spi2@0 {
 486                                 pins = "PE1", "PE2", "PE3";
 487                                 function = "spi2";
 488                         };
 489
 490                         spi2_cs0_pins_a: spi2-cs0@0 {
 491                                 pins = "PE0";
 492                                 function = "spi2";
 493                         };
 494
 495                         uart1_pins_a: uart1@0 {
 496                                 pins = "PE10", "PE11";
 497                                 function = "uart1";
 498                         };
 499
 500                         uart1_pins_b: uart1@1 {
 501                                 pins = "PG3", "PG4";
 502                                 function = "uart1";
 503                         };
 504
 505                         uart2_pins_a: uart2@0 {
 506                                 pins = "PD2", "PD3";
 507                                 function = "uart2";
 508                         };
 509
 510                         uart2_cts_rts_pins_a: uart2-cts-rts@0 {
 511                                 pins = "PD4", "PD5";
 512                                 function = "uart2";
 513                         };
 514
 515                         uart3_pins_a: uart3@0 {
 516                                 pins = "PG9", "PG10";
 517                                 function = "uart3";
 518                         };
 519
 520                         uart3_cts_rts_pins_a: uart3-cts-rts@0 {
 521                                 pins = "PG11", "PG12";
 522                                 function = "uart3";
 523                         };
 524
 525                         pwm0_pins: pwm0 {
 526                                 pins = "PB2";
 527                                 function = "pwm";
 528                         };
 529                 };
 530
 531                 timer@01c20c00 {
 532                         compatible = "allwinner,sun4i-a10-timer";
 533                         reg = <0x01c20c00 0x90>;
 534                         interrupts = <22>;
 535                         clocks = <&ccu CLK_HOSC>;
 536                 };
 537
 538                 wdt: watchdog@01c20c90 {
 539                         compatible = "allwinner,sun4i-a10-wdt";
 540                         reg = <0x01c20c90 0x10>;
 541                 };
 542
 543                 ir0: ir@01c21800 {
 544                         compatible = "allwinner,sun4i-a10-ir";
 545                         clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
 546                         clock-names = "apb", "ir";
 547                         interrupts = <5>;
 548                         reg = <0x01c21800 0x40>;
 549                         status = "disabled";
 550                 };
 551
 552                 lradc: lradc@01c22800 {
 553                         compatible = "allwinner,sun4i-a10-lradc-keys";
 554                         reg = <0x01c22800 0x100>;
 555                         interrupts = <31>;
 556                         status = "disabled";
 557                 };
 558
 559                 codec: codec@01c22c00 {
 560                         #sound-dai-cells = <0>;
 561                         compatible = "allwinner,sun4i-a10-codec";
 562                         reg = <0x01c22c00 0x40>;
 563                         interrupts = <30>;
 564                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 565                         clock-names = "apb", "codec";
 566                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 567                                <&dma SUN4I_DMA_NORMAL 19>;
 568                         dma-names = "rx", "tx";
 569                         status = "disabled";
 570                 };
 571
 572                 sid: eeprom@01c23800 {
 573                         compatible = "allwinner,sun4i-a10-sid";
 574                         reg = <0x01c23800 0x10>;
 575                 };
 576
 577                 rtp: rtp@01c25000 {
 578                         compatible = "allwinner,sun5i-a13-ts";
 579                         reg = <0x01c25000 0x100>;
 580                         interrupts = <29>;
 581                         #thermal-sensor-cells = <0>;
 582                 };
 583
 584                 uart0: serial@01c28000 {
 585                         compatible = "snps,dw-apb-uart";
 586                         reg = <0x01c28000 0x400>;
 587                         interrupts = <1>;
 588                         reg-shift = <2>;
 589                         reg-io-width = <4>;
 590                         clocks = <&ccu CLK_APB1_UART0>;
 591                         status = "disabled";
 592                 };
 593
 594                 uart1: serial@01c28400 {
 595                         compatible = "snps,dw-apb-uart";
 596                         reg = <0x01c28400 0x400>;
 597                         interrupts = <2>;
 598                         reg-shift = <2>;
 599                         reg-io-width = <4>;
 600                         clocks = <&ccu CLK_APB1_UART1>;
 601                         status = "disabled";
 602                 };
 603
 604                 uart2: serial@01c28800 {
 605                         compatible = "snps,dw-apb-uart";
 606                         reg = <0x01c28800 0x400>;
 607                         interrupts = <3>;
 608                         reg-shift = <2>;
 609                         reg-io-width = <4>;
 610                         clocks = <&ccu CLK_APB1_UART2>;
 611                         status = "disabled";
 612                 };
 613
 614                 uart3: serial@01c28c00 {
 615                         compatible = "snps,dw-apb-uart";
 616                         reg = <0x01c28c00 0x400>;
 617                         interrupts = <4>;
 618                         reg-shift = <2>;
 619                         reg-io-width = <4>;
 620                         clocks = <&ccu CLK_APB1_UART3>;
 621                         status = "disabled";
 622                 };
 623
 624                 i2c0: i2c@01c2ac00 {
 625                         compatible = "allwinner,sun4i-a10-i2c";
 626                         reg = <0x01c2ac00 0x400>;
 627                         interrupts = <7>;
 628                         clocks = <&ccu CLK_APB1_I2C0>;
 629                         status = "disabled";
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632                 };
 633
 634                 i2c1: i2c@01c2b000 {
 635                         compatible = "allwinner,sun4i-a10-i2c";
 636                         reg = <0x01c2b000 0x400>;
 637                         interrupts = <8>;
 638                         clocks = <&ccu CLK_APB1_I2C1>;
 639                         status = "disabled";
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642                 };
 643
 644                 i2c2: i2c@01c2b400 {
 645                         compatible = "allwinner,sun4i-a10-i2c";
 646                         reg = <0x01c2b400 0x400>;
 647                         interrupts = <9>;
 648                         clocks = <&ccu CLK_APB1_I2C2>;
 649                         status = "disabled";
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                 };
 653
 654                 timer@01c60000 {
 655                         compatible = "allwinner,sun5i-a13-hstimer";
 656                         reg = <0x01c60000 0x1000>;
 657                         interrupts = <82>, <83>;
 658                         clocks = <&ccu CLK_AHB_HSTIMER>;
 659                 };
 660
 661                 fe0: display-frontend@01e00000 {
 662                         compatible = "allwinner,sun5i-a13-display-frontend";
 663                         reg = <0x01e00000 0x20000>;
 664                         interrupts = <47>;
 665                         clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
 666                                  <&ccu CLK_DRAM_DE_FE>;
 667                         clock-names = "ahb", "mod",
 668                                       "ram";
 669                         resets = <&ccu RST_DE_FE>;
 670                         status = "disabled";
 671
 672                         ports {
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675
 676                                 fe0_out: port@1 {
 677                                         #address-cells = <1>;
 678                                         #size-cells = <0>;
 679                                         reg = <1>;
 680
 681                                         fe0_out_be0: endpoint@0 {
 682                                                 reg = <0>;
 683                                                 remote-endpoint = <&be0_in_fe0>;
 684                                         };
 685                                 };
 686                         };
 687                 };
 688
 689                 be0: display-backend@01e60000 {
 690                         compatible = "allwinner,sun5i-a13-display-backend";
 691                         reg = <0x01e60000 0x10000>;
 692                         interrupts = <47>;
 693                         clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
 694                                  <&ccu CLK_DRAM_DE_BE>;
 695                         clock-names = "ahb", "mod",
 696                                       "ram";
 697                         resets = <&ccu RST_DE_BE>;
 698                         status = "disabled";
 699
 700                         assigned-clocks = <&ccu CLK_DE_BE>;
 701                         assigned-clock-rates = <300000000>;
 702
 703                         ports {
 704                                 #address-cells = <1>;
 705                                 #size-cells = <0>;
 706
 707                                 be0_in: port@0 {
 708                                         #address-cells = <1>;
 709                                         #size-cells = <0>;
 710                                         reg = <0>;
 711
 712                                         be0_in_fe0: endpoint@0 {
 713                                                 reg = <0>;
 714                                                 remote-endpoint = <&fe0_out_be0>;
 715                                         };
 716                                 };
 717
 718                                 be0_out: port@1 {
 719                                         #address-cells = <1>;
 720                                         #size-cells = <0>;
 721                                         reg = <1>;
 722
 723                                         be0_out_tcon0: endpoint@0 {
 724                                                 reg = <0>;
 725                                                 remote-endpoint = <&tcon0_in_be0>;
 726                                         };
 727                                 };
 728                         };
 729                 };
 730         };
 731 };