2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
34 compatible = "arm,cortex-a7";
40 compatible = "arm,cortex-a7";
46 compatible = "arm,cortex-a7";
52 compatible = "arm,cortex-a7";
59 reg = <0x40000000 0x80000000>;
69 compatible = "fixed-clock";
70 clock-frequency = <24000000>;
75 compatible = "fixed-clock";
76 clock-frequency = <32768>;
77 clock-output-names = "osc32k";
82 compatible = "allwinner,sun6i-a31-pll1-clk";
83 reg = <0x01c20000 0x4>;
85 clock-output-names = "pll1";
90 compatible = "allwinner,sun6i-a31-pll6-clk";
91 reg = <0x01c20028 0x4>;
93 clock-output-names = "pll6";
98 compatible = "allwinner,sun4i-a10-cpu-clk";
99 reg = <0x01c20050 0x4>;
102 * PLL1 is listed twice here.
103 * While it looks suspicious, it's actually documented
104 * that way both in the datasheet and in the code from
107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
108 clock-output-names = "cpu";
113 compatible = "allwinner,sun4i-a10-axi-clk";
114 reg = <0x01c20050 0x4>;
116 clock-output-names = "axi";
119 ahb1_mux: ahb1_mux@01c20054 {
121 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
122 reg = <0x01c20054 0x4>;
123 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
124 clock-output-names = "ahb1_mux";
127 ahb1: ahb1@01c20054 {
129 compatible = "allwinner,sun4i-a10-ahb-clk";
130 reg = <0x01c20054 0x4>;
131 clocks = <&ahb1_mux>;
132 clock-output-names = "ahb1";
135 ahb1_gates: clk@01c20060 {
137 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
138 reg = <0x01c20060 0x8>;
140 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
141 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
142 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
143 "ahb1_nand0", "ahb1_sdram",
144 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
145 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
146 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
147 "ahb1_ehci1", "ahb1_ohci0",
148 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
149 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
150 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
151 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
152 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
153 "ahb1_drc0", "ahb1_drc1";
156 apb1: apb1@01c20054 {
158 compatible = "allwinner,sun4i-a10-apb0-clk";
159 reg = <0x01c20054 0x4>;
161 clock-output-names = "apb1";
164 apb1_gates: clk@01c20068 {
166 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
167 reg = <0x01c20068 0x4>;
169 clock-output-names = "apb1_codec", "apb1_digital_mic",
170 "apb1_pio", "apb1_daudio0",
174 apb2_mux: apb2_mux@01c20058 {
176 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
177 reg = <0x01c20058 0x4>;
178 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
179 clock-output-names = "apb2_mux";
182 apb2: apb2@01c20058 {
184 compatible = "allwinner,sun6i-a31-apb2-div-clk";
185 reg = <0x01c20058 0x4>;
186 clocks = <&apb2_mux>;
187 clock-output-names = "apb2";
190 apb2_gates: clk@01c2006c {
192 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
193 reg = <0x01c2006c 0x4>;
195 clock-output-names = "apb2_i2c0", "apb2_i2c1",
196 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
197 "apb2_uart1", "apb2_uart2", "apb2_uart3",
198 "apb2_uart4", "apb2_uart5";
201 spi0_clk: clk@01c200a0 {
203 compatible = "allwinner,sun4i-a10-mod0-clk";
204 reg = <0x01c200a0 0x4>;
205 clocks = <&osc24M>, <&pll6>;
206 clock-output-names = "spi0";
209 spi1_clk: clk@01c200a4 {
211 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c200a4 0x4>;
213 clocks = <&osc24M>, <&pll6>;
214 clock-output-names = "spi1";
217 spi2_clk: clk@01c200a8 {
219 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c200a8 0x4>;
221 clocks = <&osc24M>, <&pll6>;
222 clock-output-names = "spi2";
225 spi3_clk: clk@01c200ac {
227 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c200ac 0x4>;
229 clocks = <&osc24M>, <&pll6>;
230 clock-output-names = "spi3";
235 compatible = "simple-bus";
236 #address-cells = <1>;
240 pio: pinctrl@01c20800 {
241 compatible = "allwinner,sun6i-a31-pinctrl";
242 reg = <0x01c20800 0x400>;
243 interrupts = <0 11 4>,
247 clocks = <&apb1_gates 5>;
249 interrupt-controller;
250 #address-cells = <1>;
254 uart0_pins_a: uart0@0 {
255 allwinner,pins = "PH20", "PH21";
256 allwinner,function = "uart0";
257 allwinner,drive = <0>;
258 allwinner,pull = <0>;
262 ahb1_rst: reset@01c202c0 {
264 compatible = "allwinner,sun6i-a31-ahb1-reset";
265 reg = <0x01c202c0 0xc>;
268 apb1_rst: reset@01c202d0 {
270 compatible = "allwinner,sun6i-a31-clock-reset";
271 reg = <0x01c202d0 0x4>;
274 apb2_rst: reset@01c202d8 {
276 compatible = "allwinner,sun6i-a31-clock-reset";
277 reg = <0x01c202d8 0x4>;
281 compatible = "allwinner,sun4i-timer";
282 reg = <0x01c20c00 0xa0>;
283 interrupts = <0 18 4>,
291 wdt1: watchdog@01c20ca0 {
292 compatible = "allwinner,sun6i-wdt";
293 reg = <0x01c20ca0 0x20>;
296 uart0: serial@01c28000 {
297 compatible = "snps,dw-apb-uart";
298 reg = <0x01c28000 0x400>;
299 interrupts = <0 0 4>;
302 clocks = <&apb2_gates 16>;
303 resets = <&apb2_rst 16>;
307 uart1: serial@01c28400 {
308 compatible = "snps,dw-apb-uart";
309 reg = <0x01c28400 0x400>;
310 interrupts = <0 1 4>;
313 clocks = <&apb2_gates 17>;
314 resets = <&apb2_rst 17>;
318 uart2: serial@01c28800 {
319 compatible = "snps,dw-apb-uart";
320 reg = <0x01c28800 0x400>;
321 interrupts = <0 2 4>;
324 clocks = <&apb2_gates 18>;
325 resets = <&apb2_rst 18>;
329 uart3: serial@01c28c00 {
330 compatible = "snps,dw-apb-uart";
331 reg = <0x01c28c00 0x400>;
332 interrupts = <0 3 4>;
335 clocks = <&apb2_gates 19>;
336 resets = <&apb2_rst 19>;
340 uart4: serial@01c29000 {
341 compatible = "snps,dw-apb-uart";
342 reg = <0x01c29000 0x400>;
343 interrupts = <0 4 4>;
346 clocks = <&apb2_gates 20>;
347 resets = <&apb2_rst 20>;
351 uart5: serial@01c29400 {
352 compatible = "snps,dw-apb-uart";
353 reg = <0x01c29400 0x400>;
354 interrupts = <0 5 4>;
357 clocks = <&apb2_gates 21>;
358 resets = <&apb2_rst 21>;
363 compatible = "allwinner,sun6i-a31-i2c";
364 reg = <0x01c2ac00 0x400>;
365 interrupts = <0 6 4>;
366 clocks = <&apb2_gates 0>;
367 clock-frequency = <100000>;
368 resets = <&apb2_rst 0>;
373 compatible = "allwinner,sun6i-a31-i2c";
374 reg = <0x01c2b000 0x400>;
375 interrupts = <0 7 4>;
376 clocks = <&apb2_gates 1>;
377 clock-frequency = <100000>;
378 resets = <&apb2_rst 1>;
383 compatible = "allwinner,sun6i-a31-i2c";
384 reg = <0x01c2b400 0x400>;
385 interrupts = <0 8 4>;
386 clocks = <&apb2_gates 2>;
387 clock-frequency = <100000>;
388 resets = <&apb2_rst 2>;
393 compatible = "allwinner,sun6i-a31-i2c";
394 reg = <0x01c2b800 0x400>;
395 interrupts = <0 9 4>;
396 clocks = <&apb2_gates 3>;
397 clock-frequency = <100000>;
398 resets = <&apb2_rst 3>;
403 compatible = "allwinner,sun6i-a31-spi";
404 reg = <0x01c68000 0x1000>;
405 interrupts = <0 65 4>;
406 clocks = <&ahb1_gates 20>, <&spi0_clk>;
407 clock-names = "ahb", "mod";
408 resets = <&ahb1_rst 20>;
413 compatible = "allwinner,sun6i-a31-spi";
414 reg = <0x01c69000 0x1000>;
415 interrupts = <0 66 4>;
416 clocks = <&ahb1_gates 21>, <&spi1_clk>;
417 clock-names = "ahb", "mod";
418 resets = <&ahb1_rst 21>;
423 compatible = "allwinner,sun6i-a31-spi";
424 reg = <0x01c6a000 0x1000>;
425 interrupts = <0 67 4>;
426 clocks = <&ahb1_gates 22>, <&spi2_clk>;
427 clock-names = "ahb", "mod";
428 resets = <&ahb1_rst 22>;
433 compatible = "allwinner,sun6i-a31-spi";
434 reg = <0x01c6b000 0x1000>;
435 interrupts = <0 68 4>;
436 clocks = <&ahb1_gates 23>, <&spi3_clk>;
437 clock-names = "ahb", "mod";
438 resets = <&ahb1_rst 23>;
442 gic: interrupt-controller@01c81000 {
443 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
444 reg = <0x01c81000 0x1000>,
448 interrupt-controller;
449 #interrupt-cells = <3>;
450 interrupts = <1 9 0xf04>;
454 compatible = "allwinner,sun6i-a31-cpuconfig";
455 reg = <0x01f01c00 0x300>;
459 compatible = "allwinner,sun6i-a31-prcm";
460 reg = <0x01f01400 0x200>;