2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
65 compatible = "allwinner,simple-framebuffer",
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "de_be0-lcd0";
82 compatible = "arm,armv7-timer";
83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
87 clock-frequency = <24000000>;
88 arm,cpu-registers-not-fw-configured;
92 enable-method = "allwinner,sun6i-a31";
97 compatible = "arm,cortex-a7";
101 clock-latency = <244144>; /* 8 32k periods */
109 #cooling-cells = <2>;
110 cooling-min-level = <0>;
111 cooling-max-level = <3>;
115 compatible = "arm,cortex-a7";
121 compatible = "arm,cortex-a7";
127 compatible = "arm,cortex-a7";
136 polling-delay-passive = <250>;
137 polling-delay = <1000>;
138 thermal-sensors = <&rtp>;
142 trip = <&cpu_alert0>;
143 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
148 cpu_alert0: cpu_alert0 {
150 temperature = <70000>;
157 temperature = <100000>;
166 reg = <0x40000000 0x80000000>;
170 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
171 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
178 #address-cells = <1>;
184 compatible = "fixed-clock";
185 clock-frequency = <24000000>;
190 compatible = "fixed-clock";
191 clock-frequency = <32768>;
192 clock-output-names = "osc32k";
197 compatible = "allwinner,sun6i-a31-pll1-clk";
198 reg = <0x01c20000 0x4>;
200 clock-output-names = "pll1";
205 compatible = "allwinner,sun6i-a31-pll6-clk";
206 reg = <0x01c20028 0x4>;
208 clock-output-names = "pll6", "pll6x2";
213 compatible = "allwinner,sun4i-a10-cpu-clk";
214 reg = <0x01c20050 0x4>;
217 * PLL1 is listed twice here.
218 * While it looks suspicious, it's actually documented
219 * that way both in the datasheet and in the code from
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
223 clock-output-names = "cpu";
228 compatible = "allwinner,sun4i-a10-axi-clk";
229 reg = <0x01c20050 0x4>;
231 clock-output-names = "axi";
234 ahb1: ahb1@01c20054 {
236 compatible = "allwinner,sun6i-a31-ahb1-clk";
237 reg = <0x01c20054 0x4>;
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
239 clock-output-names = "ahb1";
242 * Clock AHB1 from PLL6, instead of CPU/AXI which
243 * has rate changes due to cpufreq. Also the DMA
244 * controller requires AHB1 clocked from PLL6.
246 assigned-clocks = <&ahb1>;
247 assigned-clock-parents = <&pll6 0>;
250 ahb1_gates: clk@01c20060 {
252 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
253 reg = <0x01c20060 0x8>;
255 clock-indices = <1>, <5>,
269 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
270 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
271 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
272 "ahb1_nand0", "ahb1_sdram",
273 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
274 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
275 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
276 "ahb1_ehci1", "ahb1_ohci0",
277 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
278 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
279 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
280 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
281 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
282 "ahb1_drc0", "ahb1_drc1";
285 apb1: apb1@01c20054 {
287 compatible = "allwinner,sun4i-a10-apb0-clk";
288 reg = <0x01c20054 0x4>;
290 clock-output-names = "apb1";
293 apb1_gates: clk@01c20068 {
295 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
296 reg = <0x01c20068 0x4>;
298 clock-indices = <0>, <4>,
301 clock-output-names = "apb1_codec", "apb1_digital_mic",
302 "apb1_pio", "apb1_daudio0",
308 compatible = "allwinner,sun4i-a10-apb1-clk";
309 reg = <0x01c20058 0x4>;
310 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
311 clock-output-names = "apb2";
314 apb2_gates: clk@01c2006c {
316 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
317 reg = <0x01c2006c 0x4>;
319 clock-indices = <0>, <1>,
323 clock-output-names = "apb2_i2c0", "apb2_i2c1",
324 "apb2_i2c2", "apb2_i2c3",
325 "apb2_uart0", "apb2_uart1",
326 "apb2_uart2", "apb2_uart3",
327 "apb2_uart4", "apb2_uart5";
330 mmc0_clk: clk@01c20088 {
332 compatible = "allwinner,sun4i-a10-mmc-clk";
333 reg = <0x01c20088 0x4>;
334 clocks = <&osc24M>, <&pll6 0>;
335 clock-output-names = "mmc0",
340 mmc1_clk: clk@01c2008c {
342 compatible = "allwinner,sun4i-a10-mmc-clk";
343 reg = <0x01c2008c 0x4>;
344 clocks = <&osc24M>, <&pll6 0>;
345 clock-output-names = "mmc1",
350 mmc2_clk: clk@01c20090 {
352 compatible = "allwinner,sun4i-a10-mmc-clk";
353 reg = <0x01c20090 0x4>;
354 clocks = <&osc24M>, <&pll6 0>;
355 clock-output-names = "mmc2",
360 mmc3_clk: clk@01c20094 {
362 compatible = "allwinner,sun4i-a10-mmc-clk";
363 reg = <0x01c20094 0x4>;
364 clocks = <&osc24M>, <&pll6 0>;
365 clock-output-names = "mmc3",
370 ss_clk: clk@01c2009c {
372 compatible = "allwinner,sun4i-a10-mod0-clk";
373 reg = <0x01c2009c 0x4>;
374 clocks = <&osc24M>, <&pll6 0>;
375 clock-output-names = "ss";
378 spi0_clk: clk@01c200a0 {
380 compatible = "allwinner,sun4i-a10-mod0-clk";
381 reg = <0x01c200a0 0x4>;
382 clocks = <&osc24M>, <&pll6 0>;
383 clock-output-names = "spi0";
386 spi1_clk: clk@01c200a4 {
388 compatible = "allwinner,sun4i-a10-mod0-clk";
389 reg = <0x01c200a4 0x4>;
390 clocks = <&osc24M>, <&pll6 0>;
391 clock-output-names = "spi1";
394 spi2_clk: clk@01c200a8 {
396 compatible = "allwinner,sun4i-a10-mod0-clk";
397 reg = <0x01c200a8 0x4>;
398 clocks = <&osc24M>, <&pll6 0>;
399 clock-output-names = "spi2";
402 spi3_clk: clk@01c200ac {
404 compatible = "allwinner,sun4i-a10-mod0-clk";
405 reg = <0x01c200ac 0x4>;
406 clocks = <&osc24M>, <&pll6 0>;
407 clock-output-names = "spi3";
410 usb_clk: clk@01c200cc {
413 compatible = "allwinner,sun6i-a31-usb-clk";
414 reg = <0x01c200cc 0x4>;
416 clock-indices = <8>, <9>, <10>,
419 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
420 "usb_ohci0", "usb_ohci1",
425 * The following two are dummy clocks, placeholders
426 * used in the gmac_tx clock. The gmac driver will
427 * choose one parent depending on the PHY interface
428 * mode, using clk_set_rate auto-reparenting.
430 * The actual TX clock rate is not controlled by the
433 mii_phy_tx_clk: clk@1 {
435 compatible = "fixed-clock";
436 clock-frequency = <25000000>;
437 clock-output-names = "mii_phy_tx";
440 gmac_int_tx_clk: clk@2 {
442 compatible = "fixed-clock";
443 clock-frequency = <125000000>;
444 clock-output-names = "gmac_int_tx";
447 gmac_tx_clk: clk@01c200d0 {
449 compatible = "allwinner,sun7i-a20-gmac-clk";
450 reg = <0x01c200d0 0x4>;
451 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
452 clock-output-names = "gmac_tx";
457 compatible = "simple-bus";
458 #address-cells = <1>;
462 dma: dma-controller@01c02000 {
463 compatible = "allwinner,sun6i-a31-dma";
464 reg = <0x01c02000 0x1000>;
465 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&ahb1_gates 6>;
467 resets = <&ahb1_rst 6>;
472 compatible = "allwinner,sun5i-a13-mmc";
473 reg = <0x01c0f000 0x1000>;
474 clocks = <&ahb1_gates 8>,
482 resets = <&ahb1_rst 8>;
484 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
491 compatible = "allwinner,sun5i-a13-mmc";
492 reg = <0x01c10000 0x1000>;
493 clocks = <&ahb1_gates 9>,
501 resets = <&ahb1_rst 9>;
503 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>;
510 compatible = "allwinner,sun5i-a13-mmc";
511 reg = <0x01c11000 0x1000>;
512 clocks = <&ahb1_gates 10>,
520 resets = <&ahb1_rst 10>;
522 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
524 #address-cells = <1>;
529 compatible = "allwinner,sun5i-a13-mmc";
530 reg = <0x01c12000 0x1000>;
531 clocks = <&ahb1_gates 11>,
539 resets = <&ahb1_rst 11>;
541 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
543 #address-cells = <1>;
547 usbphy: phy@01c19400 {
548 compatible = "allwinner,sun6i-a31-usb-phy";
549 reg = <0x01c19400 0x10>,
552 reg-names = "phy_ctrl",
555 clocks = <&usb_clk 8>,
558 clock-names = "usb0_phy",
561 resets = <&usb_clk 0>,
564 reset-names = "usb0_reset",
571 ehci0: usb@01c1a000 {
572 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
573 reg = <0x01c1a000 0x100>;
574 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&ahb1_gates 26>;
576 resets = <&ahb1_rst 26>;
582 ohci0: usb@01c1a400 {
583 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
584 reg = <0x01c1a400 0x100>;
585 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
587 resets = <&ahb1_rst 29>;
593 ehci1: usb@01c1b000 {
594 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
595 reg = <0x01c1b000 0x100>;
596 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&ahb1_gates 27>;
598 resets = <&ahb1_rst 27>;
604 ohci1: usb@01c1b400 {
605 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
606 reg = <0x01c1b400 0x100>;
607 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
609 resets = <&ahb1_rst 30>;
615 ohci2: usb@01c1c400 {
616 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
617 reg = <0x01c1c400 0x100>;
618 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
620 resets = <&ahb1_rst 31>;
624 pio: pinctrl@01c20800 {
625 compatible = "allwinner,sun6i-a31-pinctrl";
626 reg = <0x01c20800 0x400>;
627 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&apb1_gates 5>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
638 uart0_pins_a: uart0@0 {
639 allwinner,pins = "PH20", "PH21";
640 allwinner,function = "uart0";
641 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
642 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
645 i2c0_pins_a: i2c0@0 {
646 allwinner,pins = "PH14", "PH15";
647 allwinner,function = "i2c0";
648 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
649 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
652 i2c1_pins_a: i2c1@0 {
653 allwinner,pins = "PH16", "PH17";
654 allwinner,function = "i2c1";
655 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
656 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
659 i2c2_pins_a: i2c2@0 {
660 allwinner,pins = "PH18", "PH19";
661 allwinner,function = "i2c2";
662 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
663 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
666 mmc0_pins_a: mmc0@0 {
667 allwinner,pins = "PF0", "PF1", "PF2",
669 allwinner,function = "mmc0";
670 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
671 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
674 mmc1_pins_a: mmc1@0 {
675 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
677 allwinner,function = "mmc1";
678 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
679 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
682 gmac_pins_mii_a: gmac_mii@0 {
683 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
684 "PA8", "PA9", "PA11",
685 "PA12", "PA13", "PA14", "PA19",
686 "PA20", "PA21", "PA22", "PA23",
687 "PA24", "PA26", "PA27";
688 allwinner,function = "gmac";
689 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
690 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
693 gmac_pins_gmii_a: gmac_gmii@0 {
694 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
695 "PA4", "PA5", "PA6", "PA7",
696 "PA8", "PA9", "PA10", "PA11",
697 "PA12", "PA13", "PA14", "PA15",
698 "PA16", "PA17", "PA18", "PA19",
699 "PA20", "PA21", "PA22", "PA23",
700 "PA24", "PA25", "PA26", "PA27";
701 allwinner,function = "gmac";
703 * data lines in GMII mode run at 125MHz and
704 * might need a higher signal drive strength
706 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
707 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
710 gmac_pins_rgmii_a: gmac_rgmii@0 {
711 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
712 "PA9", "PA10", "PA11",
713 "PA12", "PA13", "PA14", "PA19",
714 "PA20", "PA25", "PA26", "PA27";
715 allwinner,function = "gmac";
717 * data lines in RGMII mode use DDR mode
718 * and need a higher signal drive strength
720 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
721 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
725 ahb1_rst: reset@01c202c0 {
727 compatible = "allwinner,sun6i-a31-ahb1-reset";
728 reg = <0x01c202c0 0xc>;
731 apb1_rst: reset@01c202d0 {
733 compatible = "allwinner,sun6i-a31-clock-reset";
734 reg = <0x01c202d0 0x4>;
737 apb2_rst: reset@01c202d8 {
739 compatible = "allwinner,sun6i-a31-clock-reset";
740 reg = <0x01c202d8 0x4>;
744 compatible = "allwinner,sun4i-a10-timer";
745 reg = <0x01c20c00 0xa0>;
746 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
754 wdt1: watchdog@01c20ca0 {
755 compatible = "allwinner,sun6i-a31-wdt";
756 reg = <0x01c20ca0 0x20>;
760 compatible = "allwinner,sun6i-a31-ts";
761 reg = <0x01c25000 0x100>;
762 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
763 #thermal-sensor-cells = <0>;
766 uart0: serial@01c28000 {
767 compatible = "snps,dw-apb-uart";
768 reg = <0x01c28000 0x400>;
769 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&apb2_gates 16>;
773 resets = <&apb2_rst 16>;
774 dmas = <&dma 6>, <&dma 6>;
775 dma-names = "rx", "tx";
779 uart1: serial@01c28400 {
780 compatible = "snps,dw-apb-uart";
781 reg = <0x01c28400 0x400>;
782 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&apb2_gates 17>;
786 resets = <&apb2_rst 17>;
787 dmas = <&dma 7>, <&dma 7>;
788 dma-names = "rx", "tx";
792 uart2: serial@01c28800 {
793 compatible = "snps,dw-apb-uart";
794 reg = <0x01c28800 0x400>;
795 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&apb2_gates 18>;
799 resets = <&apb2_rst 18>;
800 dmas = <&dma 8>, <&dma 8>;
801 dma-names = "rx", "tx";
805 uart3: serial@01c28c00 {
806 compatible = "snps,dw-apb-uart";
807 reg = <0x01c28c00 0x400>;
808 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&apb2_gates 19>;
812 resets = <&apb2_rst 19>;
813 dmas = <&dma 9>, <&dma 9>;
814 dma-names = "rx", "tx";
818 uart4: serial@01c29000 {
819 compatible = "snps,dw-apb-uart";
820 reg = <0x01c29000 0x400>;
821 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&apb2_gates 20>;
825 resets = <&apb2_rst 20>;
826 dmas = <&dma 10>, <&dma 10>;
827 dma-names = "rx", "tx";
831 uart5: serial@01c29400 {
832 compatible = "snps,dw-apb-uart";
833 reg = <0x01c29400 0x400>;
834 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&apb2_gates 21>;
838 resets = <&apb2_rst 21>;
839 dmas = <&dma 22>, <&dma 22>;
840 dma-names = "rx", "tx";
845 compatible = "allwinner,sun6i-a31-i2c";
846 reg = <0x01c2ac00 0x400>;
847 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&apb2_gates 0>;
849 resets = <&apb2_rst 0>;
851 #address-cells = <1>;
856 compatible = "allwinner,sun6i-a31-i2c";
857 reg = <0x01c2b000 0x400>;
858 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&apb2_gates 1>;
860 resets = <&apb2_rst 1>;
862 #address-cells = <1>;
867 compatible = "allwinner,sun6i-a31-i2c";
868 reg = <0x01c2b400 0x400>;
869 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&apb2_gates 2>;
871 resets = <&apb2_rst 2>;
873 #address-cells = <1>;
878 compatible = "allwinner,sun6i-a31-i2c";
879 reg = <0x01c2b800 0x400>;
880 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&apb2_gates 3>;
882 resets = <&apb2_rst 3>;
884 #address-cells = <1>;
888 gmac: ethernet@01c30000 {
889 compatible = "allwinner,sun7i-a20-gmac";
890 reg = <0x01c30000 0x1054>;
891 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "macirq";
893 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
894 clock-names = "stmmaceth", "allwinner_gmac_tx";
895 resets = <&ahb1_rst 17>;
896 reset-names = "stmmaceth";
899 snps,force_sf_dma_mode;
901 #address-cells = <1>;
905 crypto: crypto-engine@01c15000 {
906 compatible = "allwinner,sun4i-a10-crypto";
907 reg = <0x01c15000 0x1000>;
908 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&ahb1_gates 5>, <&ss_clk>;
910 clock-names = "ahb", "mod";
911 resets = <&ahb1_rst 5>;
916 compatible = "allwinner,sun6i-a31-hstimer",
917 "allwinner,sun7i-a20-hstimer";
918 reg = <0x01c60000 0x1000>;
919 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&ahb1_gates 19>;
924 resets = <&ahb1_rst 19>;
928 compatible = "allwinner,sun6i-a31-spi";
929 reg = <0x01c68000 0x1000>;
930 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&ahb1_gates 20>, <&spi0_clk>;
932 clock-names = "ahb", "mod";
933 dmas = <&dma 23>, <&dma 23>;
934 dma-names = "rx", "tx";
935 resets = <&ahb1_rst 20>;
940 compatible = "allwinner,sun6i-a31-spi";
941 reg = <0x01c69000 0x1000>;
942 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&ahb1_gates 21>, <&spi1_clk>;
944 clock-names = "ahb", "mod";
945 dmas = <&dma 24>, <&dma 24>;
946 dma-names = "rx", "tx";
947 resets = <&ahb1_rst 21>;
952 compatible = "allwinner,sun6i-a31-spi";
953 reg = <0x01c6a000 0x1000>;
954 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&ahb1_gates 22>, <&spi2_clk>;
956 clock-names = "ahb", "mod";
957 dmas = <&dma 25>, <&dma 25>;
958 dma-names = "rx", "tx";
959 resets = <&ahb1_rst 22>;
964 compatible = "allwinner,sun6i-a31-spi";
965 reg = <0x01c6b000 0x1000>;
966 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&ahb1_gates 23>, <&spi3_clk>;
968 clock-names = "ahb", "mod";
969 dmas = <&dma 26>, <&dma 26>;
970 dma-names = "rx", "tx";
971 resets = <&ahb1_rst 23>;
975 gic: interrupt-controller@01c81000 {
976 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
977 reg = <0x01c81000 0x1000>,
981 interrupt-controller;
982 #interrupt-cells = <3>;
983 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
987 compatible = "allwinner,sun6i-a31-rtc";
988 reg = <0x01f00000 0x54>;
989 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
993 nmi_intc: interrupt-controller@01f00c0c {
994 compatible = "allwinner,sun6i-a31-sc-nmi";
995 interrupt-controller;
996 #interrupt-cells = <2>;
997 reg = <0x01f00c0c 0x38>;
998 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1002 compatible = "allwinner,sun6i-a31-prcm";
1003 reg = <0x01f01400 0x200>;
1006 compatible = "allwinner,sun6i-a31-ar100-clk";
1008 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
1010 clock-output-names = "ar100";
1014 compatible = "fixed-factor-clock";
1019 clock-output-names = "ahb0";
1023 compatible = "allwinner,sun6i-a31-apb0-clk";
1026 clock-output-names = "apb0";
1029 apb0_gates: apb0_gates_clk {
1030 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1033 clock-output-names = "apb0_pio", "apb0_ir",
1034 "apb0_timer", "apb0_p2wi",
1035 "apb0_uart", "apb0_1wire",
1041 compatible = "allwinner,sun4i-a10-mod0-clk";
1042 clocks = <&osc32k>, <&osc24M>;
1043 clock-output-names = "ir";
1046 apb0_rst: apb0_rst {
1047 compatible = "allwinner,sun6i-a31-clock-reset";
1053 compatible = "allwinner,sun6i-a31-cpuconfig";
1054 reg = <0x01f01c00 0x300>;
1058 compatible = "allwinner,sun5i-a13-ir";
1059 clocks = <&apb0_gates 1>, <&ir_clk>;
1060 clock-names = "apb", "ir";
1061 resets = <&apb0_rst 1>;
1062 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1063 reg = <0x01f02000 0x40>;
1064 status = "disabled";
1067 r_pio: pinctrl@01f02c00 {
1068 compatible = "allwinner,sun6i-a31-r-pinctrl";
1069 reg = <0x01f02c00 0x400>;
1070 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1071 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&apb0_gates 0>;
1073 resets = <&apb0_rst 0>;
1075 interrupt-controller;
1076 #interrupt-cells = <2>;
1081 allwinner,pins = "PL4";
1082 allwinner,function = "s_ir";
1083 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1084 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1088 allwinner,pins = "PL0", "PL1";
1089 allwinner,function = "s_p2wi";
1090 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1091 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1095 p2wi: i2c@01f03400 {
1096 compatible = "allwinner,sun6i-a31-p2wi";
1097 reg = <0x01f03400 0x400>;
1098 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&apb0_gates 3>;
1100 clock-frequency = <100000>;
1101 resets = <&apb0_rst 3>;
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&p2wi_pins>;
1104 status = "disabled";
1105 #address-cells = <1>;