2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
65 compatible = "allwinner,simple-framebuffer",
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "de_be0-lcd0";
82 compatible = "arm,armv7-timer";
83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
87 clock-frequency = <24000000>;
88 arm,cpu-registers-not-fw-configured;
92 enable-method = "allwinner,sun6i-a31";
97 compatible = "arm,cortex-a7";
101 clock-latency = <244144>; /* 8 32k periods */
109 #cooling-cells = <2>;
110 cooling-min-level = <0>;
111 cooling-max-level = <3>;
115 compatible = "arm,cortex-a7";
121 compatible = "arm,cortex-a7";
127 compatible = "arm,cortex-a7";
136 polling-delay-passive = <250>;
137 polling-delay = <1000>;
138 thermal-sensors = <&rtp>;
142 trip = <&cpu_alert0>;
143 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
148 cpu_alert0: cpu_alert0 {
150 temperature = <70000>;
157 temperature = <100000>;
166 reg = <0x40000000 0x80000000>;
170 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
171 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
178 #address-cells = <1>;
184 compatible = "fixed-clock";
185 clock-frequency = <24000000>;
190 compatible = "fixed-clock";
191 clock-frequency = <32768>;
192 clock-output-names = "osc32k";
197 compatible = "allwinner,sun6i-a31-pll1-clk";
198 reg = <0x01c20000 0x4>;
200 clock-output-names = "pll1";
205 compatible = "allwinner,sun6i-a31-pll6-clk";
206 reg = <0x01c20028 0x4>;
208 clock-output-names = "pll6", "pll6x2";
213 compatible = "allwinner,sun4i-a10-cpu-clk";
214 reg = <0x01c20050 0x4>;
217 * PLL1 is listed twice here.
218 * While it looks suspicious, it's actually documented
219 * that way both in the datasheet and in the code from
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
223 clock-output-names = "cpu";
228 compatible = "allwinner,sun4i-a10-axi-clk";
229 reg = <0x01c20050 0x4>;
231 clock-output-names = "axi";
234 ahb1: ahb1@01c20054 {
236 compatible = "allwinner,sun6i-a31-ahb1-clk";
237 reg = <0x01c20054 0x4>;
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
239 clock-output-names = "ahb1";
242 * Clock AHB1 from PLL6, instead of CPU/AXI which
243 * has rate changes due to cpufreq. Also the DMA
244 * controller requires AHB1 clocked from PLL6.
246 assigned-clocks = <&ahb1>;
247 assigned-clock-parents = <&pll6 0>;
250 ahb1_gates: clk@01c20060 {
252 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
253 reg = <0x01c20060 0x8>;
255 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
256 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
257 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
258 "ahb1_nand0", "ahb1_sdram",
259 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
260 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
261 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
262 "ahb1_ehci1", "ahb1_ohci0",
263 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
264 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
265 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
266 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
267 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
268 "ahb1_drc0", "ahb1_drc1";
271 apb1: apb1@01c20054 {
273 compatible = "allwinner,sun4i-a10-apb0-clk";
274 reg = <0x01c20054 0x4>;
276 clock-output-names = "apb1";
279 apb1_gates: clk@01c20068 {
281 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
282 reg = <0x01c20068 0x4>;
284 clock-output-names = "apb1_codec", "apb1_digital_mic",
285 "apb1_pio", "apb1_daudio0",
291 compatible = "allwinner,sun4i-a10-apb1-clk";
292 reg = <0x01c20058 0x4>;
293 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
294 clock-output-names = "apb2";
297 apb2_gates: clk@01c2006c {
299 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
300 reg = <0x01c2006c 0x4>;
302 clock-output-names = "apb2_i2c0", "apb2_i2c1",
303 "apb2_i2c2", "apb2_i2c3",
304 "apb2_uart0", "apb2_uart1",
305 "apb2_uart2", "apb2_uart3",
306 "apb2_uart4", "apb2_uart5";
309 mmc0_clk: clk@01c20088 {
311 compatible = "allwinner,sun4i-a10-mmc-clk";
312 reg = <0x01c20088 0x4>;
313 clocks = <&osc24M>, <&pll6 0>;
314 clock-output-names = "mmc0",
319 mmc1_clk: clk@01c2008c {
321 compatible = "allwinner,sun4i-a10-mmc-clk";
322 reg = <0x01c2008c 0x4>;
323 clocks = <&osc24M>, <&pll6 0>;
324 clock-output-names = "mmc1",
329 mmc2_clk: clk@01c20090 {
331 compatible = "allwinner,sun4i-a10-mmc-clk";
332 reg = <0x01c20090 0x4>;
333 clocks = <&osc24M>, <&pll6 0>;
334 clock-output-names = "mmc2",
339 mmc3_clk: clk@01c20094 {
341 compatible = "allwinner,sun4i-a10-mmc-clk";
342 reg = <0x01c20094 0x4>;
343 clocks = <&osc24M>, <&pll6 0>;
344 clock-output-names = "mmc3",
349 spi0_clk: clk@01c200a0 {
351 compatible = "allwinner,sun4i-a10-mod0-clk";
352 reg = <0x01c200a0 0x4>;
353 clocks = <&osc24M>, <&pll6 0>;
354 clock-output-names = "spi0";
357 spi1_clk: clk@01c200a4 {
359 compatible = "allwinner,sun4i-a10-mod0-clk";
360 reg = <0x01c200a4 0x4>;
361 clocks = <&osc24M>, <&pll6 0>;
362 clock-output-names = "spi1";
365 spi2_clk: clk@01c200a8 {
367 compatible = "allwinner,sun4i-a10-mod0-clk";
368 reg = <0x01c200a8 0x4>;
369 clocks = <&osc24M>, <&pll6 0>;
370 clock-output-names = "spi2";
373 spi3_clk: clk@01c200ac {
375 compatible = "allwinner,sun4i-a10-mod0-clk";
376 reg = <0x01c200ac 0x4>;
377 clocks = <&osc24M>, <&pll6 0>;
378 clock-output-names = "spi3";
381 usb_clk: clk@01c200cc {
384 compatible = "allwinner,sun6i-a31-usb-clk";
385 reg = <0x01c200cc 0x4>;
387 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
388 "usb_ohci0", "usb_ohci1",
393 * The following two are dummy clocks, placeholders
394 * used in the gmac_tx clock. The gmac driver will
395 * choose one parent depending on the PHY interface
396 * mode, using clk_set_rate auto-reparenting.
398 * The actual TX clock rate is not controlled by the
401 mii_phy_tx_clk: clk@1 {
403 compatible = "fixed-clock";
404 clock-frequency = <25000000>;
405 clock-output-names = "mii_phy_tx";
408 gmac_int_tx_clk: clk@2 {
410 compatible = "fixed-clock";
411 clock-frequency = <125000000>;
412 clock-output-names = "gmac_int_tx";
415 gmac_tx_clk: clk@01c200d0 {
417 compatible = "allwinner,sun7i-a20-gmac-clk";
418 reg = <0x01c200d0 0x4>;
419 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
420 clock-output-names = "gmac_tx";
425 compatible = "simple-bus";
426 #address-cells = <1>;
430 dma: dma-controller@01c02000 {
431 compatible = "allwinner,sun6i-a31-dma";
432 reg = <0x01c02000 0x1000>;
433 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&ahb1_gates 6>;
435 resets = <&ahb1_rst 6>;
440 compatible = "allwinner,sun5i-a13-mmc";
441 reg = <0x01c0f000 0x1000>;
442 clocks = <&ahb1_gates 8>,
450 resets = <&ahb1_rst 8>;
452 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
459 compatible = "allwinner,sun5i-a13-mmc";
460 reg = <0x01c10000 0x1000>;
461 clocks = <&ahb1_gates 9>,
469 resets = <&ahb1_rst 9>;
471 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
478 compatible = "allwinner,sun5i-a13-mmc";
479 reg = <0x01c11000 0x1000>;
480 clocks = <&ahb1_gates 10>,
488 resets = <&ahb1_rst 10>;
490 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <1>;
497 compatible = "allwinner,sun5i-a13-mmc";
498 reg = <0x01c12000 0x1000>;
499 clocks = <&ahb1_gates 11>,
507 resets = <&ahb1_rst 11>;
509 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
511 #address-cells = <1>;
515 usb_otg: usb@01c19000 {
516 compatible = "allwinner,sun6i-a31-musb";
517 reg = <0x01c19000 0x0400>;
518 clocks = <&ahb1_gates 24>;
519 resets = <&ahb1_rst 24>;
520 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
521 interrupt-names = "mc";
524 extcon = <&usbphy 0>;
528 usbphy: phy@01c19400 {
529 compatible = "allwinner,sun6i-a31-usb-phy";
530 reg = <0x01c19400 0x10>,
533 reg-names = "phy_ctrl",
536 clocks = <&usb_clk 8>,
539 clock-names = "usb0_phy",
542 resets = <&usb_clk 0>,
545 reset-names = "usb0_reset",
552 ehci0: usb@01c1a000 {
553 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
554 reg = <0x01c1a000 0x100>;
555 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&ahb1_gates 26>;
557 resets = <&ahb1_rst 26>;
563 ohci0: usb@01c1a400 {
564 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
565 reg = <0x01c1a400 0x100>;
566 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
568 resets = <&ahb1_rst 29>;
574 ehci1: usb@01c1b000 {
575 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
576 reg = <0x01c1b000 0x100>;
577 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&ahb1_gates 27>;
579 resets = <&ahb1_rst 27>;
585 ohci1: usb@01c1b400 {
586 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
587 reg = <0x01c1b400 0x100>;
588 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
590 resets = <&ahb1_rst 30>;
596 ohci2: usb@01c1c400 {
597 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
598 reg = <0x01c1c400 0x100>;
599 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
601 resets = <&ahb1_rst 31>;
605 pio: pinctrl@01c20800 {
606 compatible = "allwinner,sun6i-a31-pinctrl";
607 reg = <0x01c20800 0x400>;
608 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&apb1_gates 5>;
614 interrupt-controller;
615 #interrupt-cells = <3>;
618 uart0_pins_a: uart0@0 {
619 allwinner,pins = "PH20", "PH21";
620 allwinner,function = "uart0";
621 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
622 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
625 i2c0_pins_a: i2c0@0 {
626 allwinner,pins = "PH14", "PH15";
627 allwinner,function = "i2c0";
628 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
629 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
632 i2c1_pins_a: i2c1@0 {
633 allwinner,pins = "PH16", "PH17";
634 allwinner,function = "i2c1";
635 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
636 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
639 i2c2_pins_a: i2c2@0 {
640 allwinner,pins = "PH18", "PH19";
641 allwinner,function = "i2c2";
642 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
643 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
646 mmc0_pins_a: mmc0@0 {
647 allwinner,pins = "PF0", "PF1", "PF2",
649 allwinner,function = "mmc0";
650 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
651 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
654 mmc1_pins_a: mmc1@0 {
655 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
657 allwinner,function = "mmc1";
658 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
659 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
662 gmac_pins_mii_a: gmac_mii@0 {
663 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
664 "PA8", "PA9", "PA11",
665 "PA12", "PA13", "PA14", "PA19",
666 "PA20", "PA21", "PA22", "PA23",
667 "PA24", "PA26", "PA27";
668 allwinner,function = "gmac";
669 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
670 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
673 gmac_pins_gmii_a: gmac_gmii@0 {
674 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
675 "PA4", "PA5", "PA6", "PA7",
676 "PA8", "PA9", "PA10", "PA11",
677 "PA12", "PA13", "PA14", "PA15",
678 "PA16", "PA17", "PA18", "PA19",
679 "PA20", "PA21", "PA22", "PA23",
680 "PA24", "PA25", "PA26", "PA27";
681 allwinner,function = "gmac";
683 * data lines in GMII mode run at 125MHz and
684 * might need a higher signal drive strength
686 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
687 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
690 gmac_pins_rgmii_a: gmac_rgmii@0 {
691 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
692 "PA9", "PA10", "PA11",
693 "PA12", "PA13", "PA14", "PA19",
694 "PA20", "PA25", "PA26", "PA27";
695 allwinner,function = "gmac";
697 * data lines in RGMII mode use DDR mode
698 * and need a higher signal drive strength
700 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
701 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
705 ahb1_rst: reset@01c202c0 {
707 compatible = "allwinner,sun6i-a31-ahb1-reset";
708 reg = <0x01c202c0 0xc>;
711 apb1_rst: reset@01c202d0 {
713 compatible = "allwinner,sun6i-a31-clock-reset";
714 reg = <0x01c202d0 0x4>;
717 apb2_rst: reset@01c202d8 {
719 compatible = "allwinner,sun6i-a31-clock-reset";
720 reg = <0x01c202d8 0x4>;
724 compatible = "allwinner,sun4i-a10-timer";
725 reg = <0x01c20c00 0xa0>;
726 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
734 wdt1: watchdog@01c20ca0 {
735 compatible = "allwinner,sun6i-a31-wdt";
736 reg = <0x01c20ca0 0x20>;
740 compatible = "allwinner,sun6i-a31-ts";
741 reg = <0x01c25000 0x100>;
742 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
743 #thermal-sensor-cells = <0>;
746 uart0: serial@01c28000 {
747 compatible = "snps,dw-apb-uart";
748 reg = <0x01c28000 0x400>;
749 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&apb2_gates 16>;
753 resets = <&apb2_rst 16>;
754 dmas = <&dma 6>, <&dma 6>;
755 dma-names = "rx", "tx";
759 uart1: serial@01c28400 {
760 compatible = "snps,dw-apb-uart";
761 reg = <0x01c28400 0x400>;
762 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&apb2_gates 17>;
766 resets = <&apb2_rst 17>;
767 dmas = <&dma 7>, <&dma 7>;
768 dma-names = "rx", "tx";
772 uart2: serial@01c28800 {
773 compatible = "snps,dw-apb-uart";
774 reg = <0x01c28800 0x400>;
775 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&apb2_gates 18>;
779 resets = <&apb2_rst 18>;
780 dmas = <&dma 8>, <&dma 8>;
781 dma-names = "rx", "tx";
785 uart3: serial@01c28c00 {
786 compatible = "snps,dw-apb-uart";
787 reg = <0x01c28c00 0x400>;
788 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&apb2_gates 19>;
792 resets = <&apb2_rst 19>;
793 dmas = <&dma 9>, <&dma 9>;
794 dma-names = "rx", "tx";
798 uart4: serial@01c29000 {
799 compatible = "snps,dw-apb-uart";
800 reg = <0x01c29000 0x400>;
801 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&apb2_gates 20>;
805 resets = <&apb2_rst 20>;
806 dmas = <&dma 10>, <&dma 10>;
807 dma-names = "rx", "tx";
811 uart5: serial@01c29400 {
812 compatible = "snps,dw-apb-uart";
813 reg = <0x01c29400 0x400>;
814 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&apb2_gates 21>;
818 resets = <&apb2_rst 21>;
819 dmas = <&dma 22>, <&dma 22>;
820 dma-names = "rx", "tx";
825 compatible = "allwinner,sun6i-a31-i2c";
826 reg = <0x01c2ac00 0x400>;
827 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&apb2_gates 0>;
829 resets = <&apb2_rst 0>;
831 #address-cells = <1>;
836 compatible = "allwinner,sun6i-a31-i2c";
837 reg = <0x01c2b000 0x400>;
838 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&apb2_gates 1>;
840 resets = <&apb2_rst 1>;
842 #address-cells = <1>;
847 compatible = "allwinner,sun6i-a31-i2c";
848 reg = <0x01c2b400 0x400>;
849 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&apb2_gates 2>;
851 resets = <&apb2_rst 2>;
853 #address-cells = <1>;
858 compatible = "allwinner,sun6i-a31-i2c";
859 reg = <0x01c2b800 0x400>;
860 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&apb2_gates 3>;
862 resets = <&apb2_rst 3>;
864 #address-cells = <1>;
868 gmac: ethernet@01c30000 {
869 compatible = "allwinner,sun7i-a20-gmac";
870 reg = <0x01c30000 0x1054>;
871 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
872 interrupt-names = "macirq";
873 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
874 clock-names = "stmmaceth", "allwinner_gmac_tx";
875 resets = <&ahb1_rst 17>;
876 reset-names = "stmmaceth";
879 snps,force_sf_dma_mode;
881 #address-cells = <1>;
886 compatible = "allwinner,sun6i-a31-hstimer",
887 "allwinner,sun7i-a20-hstimer";
888 reg = <0x01c60000 0x1000>;
889 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&ahb1_gates 19>;
894 resets = <&ahb1_rst 19>;
898 compatible = "allwinner,sun6i-a31-spi";
899 reg = <0x01c68000 0x1000>;
900 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&ahb1_gates 20>, <&spi0_clk>;
902 clock-names = "ahb", "mod";
903 dmas = <&dma 23>, <&dma 23>;
904 dma-names = "rx", "tx";
905 resets = <&ahb1_rst 20>;
910 compatible = "allwinner,sun6i-a31-spi";
911 reg = <0x01c69000 0x1000>;
912 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&ahb1_gates 21>, <&spi1_clk>;
914 clock-names = "ahb", "mod";
915 dmas = <&dma 24>, <&dma 24>;
916 dma-names = "rx", "tx";
917 resets = <&ahb1_rst 21>;
922 compatible = "allwinner,sun6i-a31-spi";
923 reg = <0x01c6a000 0x1000>;
924 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&ahb1_gates 22>, <&spi2_clk>;
926 clock-names = "ahb", "mod";
927 dmas = <&dma 25>, <&dma 25>;
928 dma-names = "rx", "tx";
929 resets = <&ahb1_rst 22>;
934 compatible = "allwinner,sun6i-a31-spi";
935 reg = <0x01c6b000 0x1000>;
936 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&ahb1_gates 23>, <&spi3_clk>;
938 clock-names = "ahb", "mod";
939 dmas = <&dma 26>, <&dma 26>;
940 dma-names = "rx", "tx";
941 resets = <&ahb1_rst 23>;
945 gic: interrupt-controller@01c81000 {
946 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
947 reg = <0x01c81000 0x1000>,
951 interrupt-controller;
952 #interrupt-cells = <3>;
953 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
957 compatible = "allwinner,sun6i-a31-rtc";
958 reg = <0x01f00000 0x54>;
959 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
963 nmi_intc: interrupt-controller@01f00c0c {
964 compatible = "allwinner,sun6i-a31-sc-nmi";
965 interrupt-controller;
966 #interrupt-cells = <2>;
967 reg = <0x01f00c0c 0x38>;
968 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
972 compatible = "allwinner,sun6i-a31-prcm";
973 reg = <0x01f01400 0x200>;
976 compatible = "allwinner,sun6i-a31-ar100-clk";
978 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
980 clock-output-names = "ar100";
984 compatible = "fixed-factor-clock";
989 clock-output-names = "ahb0";
993 compatible = "allwinner,sun6i-a31-apb0-clk";
996 clock-output-names = "apb0";
999 apb0_gates: apb0_gates_clk {
1000 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1003 clock-output-names = "apb0_pio", "apb0_ir",
1004 "apb0_timer", "apb0_p2wi",
1005 "apb0_uart", "apb0_1wire",
1011 compatible = "allwinner,sun4i-a10-mod0-clk";
1012 clocks = <&osc32k>, <&osc24M>;
1013 clock-output-names = "ir";
1016 apb0_rst: apb0_rst {
1017 compatible = "allwinner,sun6i-a31-clock-reset";
1023 compatible = "allwinner,sun6i-a31-cpuconfig";
1024 reg = <0x01f01c00 0x300>;
1028 compatible = "allwinner,sun5i-a13-ir";
1029 clocks = <&apb0_gates 1>, <&ir_clk>;
1030 clock-names = "apb", "ir";
1031 resets = <&apb0_rst 1>;
1032 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1033 reg = <0x01f02000 0x40>;
1034 status = "disabled";
1037 r_pio: pinctrl@01f02c00 {
1038 compatible = "allwinner,sun6i-a31-r-pinctrl";
1039 reg = <0x01f02c00 0x400>;
1040 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&apb0_gates 0>;
1043 resets = <&apb0_rst 0>;
1045 interrupt-controller;
1046 #interrupt-cells = <2>;
1051 allwinner,pins = "PL4";
1052 allwinner,function = "s_ir";
1053 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1054 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1058 allwinner,pins = "PL0", "PL1";
1059 allwinner,function = "s_p2wi";
1060 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1061 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1065 p2wi: i2c@01f03400 {
1066 compatible = "allwinner,sun6i-a31-p2wi";
1067 reg = <0x01f03400 0x400>;
1068 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&apb0_gates 3>;
1070 clock-frequency = <100000>;
1071 resets = <&apb0_rst 3>;
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&p2wi_pins>;
1074 status = "disabled";
1075 #address-cells = <1>;